2011-12-14  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (html/synch, $(DESTDIR)$(htmldir)synch): HTML generated
	by `makeinfo --html'.

2011-10-25  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (snapdir, infodir, htmldir): Added defaults so make
	works with empty "config.status".

2010-06-29  Aubrey Jaffer  <jaffer@dv7>

	* Makefile (VERSION): Bumped from 1c4 to 1c5.

2010-06-19  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile: INSTALL_INFO = ginstall-info

2010-06-02  Aubrey Jaffer  <agj@alum.mit.edu>

	* configure: Improved portability of trailing / detection.

2010-05-22  Aubrey Jaffer  <agj@alum.mit.edu>

	* configure (ac_default_prefix): Was lacking trailing /.

2010-02-23  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (Makefile): Runs ./configure to create config.status.

2010-02-13  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile: Reorganized per <http://www.gnu.org/prep/standards/>.

2010-02-04  Aubrey Jaffer  <agj@alum.mit.edu>

	* configure: GNU-style configuration for installation creates
	config.status, which is included by Makefile.

2009-08-02  Aubrey Jaffer  <jaffer@localhost.localdomain>

	* Makefile (VERSION): Bumped from 1c3 to 1c4.

2008-02-01  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1c2 to 1c3.

2008-01-31  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile: Always put - between synch and version.

2008-01-16  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (RSYNC): --rsync-path no longer needed.

2007-11-23  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1c1 to 1c2.

2007-09-04  Aubrey Jaffer  <agj@alum.mit.edu>

	*: Updated license notices to GPL 3.

	* COPYING: Updated to GPL-3.0.

	* Makefile (srcdir.mk): Removed.
	(install*): Added $(DESTDIR) prefix.

2007-06-08  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (synch.info, temp/synch): Changed to use "mkdir -p".

2006-10-21  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1b9 to 1c1.

2006-08-10  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (dvi, pdf): New tetex-3.0(-20.FC5) broke them -- fixed.

2006-05-15  Aubrey Jaffer  <agj@alum.mit.edu>

	* synch.texi: Converted to use @copying.

	* Makefile (docs): Added.
	(infodir): Added / suffix.

2005-06-22  Aubrey Jaffer  <jaffer@aubrey>

	* Makefile (VERSION): Bumped from 1b8 to 1b9.

2005-01-09  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vrlg.scm (translate-exp)
	* scm2vhdl.scm (out-number): reverse-bit-field changed from
	bit-reverse (SRFI-60).

	* synch.texi (Functional Design): Change argument order to
	copy-bit-field per SRFI-60.

2005-01-08  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm, scm2vrlg.scm (translate-exp): ARITHMETIC-SHIFT
	aliases ASH.

	* logic.scm (vector-bounds): ARITHMETIC-SHIFT aliases ASH.

2004-01-14  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (srcdir.mk): Include after target.
	Separated shell assignments and exports.

2003-11-29  Aubrey Jaffer  <jaffer@scm.jaffer>

	* Makefile (VERSION): Bumped from 1b7 to 1b8.

2003-10-30  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (version.txi): Regenerate only for "make new".

2003-10-29  Aubrey Jaffer  <agj@alum.mit.edu>

	* run.scm, scm2vhdl.scm, scm2vrlg.scm, simsynch.scm
	(for-each-row-in-order): Use instead of FOR-EACH-ROW.

2003-10-15    <agj@alum.mit.edu>

	* scm2vhdl.scm (generate-top-file): Recoded use of @print.

2003-07-16  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (release): make synch.pdf.

2003-06-25  Aubrey Jaffer  <agj@alum.mit.edu>

	* fifo8.scm: Output verilog also.

	* Makefile (tagfiles): Added scm2vrlg.scm.

	* scm2vrlg.scm (generate-module-header): Fixed typo.
	(generate-stimulus-file): Shortened file name (_stim.v).

2003-06-22  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1b6 to 1b7.

2003-06-22  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (synch_toc.html): Restored.
	(synch$(VERSION).info): Added --no-warn.

	* fifo8.scm: Added trivial SimSynch FIFO design example.

	* uart.scm (stim:read, stim:write): Added stim sequence.
	Added nontrivial SimSynch design example in progress.

	* run.scm (translate): Moved translator mapping to usercat.
	Added solidify-database call.

	* usercat (machxl, verilog, vhdl): Added translator features.

	* synch.texi (Infrastructure): Added text about database hygiene.

	* simsynch.scm (define-synchronous-system): Don't
	solidify-database; screwed multi-block designs.
	(create-board): Give error message if db-file locked.

2003-06-20  Aubrey Jaffer  <agj@alum.mit.edu>

	* models.scm (fifo:clear): array-fill! <- uniform-vector-fill!.

2002-03-25  aj@cypress.com  <jaffer@aubrey.cypress.com>

	* scm2vhdl.scm (infix-translate-pairwise):
	Added to fix multi-argument comparisons;
	replaces translate-<> and translate-=.

2002-03-20    <aj@cypress.com>

	* logical.vhd: (Copyright): Added with SLIB-like license.

2002-03-15    <aj@cypress.com>

	* logical.vhd (Must_Be_Valid): Suppress errors during first 10.ns
	of simulation.

2002-02-11  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1b5 to 1b6.

2002-01-31  Aubrey Jaffer  <agj@alum.mit.edu>

	* models.scm (integer->prototype): Added to support SLIB arrays.

	* simsynch.scm (synch:countsave, synch:prinsave, synch:chatsave):
	Converted to use create-array.

2002-01-20  Aubrey Jaffer  <agj@alum.mit.edu>

	* synch.texi (Translation): QASE renamed from CASEV.

	* scm2vhdl.scm, logic.scm (qase): Added alias for casev.

2002-01-19  Aubrey Jaffer  <agj@alum.mit.edu>

	* logic.scm (qase): Renamed from casev.

	* simsynch.scm (define-synchronous-system): Use solidify-database.

2001-12-18  Aubrey Jaffer  <agj@alum.mit.edu>

	* logical.vhd: "synopsys translate_off" Functions with ASSERT.
	Variable initializations moved to function bodies to supress
	warnings from brain-dead analysis programs.

2001-12-06  Aubrey Jaffer  <agj@alum.mit.edu>

	* simsynch.scm (create-board): Updated for SLIB change.

2001-12-03  Christopher Holmes  <cgholmes@rcn.com>

	* logical.vhd (Must_Be_Valid): Made it work for arbitrary width
	 argument.

2001-11-29  Aubrey Jaffer  <agj@alum.mit.edu>

	* logical.vhd (Must_Be_Valid): Added procedure; checks each bit of
	vector is '0' or '1'.

2001-11-11  Aubrey Jaffer  <agj@alum.mit.edu>

	* logic.scm (bit-reverse, gray*): Moved to SLIB/logical.scm.

2001-11-07  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (out-convert): Replaced uses of
	Conv_Std_Logic_Vector with Std_Logic_Vector of
	Conv_Std_Logic_Vector.

	* logical.vhd (Conv_Unsigned): Take STD_LOGIC_VECTOR argument.
	Replaced uses of Conv_Std_Logic_Vector with Std_Logic_Vector of
	Conv_Std_Logic_Vector.

2001-11-05  Aubrey Jaffer  <agj@alum.mit.edu>

	* synch.texi (Macros for Signals and Pins): synch:defshare fixed.

	* scm2vhdl.scm (translate-tag): Fixed synchronous resets.

2001-06-12    <ajaffer@scanlogic.com>

	* models.scm (make-sync-ram, make-sync-ram-array): Added aliases.

	* scm2vhdl.scm (process-rams): Fixed for changed ram-table fields.

2001-06-05    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (case-neval): SELECTs are less picky than CASE!

2001-06-04    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-convert): *xxxx* translated 'x' or "xxxx..".
	(translate-tag): Use short IF instead of *xxxx* for inits.
	(case-eval): EVAL if not just ,<symbol>.

2001-05-31    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (generate-top-file): Renamed testbench to tb; takes
	less room in simulator windows.

2001-05-30    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (generate-wave.do): Added.
	(out-convert): Fixed missing NOT for plain symbols.
	(out-stimulus-process): Fixed line_number.

	* run.scm (dump:vhdl): Mark uses of spew signals.

	* simsynch.scm (call-with-classified-pins): Do spew signals.

2001-05-29    <ajaffer@scanlogic.com>

	* run.scm (spew-list): remove duplicates.

2001-05-23    <ajaffer@scanlogic.com>

	* run.scm (print-nets): Removed 'U' chip prefix.

	* scm2vhdl.scm (translate-select-clause): Allow expressions for
	"WHEN".

	* simsynch.scm (synch:define-pin): Take comments if present.

	* scm2vhdl.scm (out-assignment): Fixed ELSE in CASEV clauses.

2001-05-22  Aubrey Jaffer  <agj@alum.mit.edu>

	* simsynch.scm (synch:defshare): Made backward compatible.

	* logic.scm (comment?): Added.

2001-05-16  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (pdf): Added targets.

2001-05-16    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-rhs, out-convert): Split from OUT-ASSIGNMENT.
	(translate-select-clause): Generates WHEN-ELSE and WITH-SECECT
	statements at top level of macro definitions.

2001-05-14    <ajaffer@scanlogic.com>

	* simsynch.scm (synch:prin1): Use "??" and "  " for *xxxx* and
	floating states.

	* scm2vhdl.scm (out-stimulus-process): Removed order requirement
	from spew-list.

	* run.scm (spew-list): Simplified

2001-05-11    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (optionally-parenthesize): Pad if needed for width.
	(infix-translate-arith): Calculate maximum vector width argument;
	pass to optionally-parenthesize.

	* readtext.vhd (Read): Use std_logic characters to encode state.

	* logic.scm (vector-bounds): Handle LOGAND and booleans.

2001-05-11  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (out-stimulus-process): Assert RESET while reading
	spew header.

	* run.scm (spew:prin-header): Added.

2001-05-10    <ajaffer@scanlogic.com>

	* run.scm (spew:vhdl): First line of file has signal names.  Last
	two columns are cycle number and elapsed time.

	* scm2vhdl.scm (tcq-semi): All assignments have AFTER clauses.
	(out-stimulus-process): Clock times from frequency parameter.

2001-05-10  Aubrey Jaffer  <agj@alum.mit.edu>

	* logic.scm (nibble0, nibble1, nibble2, nibble3): Added functions
	for numbers less than a byte wide.

	* simsynch.scm (synch:print): Automatically split vectorized
	signals.

2001-05-09    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-assignment): Array references are already
	To_StdLogicVector; removed gratuituos Conv_Std_Logic_Vector.
	(translate-constant-definition): Don't translate *xxxx*.
	(out-stimulus-process): Each SIGNAL now has own tmp_ variable.
	Ignores both 'X' and 'Z' values in .dat file.

	* readtext.vhd(Read): Added std_ulogic case.

	* logic.scm (vector-bounds): Right index change not when shifting!
	Groks IF.

2001-05-09  Aubrey Jaffer  <agj@alum.mit.edu>

	* run.scm (spew-list): Added block and frequency.

	* scm2vhdl.scm (out-stimulus-process): Generate plausible WAITs
	for clock frequency.

2001-05-08  Aubrey Jaffer  <agj@alum.mit.edu>

	* logical.vhd (rShift): fixed.

2001-05-08    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-stimulus-process): Extracted from
	generate-stimulus-file; fixed many problems.  Eliminated VHDL-93
	syntax for "FILE".
	(generate-stimulus-file): fixed declarations.

	* simsynch.scm (define-synchronous-system): Also MARK-USES of
	initializers.

2001-05-08  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (out-assignment): Now handles LHS also.
	Array type now BIT_VECTOR.
	(translate-exp): BYTE-REF and INTEGER->CHAR added.

2001-05-07    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-decls): Don't repeat identical array defines.
	(out-busses out-components out-instantiations): Extracted common
	code.
	Added LIFT? flag to *tris* specs.

2001-05-06  Aubrey Jaffer  <agj@alum.mit.edu>

	* simsynch.scm (call-with-classified-pins): Fixed INPUT/OUTPUT.

	* scm2vhdl.scm (generate-standard-includes): Added descriptions of
	functions from "logical.vhd".

	* simsynch.scm (used-by-other-ptags?): Only consider references to
	explicitly declared ptags.

	* run.scm (print-nets): Changed name of internal ptag INT to HID.

2001-05-04    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-design): Merged main and "_stim" files.

	* logic.scm (ptag-stripped): Don't be fooled by bit-vectors.

2001-05-03  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (out-bus, translate-exp): Support character ('Z')
	constants.

2001-05-02    <ajaffer@scanlogic.com>

	* simsynch.scm (synch:defshare): Fixed.  Takes single argument.
	(synch:define-bus): Allow NAME to have prefix.

	* scm2vhdl.scm (set-diff): Now incorporates REVERSE.

2001-05-01    <ajaffer@scanlogic.com>

	* simsynch.scm (call-with-classified-pins): Treat CLOCK as INPUT.

	* scm2vhdl.scm (out-ports): Fixed devectorizing bug triggered by
	comments.
	(out-assignment): Output literal numbers for simple assignments.
	(generate-stimulus-file): Restored output (register) declarations.
	(translate-ca-assign): Extracted TRANSLATE-ASSIGNMENT recursion.
	(translate-assign-if): Tail recursive ALTERNATE translates ELSIF.

2001-04-30    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-decls): Finds comments by itself.

	* simsynch.scm (create-board): Added field DEFINING-BLOCK to PIN.

	* run.scm (generate-spew-lists, spew-list): moved from scm2*.scm.

	* scm2vhdl.scm: Top-level generation functions reorganized to be
	PTAG-based.

	* simsynch.scm (signal->comment): Extracted to top-level.
	(create-board): Moved signal and pin comments to table COMMENT.
	(used-by-other-ptags?): Now PTAG based, rather than BLOCK.

2001-04-29  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (out-component, out-entity): Replaced TAG argument
	with DESIGN and BLOCK.
	(generate-module-includes): Unused; removed.
	(generate-main-file): PAIREDS is unused.
	(out-entity, out-component): Fixed bus data directions.
	(translate-tag): Removed unused MODULE-FILES.

2001-04-27    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-tag): Emit initial-expression rather
	than ceval of initial-expression.
	(translate-tag): Macros must be compiled using functional if(?)!
	(generate-main-file): Main files absorbed the "inc" file.

2001-04-26    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-tag): Macros can be ifable.
	(out-assignment): Made assignments smarter about small rhs.

	* logic.scm (vector-bounds): Grok VHDL string constants.

2001-04-25    <ajaffer@scanlogic.com>

	* scm2vrlg.scm, scm2mach.scm, scm2vhdl.scm (translate-design):
	Updated and renamed from translate-design-tag-from-files.

	* run.scm (translate): updated per current practice.
	(*spew-output*): moved from scm2*.scm files.

	* scm2vhdl.scm (out-assignment): Use EXT instead of
	CONV_STD_LOGIC_VECTOR for BOOLEANS-TO-NUMBER forms.
	(out-component, out-entity): removed TRI statements.

	* logic.scm (vector-bounds): Now understands expressions of ASH
	and LOGIOR.

2001-04-24    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (generate-stimulus): Conversion from BIT to
	Std_Logic requires "To_StdLogic" calls.
	(generate-inc-file): Fixed(?) INOUT treatment.

2001-04-23    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-assignment): Eliminated some gratuitous
	"To_StdLogic" calls.

2001-04-20    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-exp): Added POSITIVE? and NEGATIVE?

2001-04-19    <ajaffer@scanlogic.com>

	* simsynch.scm (synch:define-bus): Removed ". connections" bug.
	(define-synchronous-system): Bind hiddens before macros.

	* synch.texi (Translation): Added VHDL.

	* scm2vhdl.scm (*prefix-negation*): Added support for prefix "n_"
	for negation (vs. "_n" suffix).

2001-04-18    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-name): Don't upcase names.
	Changed all use of unsigned to std_logic_vector.

	* logical.vhd: Changed all use of unsigned to std_logic_vector.

2001-04-17    <ajaffer@scanlogic.com>

	* logical.vhd: Package renamed logical.

2001-04-12  Aubrey Jaffer  <agj@alum.mit.edu>

	* logical.vhd: Renamed from simsynch.vhd

2001-04-12    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-exp): Added TO-STD-LOGIC operator.
	Fixed "boolean?" bugs.

	* logical.vhd: Removed mixed boolean/std_logic overloaded logical
	operators; not used.
	(To_StdLogic): Replaced ToBit.

	* readtext.vhd (Read): Split from logical.vhd for Synopsis'
	benefit.

	* scm2vhdl.scm (integerize): Added; abstracts Conv_Integer calls
	for indexes.
	(translate-case-clause): Returns #t if encountered ELSE clause.
	(translate-assignment): Inserts default 'WHEN OTHERS' ERROR.
	Changed calls to 'translate-name' to 'out'.

	* logical.vhd (bit_field): Added.

2001-04-11  Aubrey Jaffer  <agj@alum.mit.edu>

	* Makefile (trnfiles): Split from srcfiles.

	* logic.scm (bounds->width, vector-width): Added.

	* scm2vhdl.scm (out-number): Numbers > 2^31 as bit-strings.
	(remove-gratuitous-masking): Added.

2001-04-11    <ajaffer@scanlogic.com>

	* logical.vhd (fif): Removed impossible (and ambiguous) cases.

	* scm2vhdl.scm (LOG*): Logical homonyms associated wrong.

2001-04-10    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (generate-stimulus): Check outputs against spew.

	* logical.vhd (Read): for std_ulogic_vector added.
	(To_Unsigned): Use 'range for indecis.

	* scm2vhdl.scm (out-decls): Fixed memory bound translation.

2001-04-10  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (generate-stimulus): Read binary spew.

	* run.scm (spew:vhdl): Generate fix-width binary spew.

2001-04-09    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-assignment): Elide gratuitous MODULOs.
	(translate-exp): Output numeric (rather than arithmetic) moduli.
	(generate-module-header): Combinatorials moved here.
	(translate-tag): Resets were always negated!
	(generate-stimulus): Put in (arbitrary) symmetric clock.

	* models.scm (synch:fifo): Now constructs any length fifo; figures
	counter widths for power-of-two sizes.  Put idxbits on fullness.

2001-04-09  Aubrey Jaffer  <agj@alum.mit.edu>

	* models.scm (synch:fifo): Fixed comment generation.

2001-04-06    <ajaffer@scanlogic.com>

	* logical.vhd(to_unsigned): added std_ulogic_vector case.

	* scm2vhdl.scm (out): vprintf merged into.
	(translate-tag): Call to generate-stimulus-file conditioned
	by *dump-list*.
	(generate-stimulus-file): std_logic_textio must be compiled in
	project.
	(generate-stimulus): Read in spew and drive simulation.q

	* logical.vhd ("not", To_Unsigned): Strange limits in FOR.

	* run.scm (spew:verilog, spew:vhdl): Split and moved from
	simsynch.scm.
	(dump:verilog, dump:vhdl): Macro wrappers capture *dump-list*.

2001-04-05    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (spew-list): pulled out of generate-module-header.
	Fixed lots of format problems.

	* simsynch.scm: Null comments now more informative.

	* logic.scm (comment): With single symbol argument, retrieves
	comments and defaults to "no comment for <ARG>".

2001-04-04    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-tag): Some calls to out-assignment had
	wrong polarity.
	(translate-assignment): Array indices need CONV_INTEGER.

2001-04-04  Aubrey Jaffer  <agj@alum.mit.edu>

	* simsynch.scm (dump:spew): dump:port replaces pf:dumpport.

	* logical.vhd: Redefined to FAIL the std_logic_arith mixed
	unsigned/std_ulogic overloaded arithmetic operators.

2001-04-03  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (translate-exp): ModelSim complains about vect[3]
	used as std_logic.

2001-04-03    <ajaffer@scanlogic.com>

	* logical.vhd (lShift): Added.
	Added mixed boolean/std_logic overloaded logical operators.

	* scm2vhdl.scm (translate-exp): Catenating for right-shift had
	problems; use lshift from logical.vhd.

2001-04-02  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (out-assignment): Fixed width arg to Conv_Unsigned.
	(translate-exp): Map tobit over catenate args.

	* logical.vhd: Added mixed unsigned/integer argument cases.

2001-03-30  Aubrey Jaffer  <agj@alum.mit.edu>

	* scm2vhdl.scm (out-entity): BUFFER instead of OUT allows signal
	to feed back.
	(translate-assignment): CONV_INTEGER key of CASE.
	(generate-standard-includes): Include conflicts cause symbols to
	be undefined; reduced to std_logic_1164 and std_logic_arith.

2001-03-29    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-decls):
	* logical.vhd: Use unsigned instead of std_logic_vector.

	* scm2vhdl.scm (out-number): Don't type binary (B).
	(translate-exp): UGH!  VHDL distinguishes between bits and
	booleans.

	* logical.vhd: Try writing multicasting versions of utility
	functions.

2001-03-28    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (generate-main-file): Added.  Module connections
	now separated from stim(ulus) file.
	(named-instantiate): Fixed.

2001-03-27    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (translate-ifdef): VHDL chokes on undefined
	symbols, so conditionally translate.
	(out-entity): Fixed sometimes missing semicolon;
	(generate-module-footer, translate-assignment): Fixed missing
	semicolons.
	(generate-standard-includes): Use logical.vhd module.
	(translate-if): VHDL can't inline conditionals; use BIF and VIF.

2001-03-26    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-entity): Fixed "call by name".
	(translate-tag): Fixed reset-less PROCESS.
	(out-number): Split from translate-exp.
	(out-bus): Split from translate-tag; uses correctly sized ZZZs.
	(set-diff): Needed 'equal?' version.

2001-03-23    <ajaffer@scanlogic.com>

	* scm2vhdl.scm (out-decl): Generates VHDL ARRAY types.

2001-03-22    <ajaffer@scanlogic.com>

	* run.scm (translate): Added VHDL support.

2000-08-05  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:defcomb): Added.

2000-07-02  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* logic.scm (time-stamp:configuration): Default is '??.

2000-06-18  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (generate-verilog-header): Default to current-time
	if time-stamp:time not set.
	(generate-inc-file, translate-tag): optionally-parenthesize test.
	(optionally-parenthesize): swap arguments to be like tranlate-exp.

2000-06-16  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* synch.texi (Infrastructure): Updated "usercat".

	* logic.scm: Removed ancient "SCM bug workaround".

Sat Jun 3 22:36:37 EDT 2000  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1b4 to 1b5.

2000-04-18  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* logical.v (bit_field) was shifting in the wrong direction.
	(copy_bit_field): fixed?

2000-03-25  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* simsynch.scm (synch:shout): Prefix hex numbers with #x.

2000-03-24  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:define-bus): Don't include bounds in -drv names.
	(define-synchronous-system): Check bounds of register values.

	* logic.scm (chkbnd): Added to check bounds of register values.

2000-03-23  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (merge-bounds): union eliminates duplicates in list.

	* scm2vrlg.scm (generate-module-header, *spew-output*): Send
	dump:spew expressions to file <design>-spew.scm.

	* simsynch.scm (dump:spew): Output x for *xxxx*.

2000-03-22  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (optionally-parenthesize): Simulator insists that
	catenated numbers have width.  Don't catenate onto 32-bit regs.
	(generate-module-header): Corrected dump:spew output.

2000-03-20  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (synch:do-msgs): Remove all entries form
	synch:triggers that match synch:count in order to discard
	duplicates.

2000-03-18  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:prin-messages!): Added.  Called from
	define-synchronous-system code so messages won't be lost if
	simulation is not calling synch:print.
	(synch:shout): Defaults to slib:warn or slib:error if not
	SIMULATING?.
	(signal-table:get-next-fun): Checks that signal is registered;
	only called from SYNCH:PRE.

	* scm2vrlg.scm (synch:error, synch:warn): Now report.

2000-03-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Fixed compilation of bit-field for
	non-numeric arguments.

2000-03-09  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (generate-standard-includes): includes
	asyn_ram_256x8_iror.v library module.

	(destructuring-case): Macro used for parsing ram-table
	next-function -- perhaps should be moved.

	(named-instantiate): Outputs Verilog named instantiation syntax.

	(translate-tag): (process-rams): (instantiate-asyn-ram):
	(translate-logaref):
	(ram-ref): Support for asynchronous ram instantiated using Verilog
	library module.

	* models.scm (make-asyn-ram): (make-asyn-ram-array): Modelled by
	MAKE-RAM.

	* simsynch.scm
	(create-board): pin-type of LIBRARY-MODULE type added --
	call-with-classified-pins will ignore.  ram table added to support
	library module for rams.

	(synch:define-signal): MAKE-ASYN-RAM as an initializer adds
	ram-table entry.

2000-03-08  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:prin-count): Now top-level definition.
	(synch:prline1, synch:prin): extracted procedures from defmacro
	synch:print.
	(synch:prin-header): Converted (defmacro) to procedure.
	(synch:print-pre-trigger): extracted from synch:prin.

2000-02-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (dump:spew): Open file only if writing.
	(synch:print): Open msg file only if writing.
	(synch:do-msgs): Moved from synch:print.

2000-02-17  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (synch:open-log): Opens argument filename for
	logging simsynch errors and warnings.  Reads old log file for
	trigger points.
	(synch:print): Prints values of synch:count 25 before and 25 after
	messages beginning with "W" or "E".  Prints output beginning at
	synch:trigger points.

2000-02-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* run.scm (bk): Added call to synch:reset.

	* simsynch.scm (synch:info): Added; prints message without
	context.

2000-02-16  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:print): Prints (up to) 50 lines before and
	after warnings and errors.
	(synch:shout): Added; abstracts synch:warn and synch:error.

2000-02-10  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-tag): Output 'ifdef SIMULATE ... instead
	of `ifdef exemplar ...

2000-02-09  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (infix-translate-list): Separated from
	infix-translate-exp.
	(translate-constant-definition): Removed SEP argument from all
	functions.  This function probably breaks with SILOS.
	(infix-translate-exp): Simplified.
	(infix-translate-arith): Added to catenate 00 to top bits.

2000-02-08  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (call-with-classified-pins): Removed "output-enable
	not symbol" message.

2000-02-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:warn): Print numbers in hex.

2000-01-30  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp): Keep ZERO? on one line.
	(translate-tag): No longer generate "non-reset register" message.

2000-01-26  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): Put out definitions in declared
	order.

	* simsynch.scm (signal-table:for-each-row): Added declared-order
	mapper.

2000-01-24  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Avoid negative numbers; warn.

2000-01-20    <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (out-uint): Print numbers in hex.

2000-01-19    <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-constant-definition): Removed gratuitous
	parentheses.
	(out-uint): renamed.  Prints small numbers in decimal.

2000-01-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Pad addition and multiplication
	operands with leading zeros to avoid truncation.
	(out-int): No need to pad number constants to length.

2000-01-16  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp): Change left shifts to
	concatenation.

2000-01-14  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Exemplar cannot optimize through
	the `identity' function -- so make use conditional on Verilog flag
	BROKEN_TRUNCATION.

2000-01-07  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-assign-if): Exemplar chokes if reset
	condition polarity does not match "always" statement.
	(translate-ifdef): There is no ifndef in verilog.

2000-01-06  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-ifdef): Added.
	(translate-assign-if, translate-if): Added.

1999-12-29  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp): Workaround for Synplicity bug.

	* logical.v (identity): Added.

Sun Dec 5 21:16:16 EST 1999  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1b3 to 1b4.

1999-12-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-assignment): Restored self-sets, except
	for arrays.

1999-11-26  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:print): Fixed initial off-by-one.

1999-11-24  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): Translate reset expressions.

1999-10-30  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): 0 -> 2'b00.
	(generate-standard-includes):
	(generate-module-includes): include from current directory.

1999-10-28  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (out-int): Minimum number length is 2 bits.

	* simsynch.scm: Display version in opening message.

1999-10-23  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): fluid-let *block* needs to apply
	to all translations.

1999-10-21  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (generate-module-header): Assure that clock is an
	input to module.

1999-10-13  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (define-synchronous-system): Fixed resets.

1999-10-05  Radey Shouman  <Radey_Shouman@splashtech.com>

	* logic.scm (array-bounds): Now takes block as an argument,
	instead of using *block*.

1999-09-30  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-constant-definition): Negative constants
	=> 1'bx.

	* logic.scm (vector-bounds): Fixed for imported signals; for
	example (xp tl-y[6:0]).

1999-09-21  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* Makefile (synch.info): Tolerate infobar no-changes error.

Sun Sep 12 23:00:31 EDT 1999  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1b2 to 1b3.

1999-09-08  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-tag): Conditionalize reset block with
	`ifdef exemplar if NO-RTL-SIMULATION flag is present.

	* simsynch.scm(synch:declare): Uses current *block*, instead of
	confounding blocks and ptags.

1999-09-07  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (call-with-classified-pins): Added output-enable to
	outputs when simple symbol.

1999-09-03  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (generate-inc-file): Conditionalized on feature
	'lift-bus.

	* simsynch.scm (call-with-classified-pins): Conditionalized on
	feature 'lift-bus.

Fri Sep 3 18:33:22 EDT 1999  Aubrey Jaffer  <jaffer@scm.colorage.net>

	* Makefile (VERSION): Bumped from 1b1 to 1b2.

1999-09-03  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (generate-inc-file): Raise bidirectional signals to
	include file for top-level.

	* simsynch.scm (call-with-classified-pins): simplified
	input/output section.
	(call-with-classified-pins): Output inputs and outpus for
	bidirectional signals.

	* scm2vrlg.scm (translate-exp): Treat EQV? like =.

1999-09-02  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* models.scm (make-ram-array make-ram): Fill RAM with prototype.

1999-09-01  Radey Shouman  <Radey_Shouman@splashtech.com>

	* logic.scm (read:sharp): Now skips leading semi colons in #;
	lines.

1999-09-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* synch.texi (Infrastructure): Added documentation of #; and
	comment.

1999-08-31  Radey Shouman  <Radey_Shouman@splashtech.com>

	* logic.scm: Added #; read syntax for (comment ...) forms.

1999-08-31  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* models.scm (synch:fifo): Added COMMENTs to generated code.

1999-08-30  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (outcomment): fixed comment indentation.

1999-08-30  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (generate-module-header): Now looks up comments in
	signal-table.

	* scm2vrlg.scm (out-decl): Will emit comments in declarations.

1999-08-29  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (out-decl): Added comments argument.

	* logic.scm (comment): Added.

	* simsynch.scm (create-board): Added optional-documentation
	strings for ptag, block, constants, and signals.

	* logic.scm (comment): Added.

1999-08-28  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): Added support for *xxxx*.

	* simsynch.scm (*xxxx*): Leave initial-state unspecified.

1999-08-24  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (synch:define-signal): Now checks whether
	INITIAL-STATE argument is a list with car SYNCHRONOUS, if so,
	synchronous reset Verilog will be generated for the defined
	signal.

1999-08-23  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-tag): Now checks block-table
	SYNCHRONOUS-RESET? flag.
	*simsynch (create-board): (synch:register-block):
	Added CLOCK-FREQUENCY, SYNCHRONOUS-RESET? fields to BLOCK table.

1999-08-17  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2mach.scm (translate1): Checks for unrecognized flags.
	* scm2vrlg.scm (translate1): Now checks for recognized flags.
	* simsynch.scm (synch:check-flags): Added to generate warnings
	about unrecognized flags.

	* scm2vrlg.scm (translate-tag): Recognizes SYNCHRONOUS-RESET flag,
	to remove reset signal from Verilog sensitivity list.

	* simsynch.scm (create-board): Added FLAGS table for translation
	target dependent (per signal) flags.
	(synch:signal-flags): Retrieves flags list.
	(synch:add-signal-flag): Adds flag to table.
	(synch:declare): Macro interface to SYNCH:ADD-SIGNAL-FLAG.

1999-07-30  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): moved check from "simsynch.scm".

	* simsynch.scm (synch:define-signal): moved check to
	"scm2vrlg.scm".

Fri Jul 30 12:11:05 EDT 1999  Aubrey Jaffer  <jaffer@scm.colorage.net>

	* Makefile (VERSION): Bumped from 1b0 to 1b1.

1999-07-30  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:define-signal): check that vectorized
	signals have numeric initial values and vice-versa.

1999-07-29  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (synch:print): Removed call to dma:dword-read-count.

1999-07-27  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Don't vectorize LOGBIT? unless
	first argument is number.
	(translate-case): was incorrect for logical expressions lacking
	'(else #f).

1999-07-23  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-assignment): Take POLarity into account
	when eliding assignments.

1999-07-22  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): prettied BOOLEANS-TO-NUMBER
	expansion indentation.

1999-07-22  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-exp): Added support for
	BOOLEANS-TO-NUMBER, translates to Verilog concatenation eg {foo,
	bar, baz} .

1999-07-14  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Fixed translation of LOGTEST.

1999-07-13  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): bool? argument was not being
	correctly set -- fixed.
	(translate-case): added.  Only boolean case statements can be
	translated to verilog || and &&.

1999-07-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* synch.texi (Translation): Expanded.

	* logical.v: Gave widths to all identifiers.

1999-06-22  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* models.scm (synch:fifo): Changed ".." to ":".

1999-06-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Translate modulo -> logand (not %).

	* logical.v: Added random_Percent.

1999-06-13  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-case-clause): Suppress self-set defaults.
	(translate-assignment): Suppress self-sets.
	(out-decl): Fixed array declaration.

1999-06-11  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): Added LOGTEST.

1999-06-09  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* models.scm (synch:fifo): Added checks for reading from empty and
	writing to full.

1999-06-09  Radey Shouman  <Radey_Shouman@splashtech.com>

	* edf2vrlg.scm: Added, edif netlist to verilog translator.

1999-05-25  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp): Fixed output of negative constants.

1999-05-25  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-power-connections): Attempts to print
	power and ground connections in Verilog format.

	(translate-netlist): Prints declarations, instantiations of u-numbered
	parts, and power connections, as Verilog.

1999-05-25  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (number-lines?):. (vprintf): added.
	(out): (generate-verilog-header): Fixed line numbers.

1999-05-25  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:register-u-ptag): Added, now called by
	DB:READ-U-PTAG .

	(db:read-net): Now creates ptags and u-ptags for unrecognized
	u-numbers read from netlist.

	* simsynch.scm (db:read-net): Now reads non-integer pin names from
	netlist.

1999-05-24  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp): Output numbers in base 2.

1999-05-24  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-netlist): Added, outputs Verilog version
	of netlist.

	* scm2vrlg.scm (translate-tag): Fixed "wire" declarations for
	macro signals.

	* scm2vrlg.scm (translate-tag): Split output into one file per
	module.
	(call-with-verilog-output): Fluid lets verilog output port.

1999-05-23  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (byte0 byte1 byte2 byte3): Added functions for wide
	numbers in synch:print.

1999-05-17  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-<>): added inequalities.  But doesn't <=
	mean assignment?

1999-05-13  Radey Shouman  <Radey_Shouman@splashtech.com>

	* pins.scm (pins->dcm): Now writes section of .acf file as well as
	.dcm file.

	* drawpins.scm (flush-ws): Fixed to really flush whitespace.

	(read-coord-strings-3): (read-coord-strings-4): Now named for
	number of fields they read, were *both* named read-coord-strings.

	* scm2vrlg.scm (write-acf-file): Added, writes a section of the
	.acf file specifying pin assignments.

	* run.scm (simsynch-vicinity): Now defined as top-level procedure.

1999-04-29  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* logic.scm (ptag-stripped):
	(ptag-prefix): don't mistake [31:0] for a PTAG.

	* simsynch.scm (create-board): Removed PLD table.  Just use string
	supplied to synch:register-ptag.
	(synch:definput):
	(synch:defreginput):
	(synch:define): only strip signal-name if it has the ptag.

1999-04-01  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* pins.scm (type->dir): Added GCLK type.

1999-03-23  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-name): Eliminated first, full name
	argument.

	* simsynch.scm (create-board): Replaced BASENAME table with
	PIN-BASENAME table, mapping basenames to entries in the PIN table.

	(create-board): Added BASENAME table, for scm2vrlg
	conversion: given name stripped of bounds, find signals with
	bounds & unique defining ptag.

1999-03-22  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* simsynch.scm (define-synchronous-system): Reset state
	initialized earlier.

1999-03-22  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (translate-tag): Changed condition for "always @
	(posedge <clock>" from name==initial-state to name==reset.

	* simsynch.scm
	* run.scm (print-netlist-connections): Now takes design, netlist
	file, and u-number->ptag mapping file as arguments.  No longer
	prints out nets not driven by any signals in the database.  Moved
	to run.scm.

1999-03-19  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:netlist-connects net-name bounds): Added,
		returns list of ((ptag signal-name) ...) connected to a
		net-name read from a netlist file.
	(print-netlist-connections):  Added.
	Added NAME field to the pindex table, a symbol eq? to the
	original signal-name provided to synch:define-pin.

1999-03-11  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-name): Names of pin signals now
	UPPERCASED.  Others have ptag prefixed.  Inverted signals have _n
	suffix.

1999-02-23  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (create-board): Split NETLIST-AGGREGATE table into
	NETLIST-AGGREGATE and NETLIST-NON-AGGREGATE, since there are
	aggregate nets with the same names as non-aggregate nets.

	(db:print-power-connections): Prints first aggregate nets, then
	non-aggregate.

	* simsynch.scm (create-board): Added table NETLIST-AGGREGATE which
	contains the names of each net name with trailing index deleted.

	(db:read-net): Now parses trailing digits as an index, the NETLIST
	table now uses name and index as primary keys.  -1 as index means
	no trailing digits.

	(db:print-power-connections):  Prints aggregate nets together.

1999-02-12  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:print-power-connections): Added, walks netlist
	printing nets connected to power or ground nets by resistors.

	(db:read-net) Added field R-PINS to netlist table
	for resistors in a net.  Added table RESISTOR-NETS to map
	resistors to nets they connect.

1999-02-11  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:read-net): Added sheet number to netlist table.

1999-02-10  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:read-u-ptag): Now registers unique ptags as
	necessary.

1999-02-05  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (define-tables): Renamed SIGNAL-NET table to
	NETLIST, added NETLIST-INVERSE table.

	(db:read-net): Now also inserts rows in netlist-inverse table.

	* simsynch.scm (bus-expression): Added, returns expression
	combining several vectorized signals.

	(process-aggregate-pins): Stub added.

	* scm2vrlg.scm (get-bounds): (merge-bounds):
	(call-with-classified-pins): Moved to simsynch.scm, are not
	dependant on translation target.

	* simsynch.scm (create-board): Added tables: U-PTAG, for
	tranlating u-numbers from netlist to ptags, SIGNAL-NET for
	mapping signal names to pin numbers.

	(db:read-u-ptag): Added, reads Scheme list associating
	u-numbers to ptags, eg cz-umap.scm.

	(db:read-net): Added, reads netlist.

1999-02-04  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (db:read-pins): Now reads BGA pin files.

	* drawpins.scm (flush-ws): Added to allow Scheme style comments
	with leading whitespace in .pin files.

1999-02-02  Radey Shouman  <radey@bobo.colorage.net>

	* drawpins.scm (draw-pins): Added thicker lines, lines slightly
	offset, row and column labels.

1999-01-27  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-exp):
	(translate-and):
	(infix-translate-exp):
	(optionally-parenthesize): Added BOOL? argument so test
	expressions are translated into && and ||.

1999-01-27  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (instantiate): Removed redundant (last) argument.

1999-01-20  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (instantiate): added argument HEADER? so
	instantiations are explicit form.

1999-01-17  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* ANNOUNCE: added.

Sun Jan 17 11:24:43 EST 1999  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a3 to 1b0.

1999-01-13  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-and): added.  Turn (and a ... z) into
	(if (&& a ...) z 0).

1999-01-12  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* Makefile (version.txi): support added.

	* synch.texi (SIMSYNCH_VERSION): abstracted to version.txi.

1999-01-08  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): translate booleans as 0 and 1.

	* simsynch.scm (create-board): removed constants `f' and `t'.

	* scm2vrlg.scm (negate-result?): removed; instead pass polarity
	argument to translate-assignment.

1998-12-16  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (instantiate): Added comma output where necessary.

1998-12-15  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* simsynch.scm (dump:spew): dump stuff simplified.

1998-12-15  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (synch:dump-vector): (synch:dump-scalar): Added
	functions for writing Verilog compatible dump files.

1998-12-15  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (instantiate): Now takes separate signal group
	argument; print nice comments.
	(generate-module-header): Now pretty-prints scheme code for
	dumping module state.
	(merge-bounds): Now keeps track of pin names associated with
	merged signal.

1998-12-14  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (call-with-classified-pins): only imports/exports
	pins and signals used by other blocks.

	* simsynch.scm (used-in-table mark-uses used-by-other-blocks?):
	Created to keep track of which signals are used in which blocks.

1998-12-11  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): include "logical.v" from each
	non-trivial module.
	(call-with-classified-pins): classify internal signals as
	input and output if within block.
	(translate-tag): create declarations of macros (wire) before
	assign statements.

1998-12-10  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-tag): Now generates separate modules for
	each block within a ptag.
	(translate-text-macros): removed; macros now generate assign =
	statements.
	(out-bufs out-buf): removed (already commented out).
	(generate-module-header): don't generate constants for trivial modules.
	(instantiate): used for both `module' statements and instantiations.

1998-11-10  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): shift direction was backwards.

1998-11-09  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): self-setting signals reset
	removed.

	* scm2vrlg.scm (translate-tag): outputs conditional assignments
	(with ..'bz) rather than bufif1 statements.

	* scm2vrlg.scm (translate-assignment): Restored self sets.  =
	changed to <= for assignments.

1998-10-07  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): fixed self-initing/input register
	reset generation.

Sat Aug 8 22:57:38 EDT 1998  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a2 to 1a3.

1998-07-21  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (ptag-stripped): return #f for 'tag: argument.
	(ptag-stripped): return number if stripped pin-name is.

	* simsynch.scm: pin-number and pin-num renamed to pin-name and
	pin-nam.  PTAG can now be specified on pin-nam.  Pin-nams can be
	vectorized (dq[32..00]).

	* logic.scm (ptag-stripped):
	(ptag-prefix): now pass numbers.

	* simsynch.scm (synch:define): now takes optional NEXT-FUNCTION
	argument.

1998-07-20  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (translate-assignment): elides self-sets.

	* models.scm (synch:fifo): no longer generates external names.
	All are passed as arguments.
	* logic.scm (array-bounds): puts out nicer looking index
	calculations.

1998-07-17  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (symbol-append): beefed up to tolerate strings and numbers.

	* scm2vrlg.scm: Added array support.

	* models.scm (synch:fifo): added macro to instatiate FIFO memory.

1998-07-17  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm (signal-table:get-init-fun): added.

	* logic.scm (array-bounds): added.

	* scm2vrlg.scm (translate-tag): moved call to
	translate-text-macros before generate-module-header.
	(call-with-classified-pins): now knows about arrays.

1998-07-16  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (translate-exp): ash of negative numbers now uses
	`>>'.

	* synch.texi (Models): Added chapter.

	* simsynch.scm (pld): added ORCA3 package types.
	(synch:define-bus): Doesn't count #t enabled drivers -- these are used
	to model pullup/down.

	* scm2vrlg.scm (translate-exp): added `+' and `-'.

	* models.scm (make-ram-array): added.

1998-07-15  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm (make-ram): added.

1998-06-11  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (booleans-to-number): commented out warning.

	* simsynch.scm: Added CHECK-TURNAROUND feature.  This enables
	checks generated by synch:define-bus.

1998-06-08  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (out-decl merge-bounds call-with-classified-pins):
	split out from generate-verilog-header.
	(generate-stimulus): now instantiates module with symbols.  primitive
	initial assignments added.

1998-05-29  Aubrey Jaffer  <jaffer@colorage.com>

	* Makefile (expander.scm): removed.

	* simsynch.scm (synch:set!): multiple synch:set!s now COMPOSE-SETS
	of new-states.

	* models.scm (make-fifo): added optional width-prototype field.

1998-05-26  Radey Shouman  <radey@colorage.com>

	* run.scm: Added error message for unknown translate target.

	* scm2vrlg.scm: Added support for BITWISE-IF.

1998-05-26  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm, scm2mach.scm: Added BIT-FIELD as alias for BIT-EXTRACT.

	* Makefile: split html target into html and cvshtml.

	* synch.texi: Included and reordered documentation for new
	(SLIB/SCM) logical operations.

	* simsynch.scm (define-synchronous-system): fixed
	(<block-name> <signal>) to work during reset.

1998-05-22  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm, scm2vrlg.scm, scm2mach.scm:
	(<block-name> <signal>) now retrieves value.

	* scm2vrlg.scm, simsynch.scm, scm2mach.scm:
	SYNCH:PRE no longer requires (nor works with) #.

	* Makefile: models was missing from distribution.

1998-05-21  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm: Includes "models.scm".

1998-05-20  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm: changed make-uniform-array prototype to #xffffffff.

Thu May 21 22:03:34 EDT 1998  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a1 to 1a2.

1998-05-20  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm: changed make-uniform-array prototype to #xffffffff.

1998-05-19  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm: fixed compose-sets

	* models.scm: fifo:clear added.

	* scm2vrlg.scm: Made NOT ifable.

	* scm2vrlg.scm: Added case-eval; no longer substitute values for
	constants in CASE statements.

	* scm2mach.scm: case-eval: no longer need to substitute values for
	constants in CASE statements.

	* scm2mach.scm: MACHXL string constant number must not have
	enclosing parentheses.

1998-05-14  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm: In symbol names : => _

	* simsynch.scm, scm2vrlg.scm, scm2mach.scm: Translators now handle
	defconst (and , in casev).

1998-05-13  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm: CEVAL added; evals constant

	* scm2vrlg.scm: translate-= replaced using verilog ==

	* scm2mach.scm: Added CASEV support.

1998-05-12  Aubrey Jaffer  <jaffer@colorage.com>

	* synch.texi, scm2vrlg.scm, logic.scm: defconst definition made
	conditional; (scm now defines).  memocase -> casev

	* logic.scm, ChangeLog: logic.scm (memocase): Now case compatible
	with unquote or unquote-splicing in datum-list.

	* .cvsignore: added core

	* Makefile: A dummy directory (like core/) needs to be in the
	source dir in order to get a pane with the sequential log button
	in it. (cvs2html)

1998-05-12  radey  <radey@scm.colorage.net>

	* synch.texi: documentation for memocase

1998-05-12  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (memocase): Now case compatible with unquote or
	unquote-splicing in datum-list.

Thu Oct 30 10:38:54 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* logic.scm (count): count booleans added.

Wed Jun 11 16:01:27 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* simsynch.scm (define-synchronous-system): now keeps track of
	SYNCH:STATE explicitly.

Fri May 16 10:08:30 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* scm2mach.scm (compile-tops): headers now use coded time in time
	field.  CZ support added; slightly different format.

Thu Apr  3 17:17:11 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* run.scm (translate): generalized for use with DESIGN.
