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dsynchandler.h

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00001 
00002 /*
00003 ** Copyright (C) 2004 Russell Leighton
00004 **
00005 ** This program is free software; you can redistribute it and/or modify
00006 ** it under the terms of the GNU General Public License as published by
00007 ** the Free Software Foundation; either version 2 of the License, or
00008 ** (at your option) any later version.
00009 **
00010 ** This program is distributed in the hope that it will be useful,
00011 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
00012 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013 ** GNU General Public License for more details.
00014 **
00015 ** You should have received a copy of the GNU General Public License
00016 ** along with this program; if not, write to the Free Software
00017 ** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00018 */
00019 
00020 
00021 
00022 
00023 #ifndef __AWHANDLER_DSYNC__
00024 #define __AWHANDLER_DSYNC__
00025 
00026 #include "monitor.h"
00027 
00028 #include "wire.h"
00029 
00030 #include "eventrxhandler.h"
00031 #include "eventtxhandler.h"
00032 
00080 /* default ip and port  */
00081 #define AW_DSYNC_DEFAULT_MCAST_GROUP "239.255.255.228"
00082 #define AW_DSYC_DEFAULT_MCAST_PORT 1800
00083 
00084 /* the smallest error considered acceptable to declare converged */
00085 #define AW_DSYNC_CONVERGENCE_ERROR (AW_TIMESTAMP_PER_SEC / 10)
00086 
00090 typedef struct {
00091 
00092   aw_event_sig_t
00093    interrupt;                  /* handler went off */
00094 
00095 } aw_dsynchandler_events_t;
00096 
00097 
00101 typedef struct {
00102 
00103   /* non-zero if all OTHER handlers have phases measured
00104      in the first left or right bins */
00105   int32_t
00106    converged;
00107 
00108   /* the index of the bin that , below which, is the covergence interval */
00109   int32_t
00110    convergence_bin;
00111 
00112   /* how long to accumulate before adapting */
00113   int32_t
00114    integration_step,
00115    integration_interval;
00116 
00117   /* Phase Distribution
00118      
00119      It is split into 2 histograms, one (pos) plus 1/2 period and the other (neg) minus 1/2 period.
00120      
00121      The bin size is not uniform, rather it is log base 2 per
00122      the following definition:
00123       - the last bin holds the count of those values >= upper half of the interval
00124       - the next bin holds the count of those values >= upper half of the remaining interval
00125       - etc., to 0
00126       The point of this is to have hyper resolution near the inside side where we
00127       are more concerned with accuracy.
00128       NOTE: we re-normalize if any bin overflows 
00129   */
00130   u_int16_t
00131    hist_pos[8],
00132    hist_neg[8];
00133 
00134   /* count of total in both hists */
00135   u_int32_t
00136    total_samples;
00137 
00138 } aw_dsynchandler_pdist_t;
00139 
00143 typedef struct {
00144 
00145   aw_handler_t 
00146    handler_header;
00147 
00148   aw_dsynchandler_events_t
00149    events;
00150 
00151   /* if non-zero, only emit events if converged */
00152   int32_t 
00153    onsync;
00154 
00155   /* phase distribution */
00156   aw_dsynchandler_pdist_t
00157    pdist;
00158 
00159   /* multicast inteface, defaults to NULL -> INADDR_ANY */
00160   byte_t *mcinterface;
00161 
00162   /* multicast group */
00163   aw_ip_addr_t mcaddress;
00164 
00165   /* non-zero if allow local multicast traffic, defaults to 0 */
00166   u_int32_t mcloopback;
00167 
00168   /* port */
00169   int32_t mcport;
00170 
00171   /* send events to others */
00172   aw_eventtxhandler_t
00173    *tx;
00174 
00175   /* received events from others */
00176   aw_eventrxhandler_t
00177    *rx;
00178   
00179   /* event sending dsync events */
00180   aw_event_sig_t 
00181    tx_event;
00182 
00183   /* event for received dsync events */
00184   aw_eventrxhandler_events_t 
00185    rx_event;
00186 
00187   /* the time that send_dsync_event() was called */
00188   aw_timestamp_t
00189    last_dsync_tstamp;
00190 
00191   /* id used in ire callback to delay events */
00192   int32_t
00193    delay_event_id;
00194 
00195 } aw_dsynchandler_t ;
00196 
00200 typedef struct {
00201 
00202   /* the tag for this group */
00203   const byte_t 
00204    *tag;
00205 
00206   /* multicast inteface, defaults to NULL -> INADDR_ANY */
00207   const byte_t 
00208    *mcinterface;
00209 
00210   /* multicast group */
00211   aw_ip_addr_t 
00212    mcaddress;
00213 
00214   /* non-zero if allow local multicast traffic, defaults to 0 */
00215   u_int32_t 
00216    mcloopback;
00217 
00218   /* port */
00219   int32_t 
00220    mcport;
00221 
00222   /* if non-zero, only emit events if converged */
00223   int32_t 
00224    onsync;
00225 
00226 } aw_dsynchandler_options_t;
00227 
00237 aw_dsynchandler_t *aw_create_dsynchandler(const aw_dsynchandler_events_t *events,
00238                                           aw_dsynchandler_options_t *options,
00239                                           const aw_alarm_sched_t *sched,
00240                                           aw_logger_t *logger,
00241                                           aw_monitor_t *mon
00242                                           );
00243 
00248 void aw_free_dsynchandler(aw_dsynchandler_t *h);
00249 
00250 
00254 aw_handler_t *aw_wire_dsynchandler(aw_wire_mkhandler_args_t *args);
00255 
00256 #endif
00257 
Aware 0.11.1 Copyright (C) 1998-2005 Russell Leighton (russ@elegant-software.com)