commit b2e2daf406a5a05103fea359a74ed491f28fc8fa
Author: Richard Biener <rguenther@suse.de>
Date:   Mon May 8 14:30:38 2023

    Bump BASE-VER
    
            * BASE-VER: Bump to 12.3.1.

diff --git a/gcc/BASE-VER b/gcc/BASE-VER
index 4d23cb8e0bd..9c028e25d40 100644
--- a/gcc/BASE-VER
+++ b/gcc/BASE-VER
@@ -1 +1 @@
-12.3.0
+12.3.1

commit 72a7710d886fd5b5a2697af4010e6dbbe874fdaf
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 9 02:20:09 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e50dc5212d2..d3869af5806 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230508
+20230509

commit 8b43834d069183e14c15909e144d870c39b74028
Author: Jason Merrill <jason@redhat.com>
Date:   Tue Jun 7 21:52:30 2022

    c++: non-templated friends [PR105852]
    
    The previous patch for 105852 avoids copying DECL_TEMPLATE_INFO from a
    non-templated friend, but it really shouldn't have it in the first place.
    
            PR c++/106740
            PR c++/105852
    
    gcc/cp/ChangeLog:
    
            * decl.cc (duplicate_decls): Change non-templated friend
            check to an assert.
            * pt.cc (tsubst_function_decl): Don't set DECL_TEMPLATE_INFO
            on non-templated friends.
            (tsubst_friend_function): Adjust.
    
    gcc/testsuite/ChangeLog:
    
            * g++.dg/template/friend78.C: New test.

diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index ab9a009fb7e..42f43c122b9 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -2666,10 +2666,11 @@ duplicate_decls (tree newdecl, tree olddecl, bool hiding, bool was_hidden)
 		  = TINFO_USED_TEMPLATE_ID (new_template_info);
 	    }
 
-	  if (non_templated_friend_p (olddecl))
-	    /* Don't copy tinfo from a non-templated friend (PR105761).  */;
-	  else
-	    DECL_TEMPLATE_INFO (newdecl) = DECL_TEMPLATE_INFO (olddecl);
+	  /* We don't want to copy template info from a non-templated friend
+	     (PR105761), but these shouldn't have DECL_TEMPLATE_INFO now.  */
+	  gcc_checking_assert (!DECL_TEMPLATE_INFO (olddecl)
+			       || !non_templated_friend_p (olddecl));
+	  DECL_TEMPLATE_INFO (newdecl) = DECL_TEMPLATE_INFO (olddecl);
 	}
 
       if (DECL_DECLARES_FUNCTION_P (newdecl))
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index b5fabe4341e..12d91974d32 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -11339,9 +11339,10 @@ tsubst_friend_function (tree decl, tree args)
       tree new_friend_template_info = DECL_TEMPLATE_INFO (new_friend);
       tree new_friend_result_template_info = NULL_TREE;
       bool new_friend_is_defn =
-	(DECL_INITIAL (DECL_TEMPLATE_RESULT
-		       (template_for_substitution (new_friend)))
-	 != NULL_TREE);
+	(new_friend_template_info
+	 && (DECL_INITIAL (DECL_TEMPLATE_RESULT
+			   (template_for_substitution (new_friend)))
+	     != NULL_TREE));
       tree not_tmpl = new_friend;
 
       if (TREE_CODE (new_friend) == TEMPLATE_DECL)
@@ -14175,6 +14176,10 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain,
 	  && !LAMBDA_FUNCTION_P (t))
 	return t;
 
+      /* A non-templated friend doesn't get DECL_TEMPLATE_INFO.  */
+      if (non_templated_friend_p (t))
+	goto friend_case;
+
       /* Calculate the most general template of which R is a
 	 specialization.  */
       gen_tmpl = most_general_template (DECL_TI_TEMPLATE (t));
@@ -14220,6 +14225,7 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain,
 	 tsubst_friend_function, and we want only to create a
 	 new decl (R) with appropriate types so that we can call
 	 determine_specialization.  */
+    friend_case:
       gen_tmpl = NULL_TREE;
       argvec = NULL_TREE;
     }
@@ -14415,7 +14421,7 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain,
       /* If this is an instantiation of a member template, clone it.
 	 If it isn't, that'll be handled by
 	 clone_constructors_and_destructors.  */
-      if (PRIMARY_TEMPLATE_P (gen_tmpl))
+      if (gen_tmpl && PRIMARY_TEMPLATE_P (gen_tmpl))
 	clone_cdtor (r, /*update_methods=*/false);
     }
   else if ((complain & tf_error) != 0
diff --git a/gcc/testsuite/g++.dg/template/friend78.C b/gcc/testsuite/g++.dg/template/friend78.C
new file mode 100644
index 00000000000..6100528468e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/friend78.C
@@ -0,0 +1,18 @@
+// PR c++/106740
+// { dg-additional-options -Wno-non-template-friend }
+
+template <typename> struct EnumClass { friend int toString(EnumClass); };
+struct AmhsConvInfoCoFw {
+  enum AftnTypeXMsgTypeEnum {};
+  typedef EnumClass<AftnTypeXMsgTypeEnum> AftnTypeXMsgType;
+  const int getAftnTypeXMsgTypeAsStr() const;
+  struct MtcuAxgwInfo {
+    AftnTypeXMsgType mAftnTypeXMsgType;
+  };
+};
+const int AmhsConvInfoCoFw::getAftnTypeXMsgTypeAsStr() const {
+  MtcuAxgwInfo __trans_tmp_1;
+  toString(__trans_tmp_1.mAftnTypeXMsgType);
+  return 0;
+}
+int toString(AmhsConvInfoCoFw::AftnTypeXMsgType);

commit ce5c5fe9953bc0acdd563b78db8689dd4d9b7b07
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Apr 26 07:21:05 2023

    rs6000: Fix predicate for const vector in sldoi_to_mov [PR109069]
    
    As PR109069 shows, commit r12-6537-g080a06fcb076b3 which
    introduces define_insn_and_split sldoi_to_mov adopts
    easy_vector_constant for const vector of interest, but it's
    wrong since predicate easy_vector_constant doesn't guarantee
    each byte in the const vector is the same.  One counter
    example is the const vector in pr109069-1.c.  This patch is
    to introduce new predicate const_vector_each_byte_same to
    ensure all bytes in the given const vector are the same by
    considering both int and float, meanwhile for the constants
    which don't meet easy_vector_constant we need to gen a move
    instead of just a set, and uses VECTOR_MEM_ALTIVEC_OR_VSX_P
    rather than VECTOR_UNIT_ALTIVEC_OR_VSX_P for V2DImode support
    under VSX since vector long long type of vec_sld is guarded
    under stanza vsx.
    
            PR target/109069
    
    gcc/ChangeLog:
    
            * config/rs6000/altivec.md (sldoi_to_mov<mode>): Replace predicate
            easy_vector_constant with const_vector_each_byte_same, add
            handlings in preparation for !easy_vector_constant, and update
            VECTOR_UNIT_ALTIVEC_OR_VSX_P with VECTOR_MEM_ALTIVEC_OR_VSX_P.
            * config/rs6000/predicates.md (const_vector_each_byte_same): New
            predicate.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/powerpc/pr109069-1.c: New test.
            * gcc.target/powerpc/pr109069-2-run.c: New test.
            * gcc.target/powerpc/pr109069-2.c: New test.
            * gcc.target/powerpc/pr109069-2.h: New test.
    
    (cherry picked from commit fd75f6ae5625f087980ff4a7e76cc6284cfe5a3e)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 8db9d68fbda..3849db5ca3c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -385,14 +385,22 @@
 
 (define_insn_and_split "sldoi_to_mov<mode>"
   [(set (match_operand:VM 0 "altivec_register_operand")
-	(unspec:VM [(match_operand:VM 1 "easy_vector_constant")
+	(unspec:VM [(match_operand:VM 1 "const_vector_each_byte_same")
 	            (match_dup 1)
 		    (match_operand:QI 2 "u5bit_cint_operand")]
 		    UNSPEC_VSLDOI))]
-  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
+  "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
   "#"
   "&& 1"
-  [(set (match_dup 0) (match_dup 1))])
+  [(set (match_dup 0) (match_dup 1))]
+  "{
+     if (!easy_vector_constant (operands[1], <MODE>mode))
+       {
+	 rtx dest = gen_reg_rtx (<MODE>mode);
+	 emit_move_insn (dest, operands[1]);
+	 operands[1] = dest;
+       }
+  }")
 
 (define_insn "get_vrsave_internal"
   [(set (match_operand:SI 0 "register_operand" "=r")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b1fcc69bb60..274bdbe468f 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -798,6 +798,43 @@
 	    (and (match_test "easy_altivec_constant (op, mode)")
 		 (match_test "vspltis_shifted (op) != 0")))))
 
+;; Return true if this is a vector constant and each byte in
+;; it is the same.
+(define_predicate "const_vector_each_byte_same"
+  (match_code "const_vector")
+{
+  rtx elt;
+  if (!const_vec_duplicate_p (op, &elt))
+    return false;
+
+  machine_mode emode = GET_MODE_INNER (mode);
+  unsigned HOST_WIDE_INT eval;
+  if (CONST_INT_P (elt))
+    eval = INTVAL (elt);
+  else if (CONST_DOUBLE_AS_FLOAT_P (elt))
+    {
+      gcc_assert (emode == SFmode || emode == DFmode);
+      long l[2];
+      real_to_target (l, CONST_DOUBLE_REAL_VALUE (elt), emode);
+      /* real_to_target puts 32-bit pieces in each long.  */
+      eval = zext_hwi (l[0], 32);
+      eval |= zext_hwi (l[1], 32) << 32;
+    }
+  else
+    return false;
+
+  unsigned int esize = GET_MODE_SIZE (emode);
+  unsigned char byte0 = eval & 0xff;
+  for (unsigned int i = 1; i < esize; i++)
+    {
+      eval >>= BITS_PER_UNIT;
+      if (byte0 != (eval & 0xff))
+	return false;
+    }
+
+  return true;
+})
+
 ;; Return 1 if operand is a vector int register or is either a vector constant
 ;; of all 0 bits of a vector constant of all 1 bits.
 (define_predicate "vector_int_reg_or_same_bit"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-1.c b/gcc/testsuite/gcc.target/powerpc/pr109069-1.c
new file mode 100644
index 00000000000..eb4d73a1e66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109069-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vmx_hw } */
+/* { dg-options "-O2 -maltivec" } */
+
+/* Verify it run successfully.  */
+
+#include <altivec.h>
+
+__attribute__ ((noipa))
+vector signed int
+test ()
+{
+  vector signed int v = {-16, -16, -16, -16};
+  vector signed int res = vec_sld (v, v, 3);
+  return res;
+}
+
+int
+main ()
+{
+  vector signed int res = test ();
+  if (res[0] != 0xf0ffffff)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c b/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c
new file mode 100644
index 00000000000..fad9fa5df73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vsx_hw } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Verify it doesn't generate wrong code.  */
+
+#include "pr109069-2.h"
+
+int
+main ()
+{
+  vector unsigned char res1 = test1 ();
+  for (int i = 0; i < 16; i++)
+    if (res1[i] != 0xd)
+      __builtin_abort ();
+
+  vector signed short res2 = test2 ();
+  for (int i = 0; i < 8; i++)
+    if (res2[i] != 0x7777)
+      __builtin_abort ();
+
+  vector signed int res3 = test3 ();
+  vector unsigned int res4 = test4 ();
+  vector float res6 = test6 ();
+  for (int i = 0; i < 4; i++)
+    {
+      if (res3[i] != 0xbbbbbbbb)
+	__builtin_abort ();
+      if (res4[i] != 0x7070707)
+	__builtin_abort ();
+      U32b u;
+      u.f = res6[i];
+      if (u.i != 0x17171717)
+	__builtin_abort ();
+    }
+
+  vector unsigned long long res5 = test5 ();
+  vector double res7 = test7 ();
+  for (int i = 0; i < 2; i++)
+    {
+      if (res5[i] != 0x4545454545454545ll)
+	__builtin_abort ();
+      U64b u;
+      u.f = res7[i];
+      if (u.i != 0x5454545454545454ll)
+	__builtin_abort ();
+    }
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-2.c b/gcc/testsuite/gcc.target/powerpc/pr109069-2.c
new file mode 100644
index 00000000000..e71bbeb5df5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109069-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* Disable rs6000 optimize_swaps as it drops some REG_EQUAL
+   notes on const vector and affects test point here.  */
+/* { dg-options "-O2 -mvsx -mno-optimize-swaps" } */
+
+/* Verify we can optimize away vector shifting if every byte
+   of vector is the same.  */
+
+#include "pr109069-2.h"
+
+/* { dg-final { scan-assembler-not {\mvsldoi\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-2.h b/gcc/testsuite/gcc.target/powerpc/pr109069-2.h
new file mode 100644
index 00000000000..8b03bfb65fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109069-2.h
@@ -0,0 +1,83 @@
+#include <altivec.h>
+
+typedef union
+{
+  unsigned int i;
+  float f;
+} U32b;
+
+typedef union
+{
+  unsigned long long i;
+  double f;
+} U64b;
+
+__attribute__ ((noipa))
+vector unsigned char
+test1 ()
+{
+  vector unsigned char v = {0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd,
+			    0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd};
+  vector unsigned char res = vec_sld (v, v, 3);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector signed short
+test2 ()
+{
+  vector signed short v
+    = {0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777};
+  vector signed short res = vec_sld (v, v, 5);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector signed int
+test3 ()
+{
+  vector signed int v = {0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb};
+  vector signed int res = vec_sld (v, v, 7);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector unsigned int
+test4 ()
+{
+  vector unsigned int v = {0x07070707, 0x07070707, 0x07070707, 0x07070707};
+  vector unsigned int res = vec_sld (v, v, 9);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector unsigned long long
+test5 ()
+{
+  vector unsigned long long v = {0x4545454545454545ll, 0x4545454545454545ll};
+  vector unsigned long long res = vec_sld (v, v, 10);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector float
+test6 ()
+{
+  U32b u;
+  u.i = 0x17171717;
+  vector float vf = {u.f, u.f, u.f, u.f};
+  vector float res = vec_sld (vf, vf, 11);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector double
+test7 ()
+{
+  U64b u;
+  u.i = 0x5454545454545454ll;
+  vector double vf = {u.f, u.f};
+  vector double res = vec_sld (vf, vf, 13);
+  return res;
+}
+

commit 4ea5fe9722324dc5788e84e42e47d8bdbdd21410
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Apr 26 07:21:14 2023

    rs6000: Guard power9-vector for vsx_scalar_cmp_exp_qp_* [PR108758]
    
    __builtin_vsx_scalar_cmp_exp_qp_{eq,gt,lt,unordered} used
    to be guarded with condition TARGET_P9_VECTOR before new
    bif framework was introduced (r12-5752-gd08236359eb229),
    since r12-5752 they are placed under stanza ieee128-hw,
    that is to check condition TARGET_FLOAT128_HW, it caused
    test case float128-cmp2-runnable.c to fail at -m32 as the
    condition TARGET_FLOAT128_HW isn't satisified with -m32.
    
    By checking the commit history, I didn't see any notes on
    why this condition change on them was made, so this patch
    is to move these bifs from stanza ieee128-hw to stanza
    power9-vector as before.
    
            PR target/108758
    
    gcc/ChangeLog:
    
            * config/rs6000/rs6000-builtins.def
            (__builtin_vsx_scalar_cmp_exp_qp_eq, __builtin_vsx_scalar_cmp_exp_qp_gt
            __builtin_vsx_scalar_cmp_exp_qp_lt,
            __builtin_vsx_scalar_cmp_exp_qp_unordered): Move from stanza ieee128-hw
            to power9-vector.
    
    (cherry picked from commit 33a44e3aa81f9fdf8f6b87018abd4c664e545b53)

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index afc3cd692c1..dd39a27be40 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2796,6 +2796,19 @@
   const vsi __builtin_vsx_xxbrw_v4si (vsi);
     XXBRW_V4SI p9_xxbrw_v4si {}
 
+  const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128);
+    VSCEQPEQ xscmpexpqp_eq_kf {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128);
+    VSCEQPGT xscmpexpqp_gt_kf {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128);
+    VSCEQPLT xscmpexpqp_lt_kf {}
+
+  const signed int \
+      __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128);
+    VSCEQPUO xscmpexpqp_unordered_kf {}
+
 
 ; Miscellaneous P9 functions
 [power9]
@@ -2878,19 +2891,6 @@
   fpmath _Float128 __builtin_mulf128_round_to_odd (_Float128, _Float128);
     MULF128_ODD mulkf3_odd {}
 
-  const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128);
-    VSCEQPEQ xscmpexpqp_eq_kf {}
-
-  const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128);
-    VSCEQPGT xscmpexpqp_gt_kf {}
-
-  const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128);
-    VSCEQPLT xscmpexpqp_lt_kf {}
-
-  const signed int \
-      __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128);
-    VSCEQPUO xscmpexpqp_unordered_kf {}
-
   fpmath _Float128 __builtin_sqrtf128_round_to_odd (_Float128);
     SQRTF128_ODD sqrtkf2_odd {}
 

commit a4308f9d432a108026d6ae8ad99d40a52eea341f
Author: Martin Uecker <uecker@tugraz.at>
Date:   Wed Feb 8 15:02:43 2023

    Fix ICE related to implicit access attributes for VLA arguments [PR105660]
    
    When constructing the specifier string when merging an access attribute
    that encodes information about VLA arguments, the string was constructed
    in random order by iterating through a hash table. Fix this by iterating
    though the list of arguments.
    
    gcc/c-family/Changelog:
            PR c/105660
            * c-attribs.cc (append_access_attr): Use order of arguments when
            construction string.
            (append_access_attr_idxs): Rename and make static.
            * c-warn.cc (warn_parm_array_mismatch): Add assertion.
    
    gcc/testsuite/ChangeLog:
            PR c/105660
            * gcc.dg/pr105660-1.c: New test.
            * gcc.dg/pr105660-2.c: New test.
    
    (cherry picked from commit 3057d7928c0dbc78dbf748c9621ccd102e06beee)

diff --git a/gcc/c-family/c-attribs.cc b/gcc/c-family/c-attribs.cc
index 111a33f405a..8221733613e 100644
--- a/gcc/c-family/c-attribs.cc
+++ b/gcc/c-family/c-attribs.cc
@@ -4624,22 +4624,27 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
   rdwr_map cur_idxs;
   init_attr_rdwr_indices (&cur_idxs, attrs);
 
+  tree args = TYPE_ARG_TYPES (node[0]);
+  int argpos = 0;
   std::string spec;
-  for (auto it = new_idxs.begin (); it != new_idxs.end (); ++it)
+  for (tree arg = args; arg; arg = TREE_CHAIN (arg), argpos++)
     {
-      const auto &newaxsref = *it;
+      const attr_access* const newa = new_idxs.get (argpos);
+
+      if (!newa)
+	continue;
 
       /* The map has two equal entries for each pointer argument that
 	 has an associated size argument.  Process just the entry for
 	 the former.  */
-      if ((unsigned)newaxsref.first != newaxsref.second.ptrarg)
+      if ((unsigned)argpos != newa->ptrarg)
 	continue;
 
-      const attr_access* const cura = cur_idxs.get (newaxsref.first);
+      const attr_access* const cura = cur_idxs.get (argpos);
       if (!cura)
 	{
 	  /* The new attribute needs to be added.  */
-	  tree str = newaxsref.second.to_internal_string ();
+	  tree str = newa->to_internal_string ();
 	  spec += TREE_STRING_POINTER (str);
 	  continue;
 	}
@@ -4647,7 +4652,6 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
       /* The new access spec refers to an array/pointer argument for
 	 which an access spec already exists.  Check and diagnose any
 	 conflicts.  If no conflicts are found, merge the two.  */
-      const attr_access* const newa = &newaxsref.second;
 
       if (!attrstr)
 	{
@@ -4782,7 +4786,7 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
 	continue;
 
       /* Merge the CURA and NEWA.  */
-      attr_access merged = newaxsref.second;
+      attr_access merged = *newa;
 
       /* VLA seen in a declaration takes precedence.  */
       if (cura->minsize == HOST_WIDE_INT_M1U)
@@ -4808,9 +4812,9 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
 
 /* Convenience wrapper for the above.  */
 
-tree
-append_access_attr (tree node[3], tree attrs, const char *attrstr,
-		    char code, HOST_WIDE_INT idxs[2])
+static tree
+append_access_attr_idxs (tree node[3], tree attrs, const char *attrstr,
+			 char code, HOST_WIDE_INT idxs[2])
 {
   char attrspec[80];
   int n = sprintf (attrspec, "%c%u", code, (unsigned) idxs[0] - 1);
@@ -5101,7 +5105,7 @@ handle_access_attribute (tree node[3], tree name, tree args, int flags,
      attributes specified on previous declarations of the same type
      and if not, concatenate the two.  */
   const char code = attr_access::mode_chars[mode];
-  tree new_attrs = append_access_attr (node, attrs, attrstr, code, idxs);
+  tree new_attrs = append_access_attr_idxs (node, attrs, attrstr, code, idxs);
   if (!new_attrs)
     return NULL_TREE;
 
@@ -5114,7 +5118,7 @@ handle_access_attribute (tree node[3], tree name, tree args, int flags,
     {
       /* Repeat for the previously declared type.  */
       attrs = TYPE_ATTRIBUTES (TREE_TYPE (node[1]));
-      new_attrs = append_access_attr (node, attrs, attrstr, code, idxs);
+      new_attrs = append_access_attr_idxs (node, attrs, attrstr, code, idxs);
       if (!new_attrs)
 	return NULL_TREE;
 
diff --git a/gcc/c-family/c-warn.cc b/gcc/c-family/c-warn.cc
index 1e5a64260a3..9634351a4d3 100644
--- a/gcc/c-family/c-warn.cc
+++ b/gcc/c-family/c-warn.cc
@@ -3628,6 +3628,8 @@ warn_parm_array_mismatch (location_t origloc, tree fndecl, tree newparms)
       for (tree newvbl = newa->size, curvbl = cura->size; newvbl;
 	   newvbl = TREE_CHAIN (newvbl), curvbl = TREE_CHAIN (curvbl))
 	{
+	  gcc_assert (curvbl);
+
 	  tree newpos = TREE_PURPOSE (newvbl);
 	  tree curpos = TREE_PURPOSE (curvbl);
 
diff --git a/gcc/testsuite/gcc.dg/pr105660-1.c b/gcc/testsuite/gcc.dg/pr105660-1.c
new file mode 100644
index 00000000000..d4454f04c43
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr105660-1.c
@@ -0,0 +1,13 @@
+/* PR105660
+ * { dg-do compile }
+ * { dg-options "-std=c17" }
+ */
+
+void gatherConservativeVars(int, int, int, int, int, int, int Hnvar, int,
+                            int Hnyt, int Hnxyt, int, int Hstep, double[Hnyt],
+                            double[Hnvar][Hstep][Hnxyt]);
+void gatherConservativeVars(int, int, int, int, int, int, int Hnvar, int, int Hnyt,
+                            int Hnxyt, int, int Hstep, double[Hnyt],
+                            double[Hnvar][Hstep][Hnxyt]);
+
+
diff --git a/gcc/testsuite/gcc.dg/pr105660-2.c b/gcc/testsuite/gcc.dg/pr105660-2.c
new file mode 100644
index 00000000000..29fd82f923b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr105660-2.c
@@ -0,0 +1,12 @@
+/* PR105660
+ * { dg-do compile }
+ * { dg-options "-Wall -std=c17" }
+ */
+
+
+struct bat_gen_conf_s;
+void batch_generator_create2(struct bat_gen_conf_s* config, int D, int N, const long bat_dims[D][N], const long tot_dims[D][N], const long tot_strs[D][N], const _Complex float* data[D]);
+void batch_generator_create2(struct bat_gen_conf_s* config, int D, int N, const long bat_dims[D][N], const long tot_dims[D][N], const long tot_strs[D][N], const _Complex float* data[D]);
+
+
+

commit 2835feb9c29de9167c7af19209065357899b808d
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue May 9 12:10:07 2023

    tree-ssa-ccp, wide-int: Fix up handling of [LR]ROTATE_EXPR in bitwise ccp [PR109778]
    
    The following testcase is miscompiled, because bitwise ccp2 handles
    a rotate with a signed type incorrectly.
    Seems tree-ssa-ccp.cc has the only callers of wi::[lr]rotate with 3
    arguments, all other callers just rotate in the right precision and
    I think work correctly.  ccp works with widest_ints and so rotations
    by the excessive precision certainly don't match what it wants
    when it sees a rotate in some specific bitsize.  Still, if it is
    unsigned rotate and the widest_int is zero extended from width,
    the functions perform left shift and logical right shift on the value
    and then at the end zero extend the result of left shift and uselessly
    also the result of logical right shift and return | of that.
    On the testcase we the signed char rrotate by 4 argument is
    CONSTANT -75 i.e. 0xffffffff....fffffb5 with mask 2.
    The mask is correctly rotated to 0x20, but because the 8-bit constant
    is sign extended to 192-bit one, the logical right shift by 4 doesn't
    yield expected 0xb, but gives 0xfffffffffff....ffffb, and then
    return wi::zext (left, width) | wi::zext (right, width); where left is
    0xfffffff....fb50, so we return 0xfb instead of the expected
    0x5b.
    
    The following patch fixes that by doing the zero extension in case of
    the right variable before doing wi::lrshift rather than after it.
    
    Also, wi::[lr]rotate widht width < precision always zero extends
    the result.  I'm afraid it can't do better because it doesn't know
    if it is done for an unsigned or signed type, but the caller in this
    case knows that very well, so I've done the extension based on sgn
    in the caller.  E.g. 0x5b rotated right (or left) by 4 with width 8
    previously gave 0xb5, but sgn == SIGNED in widest_int it should be
    0xffffffff....fffb5 instead.
    
    2023-05-09  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/109778
            * wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on
            wi::zext (x, width) rather than x if width != precision, rather
            than using wi::zext (right, width) after the shift.
            * tree-ssa-ccp.cc (bit_value_binop): Call wi::ext on the results
            of wi::lrotate or wi::rrotate.
    
            * gcc.c-torture/execute/pr109778.c: New test.
    
    (cherry picked from commit a8302d2a4669984c7c287d12ef5b37cde6699c80)

diff --git a/gcc/testsuite/gcc.c-torture/execute/pr109778.c b/gcc/testsuite/gcc.c-torture/execute/pr109778.c
new file mode 100644
index 00000000000..309fbf413e0
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr109778.c
@@ -0,0 +1,26 @@
+/* PR tree-optimization/109778 */
+
+int a, b, c, d, *e = &c;
+
+static inline unsigned
+foo (unsigned char x)
+{
+  x = 1 | x << 1;
+  x = x >> 4 | x << 4;
+  return x;
+}
+
+static inline void
+bar (unsigned x)
+{
+  *e = 8 > foo (x + 86) - 86;
+}
+
+int
+main ()
+{
+  d = a && b;
+  bar (d + 4);
+  if (c != 1)
+    __builtin_abort ();
+}
diff --git a/gcc/tree-ssa-ccp.cc b/gcc/tree-ssa-ccp.cc
index 29661884b92..42a02dccaeb 100644
--- a/gcc/tree-ssa-ccp.cc
+++ b/gcc/tree-ssa-ccp.cc
@@ -1552,6 +1552,8 @@ bit_value_binop (enum tree_code code, signop sgn, int width,
 		  *mask = wi::lrotate (r1mask, shift, width);
 		  *val = wi::lrotate (r1val, shift, width);
 		}
+	      *mask = wi::ext (*mask, width, sgn);
+	      *val = wi::ext (*val, width, sgn);
 	    }
 	}
       else if (wi::ltu_p (r2val | r2mask, width)
@@ -1593,8 +1595,8 @@ bit_value_binop (enum tree_code code, signop sgn, int width,
 	      /* Accumulate the result.  */
 	      res_mask |= tmp_mask | (res_val ^ tmp_val);
 	    }
-	  *val = wi::bit_and_not (res_val, res_mask);
-	  *mask = res_mask;
+	  *val = wi::ext (wi::bit_and_not (res_val, res_mask), width, sgn);
+	  *mask = wi::ext (res_mask, width, sgn);
 	}
       break;
 
diff --git a/gcc/wide-int.h b/gcc/wide-int.h
index bd0d9a2d4d5..93f293ce841 100644
--- a/gcc/wide-int.h
+++ b/gcc/wide-int.h
@@ -3169,9 +3169,11 @@ wi::lrotate (const T1 &x, const T2 &y, unsigned int width)
     width = precision;
   WI_UNARY_RESULT (T2) ymod = umod_trunc (y, width);
   WI_UNARY_RESULT (T1) left = wi::lshift (x, ymod);
-  WI_UNARY_RESULT (T1) right = wi::lrshift (x, wi::sub (width, ymod));
+  WI_UNARY_RESULT (T1) right
+    = wi::lrshift (width != precision ? wi::zext (x, width) : x,
+		   wi::sub (width, ymod));
   if (width != precision)
-    return wi::zext (left, width) | wi::zext (right, width);
+    return wi::zext (left, width) | right;
   return left | right;
 }
 
@@ -3186,10 +3188,11 @@ wi::rrotate (const T1 &x, const T2 &y, unsigned int width)
   if (width == 0)
     width = precision;
   WI_UNARY_RESULT (T2) ymod = umod_trunc (y, width);
-  WI_UNARY_RESULT (T1) right = wi::lrshift (x, ymod);
+  WI_UNARY_RESULT (T1) right
+    = wi::lrshift (width != precision ? wi::zext (x, width) : x, ymod);
   WI_UNARY_RESULT (T1) left = wi::lshift (x, wi::sub (width, ymod));
   if (width != precision)
-    return wi::zext (left, width) | wi::zext (right, width);
+    return wi::zext (left, width) | right;
   return left | right;
 }
 

commit 7408a0b93e6f6b3ce9b6be17bb9b5d2307f5ecf1
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue May 9 12:14:18 2023

    testsuite: Add further testcase for already fixed PR [PR109778]
    
    I came up with a testcase which reproduces all the way to r10-7469.
    LTO to avoid early inlining it, so that ccp handles rotates and not
    shifts before they are turned into rotates.
    
    2023-05-09  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/109778
            * gcc.dg/lto/pr109778_0.c: New test.
            * gcc.dg/lto/pr109778_1.c: New file.
    
    (cherry picked from commit c2cf2dc988eb93551fa1c01d3f8d73ef21f39dc5)

diff --git a/gcc/testsuite/gcc.dg/lto/pr109778_0.c b/gcc/testsuite/gcc.dg/lto/pr109778_0.c
new file mode 100644
index 00000000000..3c6e1b8f7b7
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/lto/pr109778_0.c
@@ -0,0 +1,22 @@
+/* PR tree-optimization/109778 */
+/* { dg-lto-do run } */
+/* { dg-lto-options { "-O2 -flto" } } */
+/* { dg-require-effective-target int32 } */
+
+int bar (int);
+
+__attribute__((noipa)) int
+foo (int x)
+{
+  x = bar (x);
+  x = (x << 16) | (int) ((unsigned) x >> 16);
+  return x & 0x10000000;
+}
+
+int
+main ()
+{
+  if (foo (0) || foo (-1))
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/lto/pr109778_1.c b/gcc/testsuite/gcc.dg/lto/pr109778_1.c
new file mode 100644
index 00000000000..d18a7209983
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/lto/pr109778_1.c
@@ -0,0 +1,7 @@
+int
+bar (int x)
+{
+  x &= 0x22222222;
+  x |= (int) 0xf1234567U;
+  return x;
+}

commit 56da68414b5b5f0124cac29756c88710e5752762
Author: Patrick Palka <ppalka@redhat.com>
Date:   Sat Apr 1 18:01:30 2023

    c++: NTTP constraint depending on outer parms [PR109160]
    
    Here we're crashing during satisfaction for the NTTP 'C<B> auto V'
    ultimately because convert_template_argument / unify don't pass all
    outer template arguments to do_auto_deduction, and during satisfaction
    we need to know all arguments.  While these callers do pass some outer
    arguments, they are only sufficient to properly substitute the
    (level-lowered) 'auto' and are not necessarily the entire set.
    
    Fortunately it seems these callers have access to the full set of outer
    arguments via convert_template_argument's 'in_decl' parameter and
    unify's 'tparms' parameter.  So this patch adds a new parameter to
    do_auto_deduction, used only during adc_unify deduction, through which
    these callers can pass the enclosing (partially instantiated) template
    and from which do_auto_deduction can obtain _all_ outer template
    arguments for sake of satisfaction.
    
    This patch also ensures that the 'in_decl' argument passed to
    coerce_template_parms is always a TEMPLATE_DECL, which in turn allows us
    to pass it as-is to do_auto_deduction; the only coerce_template_parms
    caller that needed adjustment was tsubst_decl it seems.
    
            PR c++/109160
    
    gcc/cp/ChangeLog:
    
            * cp-tree.h (do_auto_deduction): Add defaulted tmpl parameter.
            * pt.cc (convert_template_argument): Pass 'in_decl' as 'tmpl' to
            do_auto_deduction.
            (tsubst_decl) <case VAR_/TYPE_DECL>: Pass 'tmpl' instead of 't' as
            'in_decl' to coerce_template_parms.
            (unify) <case TEMPLATE_PARM_INDEX>: Pass TPARMS_PRIMARY_TEMPLATE
            as 'tmpl' to do_auto_deduction.
            (do_auto_deduction): Document default arguments.  Rename local
            variable 'tmpl' to 'ctmpl'.  Use 'tmpl' to obtain a full set of
            template arguments for satisfaction in the adc_unify case.
    
    gcc/testsuite/ChangeLog:
    
            * g++.dg/cpp2a/concepts-placeholder12.C: New test.
    
    (cherry picked from commit a5de246535db1b4fdc61287f27de0fdd074fc4b3)

diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 64b3196d1e9..6906b9bfdc8 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -7295,7 +7295,8 @@ extern tree do_auto_deduction                   (tree, tree, tree,
                                                  auto_deduction_context
 						 = adc_unspecified,
 						 tree = NULL_TREE,
-						 int = LOOKUP_NORMAL);
+						 int = LOOKUP_NORMAL,
+						 tree = NULL_TREE);
 extern tree type_uses_auto			(tree);
 extern tree type_uses_auto_or_concept		(tree);
 extern void append_type_to_template_for_access_check (tree, tree, tree,
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index 12d91974d32..c7f4a95a723 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -8636,7 +8636,7 @@ convert_template_argument (tree parm,
       else if (tree a = type_uses_auto (t))
 	{
 	  t = do_auto_deduction (t, arg, a, complain, adc_unify, args,
-				 LOOKUP_IMPLICIT);
+				 LOOKUP_IMPLICIT, /*tmpl=*/in_decl);
 	  if (t == error_mark_node)
 	    return error_mark_node;
 	}
@@ -15028,7 +15028,7 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain)
 		if (argvec != error_mark_node)
 		  argvec = (coerce_innermost_template_parms
 			    (DECL_TEMPLATE_PARMS (gen_tmpl),
-			     argvec, t, complain,
+			     argvec, tmpl, complain,
 			     /*all*/true, /*defarg*/true));
 		if (argvec == error_mark_node)
 		  RETURN (error_mark_node);
@@ -24455,7 +24455,9 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict,
 	  if (tree a = type_uses_auto (tparm))
 	    {
 	      tparm = do_auto_deduction (tparm, arg, a,
-					 complain, adc_unify, targs);
+					 complain, adc_unify, targs,
+					 LOOKUP_NORMAL,
+					 TPARMS_PRIMARY_TEMPLATE (tparms));
 	      if (tparm == error_mark_node)
 		return 1;
 	    }
@@ -30340,13 +30342,20 @@ do_class_deduction (tree ptype, tree tmpl, tree init,
    adc_requirement contexts to communicate the necessary template arguments
    to satisfaction.  OUTER_TARGS is ignored in other contexts.
 
-   For partial-concept-ids, extra args may be appended to the list of deduced
-   template arguments prior to determining constraint satisfaction.  */
+   Additionally for adc_unify contexts TMPL is the template for which TYPE
+   is a template parameter type.
+
+   For partial-concept-ids, extra args from OUTER_TARGS, TMPL and the current
+   scope may be appended to the list of deduced template arguments prior to
+   determining constraint satisfaction as appropriate.  */
 
 tree
 do_auto_deduction (tree type, tree init, tree auto_node,
-                   tsubst_flags_t complain, auto_deduction_context context,
-		   tree outer_targs, int flags)
+		   tsubst_flags_t complain /* = tf_warning_or_error */,
+		   auto_deduction_context context /* = adc_unspecified */,
+		   tree outer_targs /* = NULL_TREE */,
+		   int flags /* = LOOKUP_NORMAL */,
+		   tree tmpl /* = NULL_TREE */)
 {
   if (init == error_mark_node)
     return error_mark_node;
@@ -30365,9 +30374,9 @@ do_auto_deduction (tree type, tree init, tree auto_node,
      auto_node.  */
   complain &= ~tf_partial;
 
-  if (tree tmpl = CLASS_PLACEHOLDER_TEMPLATE (auto_node))
+  if (tree ctmpl = CLASS_PLACEHOLDER_TEMPLATE (auto_node))
     /* C++17 class template argument deduction.  */
-    return do_class_deduction (type, tmpl, init, flags, complain);
+    return do_class_deduction (type, ctmpl, init, flags, complain);
 
   if (init == NULL_TREE || TREE_TYPE (init) == NULL_TREE)
     /* Nothing we can do with this, even in deduction context.  */
@@ -30527,7 +30536,10 @@ do_auto_deduction (tree type, tree init, tree auto_node,
 		}
 	    }
 
-      tree full_targs = add_to_template_args (outer_targs, targs);
+      tree full_targs = outer_targs;
+      if (context == adc_unify && tmpl)
+	full_targs = add_outermost_template_args (tmpl, full_targs);
+      full_targs = add_to_template_args (full_targs, targs);
 
       /* HACK: Compensate for callers not always communicating all levels of
 	 outer template arguments by filling in the outermost missing levels
diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-placeholder12.C b/gcc/testsuite/g++.dg/cpp2a/concepts-placeholder12.C
new file mode 100644
index 00000000000..22f0ac5e26a
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/concepts-placeholder12.C
@@ -0,0 +1,29 @@
+// PR c++/109160
+// { dg-do compile { target c++20 } }
+
+template<class T, bool B>
+concept C = B;
+
+template<int> struct X { };
+
+template<bool B>
+struct A {
+  template<C<B> auto V> static void f();
+  template<C<B> auto V> static void g(X<V>);
+  template<C<B> auto V> static inline int value;
+  template<C<B> auto V> struct D { };
+};
+
+int main() {
+  A<true>::f<0>();
+  A<false>::f<0>(); // { dg-error "no match|constraints" }
+
+  A<true>::g(X<0>{});
+  A<false>::g(X<0>{}); // { dg-error "no match|constraints" }
+
+  bool v1 = A<true>::value<0>;
+  bool v2 = A<false>::value<0>;  // { dg-error "constraints" }
+
+  A<true>::D<0> d1;
+  A<false>::D<0> d2; // { dg-error "constraints" }
+}

commit 0069ce6631880776a44fb8408c6428c0812285cf
Author: Dan Horák <dan@danny.cz>
Date:   Wed May 3 21:29:09 2023

    libffi: fix handling of homogeneous float128 structs (#689)
    
    If there is a homogeneous struct with float128 members, they should be
    copied to vector register save area. The current code incorrectly copies
    only the value of the first member, not increasing the pointer with each
    iteration. Fix this.
    
    Merged from upstream libffi commit: 464b4b66e3cf3b5489e730c1466ee1bf825560e0
    
    2023-05-03  Dan Horák <dan@danny.cz>
    
    libffi/
            PR libffi/109447
            * src/powerpc/ffi_linux64.c (ffi_prep_args64): Update arg.f128 pointer.
    
    (cherry picked from commit 043550bceea7881163bba5d8a0486bb100a05809)

diff --git a/libffi/src/powerpc/ffi_linux64.c b/libffi/src/powerpc/ffi_linux64.c
index 4d50878e402..3454dacd3d6 100644
--- a/libffi/src/powerpc/ffi_linux64.c
+++ b/libffi/src/powerpc/ffi_linux64.c
@@ -680,7 +680,7 @@ ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)
                     {
                       if (vecarg_count < NUM_VEC_ARG_REGISTERS64
                           && i < nfixedargs)
-		        memcpy (vec_base.f128++, arg.f128, sizeof (float128));
+		        memcpy (vec_base.f128++, arg.f128++, sizeof (float128));
                       else
 		        memcpy (next_arg.f128, arg.f128++, sizeof (float128));
                       if (++next_arg.f128 == gpr_end.f128)

commit dee018e3ad66fa304dcce013b0a30067171f43d9
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 10 02:22:01 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 07376405660..9a940060c41 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,40 @@
+2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109778
+	* wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on
+	wi::zext (x, width) rather than x if width != precision, rather
+	than using wi::zext (right, width) after the shift.
+	* tree-ssa-ccp.cc (bit_value_binop): Call wi::ext on the results
+	of wi::lrotate or wi::rrotate.
+
+2023-05-09  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-04-26  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/108758
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_vsx_scalar_cmp_exp_qp_eq, __builtin_vsx_scalar_cmp_exp_qp_gt
+	__builtin_vsx_scalar_cmp_exp_qp_lt,
+	__builtin_vsx_scalar_cmp_exp_qp_unordered): Move from stanza ieee128-hw
+	to power9-vector.
+
+2023-05-09  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-04-26  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/109069
+	* config/rs6000/altivec.md (sldoi_to_mov<mode>): Replace predicate
+	easy_vector_constant with const_vector_each_byte_same, add
+	handlings in preparation for !easy_vector_constant, and update
+	VECTOR_UNIT_ALTIVEC_OR_VSX_P with VECTOR_MEM_ALTIVEC_OR_VSX_P.
+	* config/rs6000/predicates.md (const_vector_each_byte_same): New
+	predicate.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d3869af5806..c5a9ee88f24 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230509
+20230510
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 054a5330ac6..7fb93f5f454 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,14 @@
+2023-05-09  Martin Uecker  <uecker@tugraz.at>
+
+	Backported from master:
+	2023-02-18  Martin Uecker  <uecker@tugraz.at>
+
+	PR c/105660
+	* c-attribs.cc (append_access_attr): Use order of arguments when
+	construction string.
+	(append_access_attr_idxs): Rename and make static.
+	* c-warn.cc (warn_parm_array_mismatch): Add assertion.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 8de4af385a8..5b4ecfa4eb9 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,30 @@
+2023-05-09  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-04-01  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/109160
+	* cp-tree.h (do_auto_deduction): Add defaulted tmpl parameter.
+	* pt.cc (convert_template_argument): Pass 'in_decl' as 'tmpl' to
+	do_auto_deduction.
+	(tsubst_decl) <case VAR_/TYPE_DECL>: Pass 'tmpl' instead of 't' as
+	'in_decl' to coerce_template_parms.
+	(unify) <case TEMPLATE_PARM_INDEX>: Pass TPARMS_PRIMARY_TEMPLATE
+	as 'tmpl' to do_auto_deduction.
+	(do_auto_deduction): Document default arguments.  Rename local
+	variable 'tmpl' to 'ctmpl'.  Use 'tmpl' to obtain a full set of
+	template arguments for satisfaction in the adc_unify case.
+
+2023-05-09  Jason Merrill  <jason@redhat.com>
+
+	PR c++/106740
+	PR c++/105852
+	* decl.cc (duplicate_decls): Change non-templated friend
+	check to an assert.
+	* pt.cc	(tsubst_function_decl): Don't set DECL_TEMPLATE_INFO
+	on non-templated friends.
+	(tsubst_friend_function): Adjust.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c2333b51c6e..6e7d4595205 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,55 @@
+2023-05-09  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-04-01  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/109160
+	* g++.dg/cpp2a/concepts-placeholder12.C: New test.
+
+2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109778
+	* gcc.dg/lto/pr109778_0.c: New test.
+	* gcc.dg/lto/pr109778_1.c: New file.
+
+2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109778
+	* gcc.c-torture/execute/pr109778.c: New test.
+
+2023-05-09  Martin Uecker  <uecker@tugraz.at>
+
+	Backported from master:
+	2023-02-18  Martin Uecker  <uecker@tugraz.at>
+
+	PR c/105660
+	PR c/105660
+	* gcc.dg/pr105660-1.c: New test.
+	* gcc.dg/pr105660-2.c: New test.
+
+2023-05-09  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-04-26  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/109069
+	* gcc.target/powerpc/pr109069-1.c: New test.
+	* gcc.target/powerpc/pr109069-2-run.c: New test.
+	* gcc.target/powerpc/pr109069-2.c: New test.
+	* gcc.target/powerpc/pr109069-2.h: New test.
+
+2023-05-09  Jason Merrill  <jason@redhat.com>
+
+	PR c++/106740
+	PR c++/105852
+	* g++.dg/template/friend78.C: New test.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/libffi/ChangeLog b/libffi/ChangeLog
index f9668c45954..3e2b500db22 100644
--- a/libffi/ChangeLog
+++ b/libffi/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-09  Dan Horák  <dan@danny.cz>
+
+	Backported from master:
+	2023-05-06  Dan Horák  <dan@danny.cz>
+
+	PR libffi/109447
+	* src/powerpc/ffi_linux64.c (ffi_prep_args64): Update arg.f128 pointer.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.

commit 5f803e68beee9f71c12c112ccda872997919f9cc
Author: Richard Biener <rguenther@suse.de>
Date:   Wed May 10 15:36:12 2023

    Avoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABI
    
    The following forces the g++.dg/torture/pr106922.C testcase to use
    the C++11 libstdc++ ABI and checks whether that worked.
    
    gcc/testsuite/
            * g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1.
    
    (cherry picked from commit a056a9868e6ecab24b0b7e4e12e846097b8c8fb0)

diff --git a/gcc/testsuite/g++.dg/torture/pr106922.C b/gcc/testsuite/g++.dg/torture/pr106922.C
index 046fc6cce76..b0c1489fbdc 100644
--- a/gcc/testsuite/g++.dg/torture/pr106922.C
+++ b/gcc/testsuite/g++.dg/torture/pr106922.C
@@ -4,8 +4,16 @@
 // -O1 doesn't iterate VN and thus has bogus uninit diagnostics
 // { dg-skip-if "" { *-*-* } { "-O1" } { "" } }
 
+// The testcase still emits bogus diagnostics with the pre-C++11 ABI
+#undef _GLIBCXX_USE_CXX11_ABI
+#define _GLIBCXX_USE_CXX11_ABI 1
+
 #include <vector>
 
+// When the library is not dual-ABI and defaults to old just compile
+// an empty TU
+#if _GLIBCXX_USE_CXX11_ABI
+
 #include <optional>
 template <class T>
 using Optional = std::optional<T>;
@@ -46,3 +54,4 @@ void test()
         externals.external2 = internal2;
     }
 }
+#endif

commit 896f43215ec8822cbcaee372009ee6768880b3cd
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu May 11 02:20:19 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c5a9ee88f24..4744698a31c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230510
+20230511
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6e7d4595205..817770798b6 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2023-05-10  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-05-10  Richard Biener  <rguenther@suse.de>
+
+	* g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1.
+
 2023-05-09  Patrick Palka  <ppalka@redhat.com>
 
 	Backported from master:

commit 16a76499f916b5b6d11bccc03cc0d16b2b1ee31b
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Wed Nov 16 13:22:04 2022

    libstdc++: Fix std::any pretty printer
    
    The recent changes to FilteringTypePrinter affect the result of
    gdb.lookup_type('std::string') in StdExpAnyPrinter, causing it to always
    return the std::__cxx11::basic_string specialization. This then causes a
    gdb.error exception when trying to lookup the std::any manager type for
    a specialization using that string, but that manager was never
    instantiated in the program. This causes FAILs when running the tests
    with -D_GLIBCXX_USE_CXX11_ABI=0:
    
    FAIL: libstdc++-prettyprinters/libfundts.cc print as
    FAIL: libstdc++-prettyprinters/libfundts.cc print as
    
    The ugly solution used in this patch is to repeat the lookup for every
    type that std::string could be a typedef for, and hope it only works for
    one of them.
    
    libstdc++-v3/ChangeLog:
    
            * python/libstdcxx/v6/printers.py (StdExpAnyPrinter): Make
            expansion of std::string in manager name more robust.
    
    (cherry picked from commit 3c54805d03ac1bcc3d8547ffb5e6c4e1f301a7a2)

diff --git a/libstdc++-v3/python/libstdcxx/v6/printers.py b/libstdc++-v3/python/libstdcxx/v6/printers.py
index bb06a4959ee..d27a25bd96f 100644
--- a/libstdc++-v3/python/libstdcxx/v6/printers.py
+++ b/libstdc++-v3/python/libstdcxx/v6/printers.py
@@ -1216,9 +1216,34 @@ class StdExpAnyPrinter(SingleObjContainerPrinter):
             mgrname = m.group(1)
             # FIXME need to expand 'std::string' so that gdb.lookup_type works
             if 'std::string' in mgrname:
-                mgrname = re.sub("std::string(?!\w)", str(gdb.lookup_type('std::string').strip_typedefs()), m.group(1))
-
-            mgrtype = gdb.lookup_type(mgrname)
+                # This lookup for std::string might return the __cxx11 version,
+                # but that's not necessarily the one used by the std::any
+                # manager function we're trying to find.
+                strings = {str(gdb.lookup_type('std::string').strip_typedefs())}
+                # So also consider all the other possible std::string types!
+                s = 'basic_string<char, std::char_traits<char>, std::allocator<char> >'
+                quals = ['std::', 'std::__cxx11::', 'std::' + _versioned_namespace]
+                strings |= {q+s for q in quals} # set of unique strings
+                mgrtypes = []
+                for s in strings:
+                    try:
+                        x = re.sub("std::string(?!\w)", s, m.group(1))
+                        # The following lookup might raise gdb.error if the
+                        # manager function was never instantiated for 's' in the
+                        # program, because there will be no such type.
+                        mgrtypes.append(gdb.lookup_type(x))
+                    except gdb.error:
+                        pass
+                if len(mgrtypes) != 1:
+                    # FIXME: this is unlikely in practice, but possible for
+                    # programs that use both old and new string types with
+                    # std::any in a single program. Can we do better?
+                    # Maybe find the address of each type's _S_manage and
+                    # compare to the address stored in _M_manager?
+                    raise ValueError('Cannot uniquely determine std::string type used in std::any')
+                mgrtype = mgrtypes[0]
+            else:
+                mgrtype = gdb.lookup_type(mgrname)
             self.contained_type = mgrtype.template_argument(0)
             valptr = None
             if '::_Manager_internal' in mgrname:

commit 52b222ac0a48f5061f1f3cfa0c1f4c418f42267d
Author: Ian Lance Taylor <iant@golang.org>
Date:   Thu May 11 18:19:26 2023

    syscall: add prlimit
    
    As of https://go.dev/cl/476695 golang.org/x/sys/unix can call
    syscall.prlimit, so we need such a function in libgo.

diff --git a/libgo/go/syscall/libcall_linux.go b/libgo/go/syscall/libcall_linux.go
index 96974bd3269..a39f408151a 100644
--- a/libgo/go/syscall/libcall_linux.go
+++ b/libgo/go/syscall/libcall_linux.go
@@ -188,6 +188,14 @@ func Gettid() (tid int) {
 //sys	PivotRoot(newroot string, putold string) (err error)
 //pivot_root(newroot *byte, putold *byte) _C_int
 
+// Used by golang.org/x/sys/unix.
+//sys	prlimit(pid int, resource int, newlimit *Rlimit, oldlimit *Rlimit) (err error)
+//prlimit(pid Pid_t, resource _C_int, newlimit *Rlimit, oldlimit *Rlimit) _C_int
+
+func Prlimit(pid int, resource int, newlimit *Rlimit, oldlimit *Rlimit) error {
+	return prlimit(pid, resource, newlimit, oldlimit)
+}
+
 //sys	Removexattr(path string, attr string) (err error)
 //removexattr(path *byte, name *byte) _C_int
 

commit 866beb0a04d7e5ad21f2d7b5c7acca2307f38817
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 12 02:22:32 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4744698a31c..d44f41a9779 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230511
+20230512
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 3b6da1e57dd..c9fc4ec3fad 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-11  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2022-11-16  Jonathan Wakely  <jwakely@redhat.com>
+
+	* python/libstdcxx/v6/printers.py (StdExpAnyPrinter): Make
+	expansion of std::string in manager name more robust.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.

commit 0bfba6442264af83382c26f60286bd33c901178a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 13 02:20:39 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d44f41a9779..9e964bcb0cd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230512
+20230513

commit b069462ecc7a7671d7c2807dd17185612def3b05
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 14 02:20:45 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9e964bcb0cd..1d22f342aef 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230513
+20230514

commit ecf9ea59d8fcec48da6043c07db3f25b3151ab84
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon May 15 02:21:20 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1d22f342aef..0bf2258d634 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230514
+20230515

commit efcca6481eab1853b646095af642076faa62d3a5
Author: liuhongt <hongtao.liu@intel.com>
Date:   Wed May 10 09:16:58 2023

    x86: Add a new option -mdaz-ftz to enable FTZ and DAZ flags in MXCSR.
    
        if (mdaz-ftz)
          link crtfastmath.o
        else if ((Ofast || ffast-math || funsafe-math-optimizations)
                 && !mno-daz-ftz)
          link crtfastmath.o
        else
          Don't link crtfastmath.o
    
    gcc/ChangeLog:
    
            * config/i386/cygwin.h (ENDFILE_SPEC): Link crtfastmath.o
            whenever -mdaz-ftz is specified. Don't link crtfastmath.o
            when -mno-daz-ftz is specified.
            * config/i386/darwin.h (ENDFILE_SPEC): Ditto.
            * config/i386/gnu-user-common.h
            (GNU_USER_TARGET_MATHFILE_SPEC): Ditto.
            * config/i386/mingw32.h (ENDFILE_SPEC): Ditto.
            * config/i386/i386.opt (mdaz-ftz): New option.
            * doc/invoke.texi (x86 options): Document mftz-daz.

diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h
index d06eda369cf..5412c5d4479 100644
--- a/gcc/config/i386/cygwin.h
+++ b/gcc/config/i386/cygwin.h
@@ -57,7 +57,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef ENDFILE_SPEC
 #define ENDFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}\
+  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{!shared:%:if-exists(default-manifest.o%s)}\
    %{fvtable-verify=none:%s; \
     fvtable-verify=preinit:vtv_end.o%s; \
diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h
index a55f6b2b874..2f773924d6e 100644
--- a/gcc/config/i386/darwin.h
+++ b/gcc/config/i386/darwin.h
@@ -109,8 +109,8 @@ along with GCC; see the file COPYING3.  If not see
 "%{!force_cpusubtype_ALL:-force_cpusubtype_ALL} "
 
 #undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+#define ENDFILE_SPEC
+\  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{mpc32:crtprec32.o%s} \
    %{mpc64:crtprec64.o%s} \
    %{mpc80:crtprec80.o%s}" TM_DESTRUCTOR
diff --git a/gcc/config/i386/gnu-user-common.h b/gcc/config/i386/gnu-user-common.h
index 23b54c5be52..3d2a33f1714 100644
--- a/gcc/config/i386/gnu-user-common.h
+++ b/gcc/config/i386/gnu-user-common.h
@@ -47,7 +47,7 @@ along with GCC; see the file COPYING3.  If not see
 
 /* Similar to standard GNU userspace, but adding -ffast-math support.  */
 #define GNU_USER_TARGET_MATHFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{mpc32:crtprec32.o%s} \
    %{mpc64:crtprec64.o%s} \
    %{mpc80:crtprec80.o%s}"
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index a3675e515bc..5cfb7cdcbc2 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -420,6 +420,10 @@ mpc80
 Target RejectNegative
 Set 80387 floating-point precision to 80-bit.
 
+mdaz-ftz
+Target
+Set the FTZ and DAZ Flags.
+
 mpreferred-stack-boundary=
 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
 Attempt to keep stack aligned to this power of 2.
diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h
index d3ca0cd0279..ddbe6a4054b 100644
--- a/gcc/config/i386/mingw32.h
+++ b/gcc/config/i386/mingw32.h
@@ -197,7 +197,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef ENDFILE_SPEC
 #define ENDFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{!shared:%:if-exists(default-manifest.o%s)}\
    %{fvtable-verify=none:%s; \
     fvtable-verify=preinit:vtv_end.o%s; \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index cb83dd8a1cc..87eedfffa6c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1434,7 +1434,7 @@ See RS/6000 and PowerPC Options.
 -m96bit-long-double  -mlong-double-64  -mlong-double-80  -mlong-double-128 @gol
 -mregparm=@var{num}  -msseregparm @gol
 -mveclibabi=@var{type}  -mvect8-ret-in-mem @gol
--mpc32  -mpc64  -mpc80  -mstackrealign @gol
+-mpc32  -mpc64  -mpc80 -mdaz-ftz -mstackrealign @gol
 -momit-leaf-frame-pointer  -mno-red-zone  -mno-tls-direct-seg-refs @gol
 -mcmodel=@var{code-model}  -mabi=@var{name}  -maddress-mode=@var{mode} @gol
 -m32  -m64  -mx32  -m16  -miamcu  -mlarge-data-threshold=@var{num} @gol
@@ -32078,6 +32078,15 @@ are enabled by default; routines in such libraries could suffer significant
 loss of accuracy, typically through so-called ``catastrophic cancellation'',
 when this option is used to set the precision to less than extended precision.
 
+@item -mdaz-ftz
+@opindex mdaz-ftz
+
+The flush-to-zero (FTZ) and denormals-are-zero (DAZ) flags in the MXCSR register
+are used to control floating-point calculations.SSE and AVX instructions
+including scalar and vector instructions could benefit from enabling the FTZ
+and DAZ flags when @option{-mdaz-ftz} is specified. Don't set FTZ/DAZ flags
+when @option{-mno-daz-ftz} is specified.
+
 @item -mstackrealign
 @opindex mstackrealign
 Realign the stack at entry.  On the x86, the @option{-mstackrealign}

commit 6abe9843bffb9262438ef9009f323c19f9d4c766
Author: Richard Biener <rguenther@suse.de>
Date:   Thu May 11 09:30:52 2023

    Fix gcc.dg/vect/pr108950.c
    
    The following puts the dg-require-effective-target properly after
    the dg-do.
    
            * gcc.dg/vect/pr108950.c: Re-order dg-require-effective-target
            and dg-do.
    
    (cherry picked from commit 66e268eb063de32b232f6f006048e6f7bae6268f)

diff --git a/gcc/testsuite/gcc.dg/vect/pr108950.c b/gcc/testsuite/gcc.dg/vect/pr108950.c
index ecf076c964b..563c4b9df38 100644
--- a/gcc/testsuite/gcc.dg/vect/pr108950.c
+++ b/gcc/testsuite/gcc.dg/vect/pr108950.c
@@ -1,5 +1,5 @@
-/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-do compile } */
+/* { dg-require-effective-target vect_simd_clones } */
 
 int m;
 short int n;

commit 9410a52061ffe4a9e6ef8fd82f9c21d1874ff589
Author: Richard Biener <rguenther@suse.de>
Date:   Thu May 11 09:13:31 2023

    testsuite/108776 - avoid c-c++-common/rotate-11.c FAIL
    
    On the branch ranger isn't powerful enough to handle some cases
    appearing with logical-op-non-short-circuit evaluating to false
    causing FAILs of the testcase for ppc64le and s390x.  The following
    foces logical-op-non-short-circuit to true for this testcase
    on the branch.
    
            PR testsuite/108776
            * c-c++-common/rotate-11.c: Add --param logical-op-non-short-circuit=1.

diff --git a/gcc/testsuite/c-c++-common/rotate-11.c b/gcc/testsuite/c-c++-common/rotate-11.c
index e57db19d949..85cde2786e2 100644
--- a/gcc/testsuite/c-c++-common/rotate-11.c
+++ b/gcc/testsuite/c-c++-common/rotate-11.c
@@ -1,6 +1,6 @@
 /* PR tree-optimization/108440 */
 /* { dg-do compile { target { { ilp32 || lp64 } || llp64 } } } */
-/* { dg-options "-O2 -fdump-tree-optimized" } */
+/* { dg-options "-O2 -fdump-tree-optimized --param logical-op-non-short-circuit=1" } */
 /* { dg-final { scan-tree-dump-times " r<< " 5 "optimized" } } */
 /* { dg-final { scan-tree-dump-times " \\\& 7;" 4 "optimized" } } */
 

commit 396a4e76afec30d2461638f569cae18955eb4ad2
Author: Jason Merrill <jason@redhat.com>
Date:   Wed Mar 22 21:11:47 2023

    c++: local class in nested generic lambda [PR109241]
    
    In this testcase, the tree walk to look for bare parameter packs was
    confused by finding a type with no TREE_BINFO.  But it should be fine that
    it's unset; we already checked for unexpanded packs at parse time.
    
    I also tried doing the partial instantiation of the local class, which is
    probably the long-term direction we want to go, but for stage 4 let's go
    with this safer change.
    
            PR c++/109241
    
    gcc/cp/ChangeLog:
    
            * pt.cc (find_parameter_packs_r): Handle null TREE_BINFO.
    
    gcc/testsuite/ChangeLog:
    
            * g++.dg/cpp1y/lambda-generic-local-class2.C: New test.

diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index c7f4a95a723..79bc9c014c8 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -4106,10 +4106,14 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, void* data)
     case TAG_DEFN:
       t = TREE_TYPE (t);
       if (CLASS_TYPE_P (t))
-	/* Local class, need to look through the whole definition.  */
-	for (tree bb : BINFO_BASE_BINFOS (TYPE_BINFO (t)))
-	  cp_walk_tree (&BINFO_TYPE (bb), &find_parameter_packs_r,
-			ppd, ppd->visited);
+	{
+	  /* Local class, need to look through the whole definition.
+	     TYPE_BINFO might be unset for a partial instantiation.  */
+	  if (TYPE_BINFO (t))
+	    for (tree bb : BINFO_BASE_BINFOS (TYPE_BINFO (t)))
+	      cp_walk_tree (&BINFO_TYPE (bb), &find_parameter_packs_r,
+			    ppd, ppd->visited);
+	}
       else
 	/* Enum, look at the values.  */
 	for (tree l = TYPE_VALUES (t); l; l = TREE_CHAIN (l))
diff --git a/gcc/testsuite/g++.dg/cpp1y/lambda-generic-local-class2.C b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-local-class2.C
new file mode 100644
index 00000000000..83856de1f41
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-local-class2.C
@@ -0,0 +1,13 @@
+// PR c++/109241
+// { dg-do compile { target c++14 } }
+// { dg-options "" } no pedantic
+
+void g() {
+  [](auto) {
+    [](auto) {
+      ({
+        struct A {};
+      });
+    };
+  }(1);
+}

commit b8789d2b222c50c5331b530a3359563d16208a5e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 16 02:21:27 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9a940060c41..3f096df5808 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2023-05-15  liuhongt  <hongtao.liu@intel.com>
+
+	* config/i386/cygwin.h (ENDFILE_SPEC): Link crtfastmath.o
+	whenever -mdaz-ftz is specified. Don't link crtfastmath.o
+	when -mno-daz-ftz is specified.
+	* config/i386/darwin.h (ENDFILE_SPEC): Ditto.
+	* config/i386/gnu-user-common.h
+	(GNU_USER_TARGET_MATHFILE_SPEC): Ditto.
+	* config/i386/mingw32.h (ENDFILE_SPEC): Ditto.
+	* config/i386/i386.opt (mdaz-ftz): New option.
+	* doc/invoke.texi (x86 options): Document mftz-daz.
+
 2023-05-09  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0bf2258d634..ae488c0e7fc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230515
+20230516
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 5b4ecfa4eb9..c0081902bfb 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,8 @@
+2023-05-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/109241
+	* pt.cc (find_parameter_packs_r): Handle null TREE_BINFO.
+
 2023-05-09  Patrick Palka  <ppalka@redhat.com>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 817770798b6..0d8a1bef47b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2023-05-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/109241
+	* g++.dg/cpp1y/lambda-generic-local-class2.C: New test.
+
+2023-05-15  Richard Biener  <rguenther@suse.de>
+
+	PR testsuite/108776
+	* c-c++-common/rotate-11.c: Add --param logical-op-non-short-circuit=1.
+
+2023-05-15  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-05-15  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/vect/pr108950.c: Re-order dg-require-effective-target
+	and dg-do.
+
 2023-05-10  Richard Biener  <rguenther@suse.de>
 
 	Backported from master:

commit e6baa800897728fac40fc7153facaf3c7541ff3f
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Mon Nov 28 14:28:53 2022

    libstdc++: Fix src/c++17/memory_resource for H8 targets [PR107801]
    
    This fixes compilation failures for H8 multilibs. For the normal
    multilib (ILP16L32?), the chunk struct does not have the expected size,
    because uint32_t is type long and has alignment 4 (by default). This
    forces sizeof(chunk) to be 12 instead of the expected 10. We can fix
    that by using bitset::size_type instead of uint32_t, so that we only use
    a 16-bit size when size_t and pointers are 16-bit types.
    
    For the IL32P16 multilibs that use -mint32, int is wider than size_t
    and so arithmetic expressions involving size_t promote to int. This
    means we need some explicit casts back to size_t.
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/107801
            * src/c++17/memory_resource.cc (chunk::_M_bytes): Change type
            from uint32_t to bitset::size_type. Adjust static assertion.
            (__pool_resource::_Pool::replenish): Cast to size_t after
            multiplication instead of before.
            (__pool_resource::_M_alloc_pools): Ensure both arguments to
            std::max have type size_t.
    
    (cherry picked from commit 75e562d2c4303d3918be9d1563284b0c580c5e45)

diff --git a/libstdc++-v3/src/c++17/memory_resource.cc b/libstdc++-v3/src/c++17/memory_resource.cc
index d6555aa8823..b7a1a716c42 100644
--- a/libstdc++-v3/src/c++17/memory_resource.cc
+++ b/libstdc++-v3/src/c++17/memory_resource.cc
@@ -506,7 +506,7 @@ namespace pmr
     }
 
     // Allocated size of chunk:
-    uint32_t _M_bytes = 0;
+    bitset::size_type _M_bytes = 0;
     // Start of allocated chunk:
     std::byte* _M_p = nullptr;
 
@@ -580,7 +580,7 @@ namespace pmr
   // For 16-bit pointers it's five pointers (10 bytes).
   // TODO pad 64-bit to 4*sizeof(void*) to avoid splitting across cache lines?
   static_assert(sizeof(chunk)
-      == sizeof(bitset::size_type) + sizeof(uint32_t) + 2 * sizeof(void*));
+      == 2 * sizeof(bitset::size_type) + 2 * sizeof(void*));
 
   // An oversized allocation that doesn't fit in a pool.
   struct big_block
@@ -735,7 +735,7 @@ namespace pmr
 	  _M_blocks_per_chunk = std::min({
 	      max_blocks,
 	      __opts.max_blocks_per_chunk,
-	      (size_t)_M_blocks_per_chunk * 2
+	      size_t(_M_blocks_per_chunk * 2)
 	  });
 	}
     }
@@ -1058,7 +1058,8 @@ namespace pmr
 	// Decide on initial number of blocks per chunk.
 	// At least 16 blocks per chunk seems reasonable,
 	// more for smaller blocks:
-	size_t blocks_per_chunk = std::max(size_t(16), 1024 / block_size);
+	size_t blocks_per_chunk = 1024 / block_size;
+	blocks_per_chunk = std::max(size_t(16), blocks_per_chunk);
 	// But don't exceed the requested max_blocks_per_chunk:
 	blocks_per_chunk
 	  = std::min(blocks_per_chunk, _M_opts.max_blocks_per_chunk);

commit 6187750aa83aef378fe214ed7d804e7d0df25ab1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 17 02:20:26 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ae488c0e7fc..e2f60e4d429 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230516
+20230517
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index c9fc4ec3fad..2d1423be22f 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,16 @@
+2023-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/107801
+	* src/c++17/memory_resource.cc (chunk::_M_bytes): Change type
+	from uint32_t to bitset::size_type. Adjust static assertion.
+	(__pool_resource::_Pool::replenish): Cast to size_t after
+	multiplication instead of before.
+	(__pool_resource::_M_alloc_pools): Ensure both arguments to
+	std::max have type size_t.
+
 2023-05-11  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 8618aed89650bbeec450191aecab3037124851b1
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed May 17 10:15:50 2023

    c++: Don't try to initialize zero width bitfields in zero initialization [PR109868]
    
    My GCC 12 change to avoid removing zero-sized bitfields as they are
    important for ABI and are needed for layout compatibility traits
    apparently causes zero sized bitfields to be initialized in the IL,
    which at least in 13+ results in ICEs in the ranger which is upset
    about zero precision types.
    
    I think we could even avoid initializing other unnamed bitfields, but
    unfortunately !CONSTRUCTOR_NO_CLEARING doesn't mean in the middle-end
    clearing of padding bits and until we have some new flag that represents
    the request to clear padding bits, I think it is better to keep zeroing
    non-zero sized unnamed bitfields.
    
    In addition to skipping those fields, I have changed the logic how
    UNION_TYPEs are handled, the current code was a little bit weird in that
    e.g. if first non-static data member had error_mark_node type, we'd happily
    zero initialize the second non-static data member, etc.
    
    2023-05-17  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/109868
            * init.cc (build_zero_init_1): Don't initialize zero-width bitfields.
            For unions only initialize the first FIELD_DECL.
    
            * g++.dg/init/pr109868.C: New test.
    
    (cherry picked from commit 78327cf06e6b65fc9c614622c98f6a3f3bfb7784)

diff --git a/gcc/cp/init.cc b/gcc/cp/init.cc
index 75dbfe112b5..36dcd70e152 100644
--- a/gcc/cp/init.cc
+++ b/gcc/cp/init.cc
@@ -189,15 +189,21 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p,
     init = build_zero_cst (type);
   else if (RECORD_OR_UNION_CODE_P (TREE_CODE (type)))
     {
-      tree field;
+      tree field, next;
       vec<constructor_elt, va_gc> *v = NULL;
 
       /* Iterate over the fields, building initializations.  */
-      for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
+      for (field = TYPE_FIELDS (type); field; field = next)
 	{
+	  next = DECL_CHAIN (field);
+
 	  if (TREE_CODE (field) != FIELD_DECL)
 	    continue;
 
+	  /* For unions, only the first field is initialized.  */
+	  if (TREE_CODE (type) == UNION_TYPE)
+	    next = NULL_TREE;
+
 	  if (TREE_TYPE (field) == error_mark_node)
 	    continue;
 
@@ -212,6 +218,11 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p,
 		continue;
 	    }
 
+	  /* Don't add zero width bitfields.  */
+	  if (DECL_C_BIT_FIELD (field)
+	      && integer_zerop (DECL_SIZE (field)))
+	    continue;
+
 	  /* Note that for class types there will be FIELD_DECLs
 	     corresponding to base classes as well.  Thus, iterating
 	     over TYPE_FIELDs will result in correct initialization of
@@ -230,10 +241,6 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p,
 	      if (value)
 		CONSTRUCTOR_APPEND_ELT(v, field, value);
 	    }
-
-	  /* For unions, only the first field is initialized.  */
-	  if (TREE_CODE (type) == UNION_TYPE)
-	    break;
 	}
 
       /* Build a constructor to contain the initializations.  */
diff --git a/gcc/testsuite/g++.dg/init/pr109868.C b/gcc/testsuite/g++.dg/init/pr109868.C
new file mode 100644
index 00000000000..0926f406e4f
--- /dev/null
+++ b/gcc/testsuite/g++.dg/init/pr109868.C
@@ -0,0 +1,13 @@
+// PR c++/109868
+// { dg-do compile }
+// { dg-options "-O2" }
+
+struct A { virtual void foo (); };
+struct B { long b; int : 0; };
+struct C : A { B c; };
+
+void
+bar (C *p)
+{
+  *p = C ();
+}

commit 4a9618035a4648d901b53c67f8f8bb5e5b624bc8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu May 18 02:19:59 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e2f60e4d429..460c1ea9af3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230517
+20230518
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index c0081902bfb..7c0497dc46f 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,12 @@
+2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/109868
+	* init.cc (build_zero_init_1): Don't initialize zero-width bitfields.
+	For unions only initialize the first FIELD_DECL.
+
 2023-05-15  Jason Merrill  <jason@redhat.com>
 
 	PR c++/109241
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0d8a1bef47b..7f65d308ec8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/109868
+	* g++.dg/init/pr109868.C: New test.
+
 2023-05-15  Jason Merrill  <jason@redhat.com>
 
 	PR c++/109241

commit 015848f7014e797ae8f3b044dcbec6186000cf90
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Thu Oct 6 15:43:51 2022

    arm: improve vcreateq* tests
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
    
    (cherry picked from commit 9a79b522e0663a202a288db56ebcbdcdb48bdaca)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
index fb3601edb94..c39303daa03 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 float16x8_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+float16x8_t
+foo1 ()
+{
+  return vcreateq_f16 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
index 4f4da62eed7..ad66f4407cd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 float32x4_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+float32x4_t
+foo1 ()
+{
+  return vcreateq_f32 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
index 103be6310bd..7e70a486513 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 int16x8_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int16x8_t
+foo1 ()
+{
+  return vcreateq_s16 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
index 96f7a972d93..ffcfc80ff40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 int32x4_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int32x4_t
+foo1 ()
+{
+  return vcreateq_s32 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
index 74c554506c0..26642f9cd68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 int64x2_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s64 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int64x2_t
+foo1 ()
+{
+  return vcreateq_s64 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
index 03c50a0928a..7e7e4d5948d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 int8x16_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int8x16_t
+foo1 ()
+{
+  return vcreateq_s8 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
index 411cec8471e..858a3a4546f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 uint16x8_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint16x8_t
+foo1 ()
+{
+  return vcreateq_u16 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
index 8bc8f60640e..5f27cf68845 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 uint32x4_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint32x4_t
+foo1 ()
+{
+  return vcreateq_u32 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
index e74641c32f3..78553dec701 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 uint64x2_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u64 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint64x2_t
+foo1 ()
+{
+  return vcreateq_u64 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
index de79f471d63..4a8ab61f865 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
@@ -1,13 +1,34 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
 uint8x16_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint8x16_t
+foo1 ()
+{
+  return vcreateq_u8 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 4aa7b4930279690ca482f4886ee6a2244ccba98d
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Tue Sep 13 19:02:47 2022

    arm: fix 'vmsr' spacing and register capitalization
    
    gcc/ChangeLog:
    
            * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix
            'vmsr' spacing and reg capitalization.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
            Update test.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c:
            Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c:
            Likewise.
    
    (cherry picked from commit b9496f8411d1058539d00f716c21397efa43022d)

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index d0f423cc3c5..932e4b7447e 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -105,9 +105,9 @@
     case 8:
       return "vmov%?.f32\t%0, %1\t%@ int";
     case 9:
-      return "vmsr%?\t P0, %1\t@ movhi";
+      return "vmsr%?\tp0, %1\t@ movhi";
     case 10:
-      return "vmrs%?\t %0, P0\t@ movhi";
+      return "vmrs%?\t%0, p0\t@ movhi";
     default:
       gcc_unreachable ();
     }
@@ -209,9 +209,9 @@
     case 8:
       return "vmov%?.f32\t%0, %1\t%@ int";
     case 9:
-      return "vmsr%?\t P0, %1\t%@ movhi";
+      return "vmsr%?\tp0, %1\t%@ movhi";
     case 10:
-      return "vmrs%?\t%0, P0\t%@ movhi";
+      return "vmrs%?\t%0, p0\t%@ movhi";
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
index f3219e2e825..1e57ca40739 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
@@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p)
 }
 
 /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
 /* { dg-final { scan-assembler "vpst" } } */
 /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
 /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
index 4d093d243fe..f8d77fdfd5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
@@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p)
 }
 
 /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
 /* { dg-final { scan-assembler "vpst" } } */
 /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
 /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
index e796522a49c..8a0e109c70c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
@@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p)
 }
 
 /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
 /* { dg-final { scan-assembler "vpst" } } */
 /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
 /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */

commit 96fcd2c47ab738adcca92dc868bc49ca76f957c7
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Thu Oct 6 16:36:28 2022

    arm: improve tests and fix vddupq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vddupq_u<mode>_insn): Fix 'vddup.u'
            spacing.
            (mve_vddupq_m_wb_u<mode>_insn): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c : Likewise.
    
    (cherry picked from commit f3f4295ad19f205862fe21ab49db090e7d295557)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 1d957dd2539..aaa16bfde8a 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -9038,7 +9038,7 @@
        (minus:SI (match_dup 2)
 		 (match_operand:SI 4 "immediate_operand" "i")))]
  "TARGET_HAVE_MVE"
- "vddup.u%#<V_sz_elem>  %q0, %1, %3")
+ "vddup.u%#<V_sz_elem>\t%q0, %1, %3")
 
 ;;
 ;; [vddupq_m_n_u])
@@ -9074,7 +9074,7 @@
        (minus:SI (match_dup 3)
 		 (match_operand:SI 6 "immediate_operand" "i")))]
  "TARGET_HAVE_MVE"
- "vpst\;\tvddupt.u%#<V_sz_elem>\t%q0, %2, %4"
+ "vpst\;vddupt.u%#<V_sz_elem>\t%q0, %2, %4"
  [(set_attr "length""8")])
 
 ;;
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
index 7332711f6a7..7c8b0152763 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vddupq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
index 54ad91f2803..810a1a7e21b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m_n_u32 (inactive, a, 4, p);
+  return vddupq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
index 3746b5db6e5..6642b9f4b88 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m_n_u8 (inactive, a, 4, p);
+  return vddupq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
index 8b5d9e86469..cc6a19516d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vddupq_m_wb_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
index 7a8c363ac70..cd6c6f86eea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m_wb_u32 (inactive, a, 4, p);
+  return vddupq_m_wb_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
index 45784a5c9cd..fe186e743da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m_wb_u8 (inactive, a, 4, p);
+  return vddupq_m_wb_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
index 4684e2af553..2dba2d74b61 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a)
 {
-  return vddupq_n_u16 (a, 4);
+  return vddupq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a)
 {
-  return vddupq_u16 (a, 4);
+  return vddupq_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vddupq_u16 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
index aeaa83eb6bc..6b5cf6c75b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a)
 {
   return vddupq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a)
 {
   return vddupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vddupq_u32 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
index 255a9f80b6b..174e422f4ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a)
 {
   return vddupq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a)
 {
   return vddupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vddupq_u8 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
index 40fc6cf2197..6a471a7f72f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t *a)
 {
-  return vddupq_wb_u16 (a, 4);
+  return vddupq_wb_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t *a)
 {
-  return vddupq_u16 (a, 4);
+  return vddupq_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vddupq_u16 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
index 09b5b1f2f80..debf420d3e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t *a)
 {
   return vddupq_wb_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t *a)
 {
   return vddupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vddupq_u32 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
index 00dfa906748..8e6ef8adccd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t *a)
 {
   return vddupq_wb_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t *a)
 {
   return vddupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vddupq_u8 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
index 5b0fc0b6340..1aafaf87b82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vddupq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
   return vddupq_x_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u16 (1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
index 66def991b65..2e3e268dbee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_n_u32 (a, 4, p);
+  return vddupq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_u32 (a, 4, p);
+  return vddupq_x_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u32 (1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
index 8ac322ed52d..bdf563a8074 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_n_u8 (a, 4, p);
+  return vddupq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_u8 (a, 4, p);
+  return vddupq_x_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u8 (1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
index 030048f840a..713d8b731c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
@@ -1,25 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
-
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_wb_u16 (a, 2, p);
+  return vddupq_x_wb_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint32_t *a, mve_pred16_t p)
+{
+  return vddupq_x_u16 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (mve_pred16_t p)
+foo2 (mve_pred16_t p)
 {
-  return vddupq_x_u16 (a, 2, p);
+  return vddupq_x_u16 (1, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
index 95bf28e4052..9f484b3b8fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
@@ -1,25 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
-
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_wb_u32 (a, 8, p);
+  return vddupq_x_wb_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32_t *a, mve_pred16_t p)
+{
+  return vddupq_x_u32 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (mve_pred16_t p)
+foo2 (mve_pred16_t p)
 {
-  return vddupq_x_u32 (a, 8, p);
+  return vddupq_x_u32 (1, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
index 2fe81dded55..aa83bfed125 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
@@ -1,25 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
-
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_wb_u8 (a, 8, p);
+  return vddupq_x_wb_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint32_t *a, mve_pred16_t p)
+{
+  return vddupq_x_u8 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (mve_pred16_t p)
+foo2 (mve_pred16_t p)
 {
-  return vddupq_x_u8 (a, 8, p);
+  return vddupq_x_u8 (1, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit a6cab55acb5f3ee201a294326c153dfdfbdccda1
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 10:19:38 2022

    arm: improve tests and fix vdwdupq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vdwdupq_m_wb_u<mode>_insn): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c : Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c : Likewise.
    
    (cherry picked from commit d5cc5a6d2e3726d2075bb2a9379c4da850947b6d)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index aaa16bfde8a..606d9d9f24e 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -9190,7 +9190,7 @@
 	 VDWDUPQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
+  "vpst\;vdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
index 5303fd7d361..8f53f5ef0cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 1, p);
+  return vdwdupq_m_n_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
index 9f22bd7f852..30e971fb733 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m_n_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
index 0591e731958..0abc19a2318 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m_n_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
index e4e7b47e082..b3e6affbf8f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 8, p);
+  return vdwdupq_m_wb_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 8, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
index 42917dc9886..60c52b0d850 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 1, p);
+  return vdwdupq_m_wb_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
index 32c3153ffb3..459321a7984 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 2, p);
+  return vdwdupq_m_wb_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 2, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
index 725a6e4bc0e..9f76dbf35eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b)
 {
-  return vdwdupq_n_u16 (a, b, 2);
+  return vdwdupq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return vdwdupq_u16 (a, b, 2);
+  return vdwdupq_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vdwdupq_u16 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
index 6ceaadb984d..962f766b496 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b)
 {
-  return vdwdupq_n_u32 (a, b, 8);
+  return vdwdupq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return vdwdupq_u32 (a, b, 8);
+  return vdwdupq_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vdwdupq_u32 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
index a1712e418be..c73b1b69661 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b)
 {
-  return vdwdupq_n_u8 (a, b, 4);
+  return vdwdupq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return vdwdupq_u8 (a, b, 4);
+  return vdwdupq_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vdwdupq_u8 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
index 0164ea9502c..3b1968d78aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_wb_u16 (a, b, 2);
+  return vdwdupq_wb_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_u16 (a, b, 2);
+  return vdwdupq_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vdwdupq_u16 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
index 7681371b016..8554f62ee6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_wb_u32 (a, b, 8);
+  return vdwdupq_wb_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_u32 (a, b, 8);
+  return vdwdupq_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vdwdupq_u32 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
index 6f60bb09b24..eb91a80daf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_wb_u8 (a, b, 4);
+  return vdwdupq_wb_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_u8 (a, b, 4);
+  return vdwdupq_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vdwdupq_u8 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
index ce975267531..9c0fd1e253c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u16 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
index 9ed75d292d8..3107e2fdbbe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_n_u32 (a, b, 4, p);
+  return vdwdupq_x_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u32 (a, b, 4, p);
+  return vdwdupq_x_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u32 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
index 3705094c4df..03d01e0dd43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_n_u8 (a, b, 4, p);
+  return vdwdupq_x_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u8 (a, b, 4, p);
+  return vdwdupq_x_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u8 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
index caf744d7255..f7dca660c03 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_wb_u16 (a, b, 8, p);
+  return vdwdupq_x_wb_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u16 (a, b, 8, p);
+  return vdwdupq_x_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u16 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
index 8c8be86bce6..032ae94e8c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_wb_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u32 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
index 1c6ef4ed33f..5d238a7a865 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_wb_u8 (a, b, 2, p);
+  return vdwdupq_x_wb_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u8 (a, b, 2, p);
+  return vdwdupq_x_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u8 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit f2477c0eabbb0b304dd5492805db7996579e00e3
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 10:23:39 2022

    arm: improve vidupq* tests
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Improve tests.
            * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
    
    (cherry picked from commit e9fe7b23b82942faffcdf4803eda4ade7b708a8a)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
index 822d41197e6..b4ee7af36e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vidupq_m_n_u16 (inactive, a, 4, p);
+  return vidupq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vidupq_m (inactive, a, 4, p);
+  return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
index c01826e15dc..b13a7a80dcb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
index e269665813c..b731002724a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
index 8d21bc7db80..0e2ad6a2b55 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_m_wb_u16 (inactive, a, 4, p);
+  return vidupq_m_wb_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_m (inactive, a, 4, p);
+  return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
index e7bc06cd826..786a05eee35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m_wb_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
index a8a2f9a1c49..3fcc3ba0d67 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m_wb_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
index c59ca1ebf74..a6ffdc05ce5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a)
 {
-  return vidupq_n_u16 (a, 4);
+  return vidupq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a)
 {
-  return vidupq_u16 (a, 4);
+  return vidupq_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vidupq_u16 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
index 7e835e0868c..8cd43e38255 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a)
 {
   return vidupq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a)
 {
   return vidupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vidupq_u32 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
index 06d1a1a1480..4005eabb45d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a)
 {
   return vidupq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a)
 {
   return vidupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vidupq_u8 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
index 1cb0ded198f..3ad89c0536c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t *a)
 {
-  return vidupq_wb_u16 (a, 4);
+  return vidupq_wb_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t *a)
 {
-  return vidupq_u16 (a, 4);
+  return vidupq_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vidupq_u16 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
index e5d9c5327fb..45eb1b09a5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t *a)
 {
   return vidupq_wb_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t *a)
 {
   return vidupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vidupq_u32 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
index 57e1bb46776..beb0aae67a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t *a)
 {
   return vidupq_wb_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t *a)
 {
   return vidupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vidupq_u8 (1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
index bdf8ec2b047..74cd4310213 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, mve_pred16_t p)
 {
-  return vidupq_x_n_u16 (a, 4, p);
+  return vidupq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
-  return vidupq_x_u16 (a, 4, p);
+  return vidupq_x_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u16 (1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
index 8be549cb446..3111b1a54e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u32 (1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
index 1e1975017de..5bedb4f9e79 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u8 (1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
index 31197a76cfa..caf334fa32f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
@@ -1,25 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
-
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_wb_u16 (a, 8, p);
+  return vidupq_x_wb_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint32_t *a, mve_pred16_t p)
+{
+  return vidupq_x_u16 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (mve_pred16_t p)
+foo2 (mve_pred16_t p)
 {
-  return vidupq_x_u16 (a, 8, p);
+  return vidupq_x_u16 (1, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
index cef56f133e8..11895e303cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
@@ -1,25 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
-
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_wb_u32 (a, 2, p);
+  return vidupq_x_wb_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32_t *a, mve_pred16_t p)
+{
+  return vidupq_x_u32 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (mve_pred16_t p)
+foo2 (mve_pred16_t p)
 {
-  return vidupq_x_u32 (a, 2, p);
+  return vidupq_x_u32 (1, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
index 0403ba1174c..b951d4cfe94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
@@ -1,25 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t * a;
-
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_wb_u8 (a, 2, p);
+  return vidupq_x_wb_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint32_t *a, mve_pred16_t p)
+{
+  return vidupq_x_u8 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (mve_pred16_t p)
+foo2 (mve_pred16_t p)
 {
-  return vidupq_x_u8 (a, 2, p);
+  return vidupq_x_u8 (1, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 18c231714fd66ddafba0b4780f13d0c48104d3a1
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 11:45:13 2022

    arm: improve tests and fix vdupq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vdupq_n_f<mode>)
            (mve_vdupq_n_<supf><mode>, mve_vdupq_m_n_<supf><mode>)
            (mve_vdupq_m_n_f<mode>): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
    
    (cherry picked from commit 7827909fb2ffa3517ada8fae6e41873fb1cbe47a)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 606d9d9f24e..86e4eb2798e 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -259,7 +259,7 @@
 	 VDUPQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vdup.%#<V_sz_elem>   %q0, %1"
+  "vdup.%#<V_sz_elem>\t%q0, %1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -428,7 +428,7 @@
 	 VDUPQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vdup.%#<V_sz_elem>   %q0, %1"
+  "vdup.%#<V_sz_elem>\t%q0, %1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -3041,7 +3041,7 @@
 	 VDUPQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vdupt.%#<V_sz_elem>	%q0, %2"
+  "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3986,7 +3986,7 @@
 	 VDUPQ_M_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vdupt.%#<V_sz_elem>	%q0, %2"
+  "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
index 0b749be3527..bfa471bcb31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16_t a, mve_pred16_t p)
 {
   return vdupq_m_n_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
index 9cca5310c7a..e1dd8f58ad0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32_t a, mve_pred16_t p)
 {
   return vdupq_m_n_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
index b521f13e94f..52304ace03a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16_t a, mve_pred16_t p)
 {
   return vdupq_m_n_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
index 96aa195dc18..44a80c5d5bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32_t a, mve_pred16_t p)
 {
   return vdupq_m_n_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
index f1d222000c1..1630a3b9234 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8_t a, mve_pred16_t p)
 {
   return vdupq_m_n_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
index 39d0c9f502d..d3df8b69248 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16_t a, mve_pred16_t p)
 {
   return vdupq_m_n_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
index fc107172e16..e6bb0cc2c38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vdupq_m_n_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
index 9fd3bc443cb..ad6f6d04ae3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8_t a, mve_pred16_t p)
 {
   return vdupq_m_n_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
index 62bfc194533..fc5a7933653 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16_t a)
 {
   return vdupq_n_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.16"  }  } */
+/*
+**foo1:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 ()
+{
+  return vdupq_n_f16 (1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
index f5ad2286d8d..a6be82e5927 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32_t a)
 {
   return vdupq_n_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.32"  }  } */
+/*
+**foo1:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 ()
+{
+  return vdupq_n_f32 (1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
index 1378522a18e..f842b96c3b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
@@ -1,13 +1,20 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16_t a)
 {
   return vdupq_n_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
index 43affe856c0..05cbff8fdae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
@@ -1,13 +1,20 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32_t a)
 {
   return vdupq_n_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
index 3f934dc5d59..1d141161604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
@@ -1,13 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8_t a)
 {
   return vdupq_n_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
index 93268643fec..4839d427e65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16_t a)
 {
-    return vdupq_n_u16 (a);
+  return vdupq_n_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.16"  }  } */
+/*
+**foo1:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 ()
+{
+  return vdupq_n_u16 (1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
index 276e9ddc67f..f0069eb7280 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a)
 {
-    return vdupq_n_u32 (a);
+  return vdupq_n_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.32"  }  } */
+/*
+**foo1:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 ()
+{
+  return vdupq_n_u32 (1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
index d0361c15047..fe26687ae45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vdup.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8_t a)
 {
-    return vdupq_n_u8 (a);
+  return vdupq_n_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.8"  }  } */
+/*
+**foo1:
+**	...
+**	vdup.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 ()
+{
+  return vdupq_n_u8 (1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
index c91ee62791c..11ebb47f94f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
@@ -1,14 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16_t a, mve_pred16_t p)
 {
   return vdupq_x_n_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_f16 (1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
index c2b39051f5b..4e79bd54f71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
@@ -1,14 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32_t a, mve_pred16_t p)
 {
   return vdupq_x_n_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_f32 (1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
index cc8a5bfeca1..90288777df7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
@@ -1,14 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16_t a, mve_pred16_t p)
 {
   return vdupq_x_n_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
index b3ed3eb68e8..c4c906e0682 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
@@ -1,14 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32_t a, mve_pred16_t p)
 {
   return vdupq_x_n_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
index 3be865dcc84..6234730827e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
@@ -1,14 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8_t a, mve_pred16_t p)
 {
   return vdupq_x_n_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
index d01338aeb91..821fcddcab1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
@@ -1,14 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16_t a, mve_pred16_t p)
 {
   return vdupq_x_n_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_u16 (1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
index 8fa7d4552bc..20125df6226 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
@@ -1,14 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vdupq_x_n_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_u32 (1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
index 96ad899c9c2..defaaeebfcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
@@ -1,14 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8_t a, mve_pred16_t p)
 {
   return vdupq_x_n_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_u8 (1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 351cc920d8a75748f082340eb4291914a1f56afc
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 11:59:58 2022

    arm: improve tests and fix vcmp*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>): Fix
            spacing.
            * config/arm/arm_mve.h (__arm_vcmpgtq_m, __arm_vcmpleq_m)
            (__arm_vcmpltq_m, __arm_vcmpneq_m): Add missing defines.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
    
    (cherry picked from commit 1fa5a44736062eeccd241ebeb1771bd77b7fd168)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 073e3711623..684f997520f 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -39229,6 +39229,53 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
 
+
+#define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+
+#define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+
+#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+
+#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));})
+
 #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 86e4eb2798e..b91d06faaeb 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -824,7 +824,7 @@
 		    (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vcmp.<mve_cmp_type>%#<V_sz_elem>  <mve_cmp_op>, %q1, %q2"
+  "vcmp.<mve_cmp_type>%#<V_sz_elem>\t<mve_cmp_op>, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
index a1640133012..de9fe5e7d01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmpcsq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
index d269ec7e3ab..04df1b2dc61 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmpcsq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
index 52c16b3e70f..34ebadca248 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmpcsq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
index e68afa316a9..bc03bf687de 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
index 05d1b21b279..8e216d49a02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
index 4c8a9d0aa2c..ac4196a2e48 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
index 4124036003e..6038f4c8c65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmpcsq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmpcsq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
index 463c1ee12b4..9f39aa761c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmpcsq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmpcsq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
index 92bc44a4bb6..0ce2cd13a7b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmpcsq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmpcsq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
index 26c7d750cef..5598d06875c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmpcsq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
index c91b0e1c2e3..99b232b05dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmpcsq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
index 51ddab91500..571e57135ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmpcsq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
index 556351f4984..57b276a1d4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpeqq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
index 65b2f240520..ab1b25e2888 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpeqq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
index 91b0ffa0afd..c5587884d0e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
index d66e9c8be34..4e9675fff51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
index 46b3f4499d3..a3cae828e79 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
index 7d672c129db..a7ce9e0c7e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
index 912d4ad893d..7ba481e169f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
index 947c331622d..13c88eaabb5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
index e215d655ea2..dcf276dee44 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
index ea4716c450e..d59d5149a30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
index 489c6ec0cb3..1fbf385d030 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
index e8dfce432d1..92758c98c9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
index 7e4c141e5d2..1ea35ed924b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
index 904cfb6fe37..a9bc9733842 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
index a7e12164e32..a9fe771a101 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
index 283e1fd036e..826901874d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
index ad1739bd609..512b7f9c889 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
index 595142e9cda..01b4507ba63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
index f97209d2322..cf2812558ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpeqq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpeqq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
index c80843288b2..13817174282 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpeqq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpeqq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
index 69f1f531af4..bd29828492e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpeqq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
index 06032dbcc20..2a0d84e9b51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpeqq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
index 3ebd88be85b..524bbe9f3cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpeqq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
index 2f6c53a525e..3eeaa49aa97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmpeqq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmpeqq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
index 22fb5be97c5..a881bb841af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmpeqq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmpeqq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
index 79eaeed6950..429b2e35eb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmpeqq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmpeqq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
index 7951ead8a31..92a87c08773 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpeqq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
index 659ccb4ac14..d3b87d59bfa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpeqq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
index 9282ec2a97a..2b71bbf75f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpeqq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
index 318b7aa9306..1830b667bb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmpeqq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
index 88e015f1fa3..2b2a5f920f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmpeqq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
index 990a96f7b3f..9450c203394 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmpeqq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
index eea63a2fe50..fd8bcab4f25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpgeq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
index 64243fe3e8c..a2d50b580e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpgeq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
index 3588b0a536f..a631825fadd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
index 8ed1d22e919..b94e0738ef0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
index d106af8f53b..9f4903d9cfd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
index 1feef8adb7f..679e644f165 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
index c0ad38f6c6f..45e26d0a77b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
index 8974ce4d11a..3a6cad921f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
index 981aa1b516c..ce1ca30d6ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
index 587432a6af1..51587a38b72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
index e460a8dcafc..3ff0aaaa414 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
index cde28a314b9..df71ee57945 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
index 907fa5d50f6..2ca1b9d6684 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpgeq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpgeq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
index e4d1406c049..3af110bd2b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpgeq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpgeq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
index f4aad09e783..3c1af8a93ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpgeq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
index 2baa5204819..8b4e0f426e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpgeq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
index 1dcffcc3050..c1669bcdd90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpgeq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
index 817ffb2d8ac..593c7410dcb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpgeq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
index d608b7fc9cf..9e26ea9938a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpgeq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
index 506e6cede95..3cb2832e159 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpgeq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
index e2bfd7ed156..8835fe08dba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpgtq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
index 1b4433f0e76..e1470884708 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpgtq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
index def3f90a79d..cb9d5f4036f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
index 41a11563f36..b249b831782 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
index 80c86f65825..b375983f01e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpgtq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
index 9b7aaadfe71..208a285cb39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpgtq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
index c0719d0110c..248e3093d2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
index 26df8cea9fc..9843288296e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
index f20c50d69c1..80f1aa9ead0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
index da97abceb2e..9289c00b5af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
index ab7c218c7af..8a3d7606bb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
index 13520d1067b..2760795eb86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
index 98e152cd999..9f2a4be319a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpgtq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpgtq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
index 5691e2f9d35..bbf18ebe6e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpgtq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpgtq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
index bc3bdbae2da..d833cb6f58e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpgtq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
index 409a3f9d808..28cd51b9582 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpgtq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
index 2624307be9d..5a953ca55f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpgtq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
index be19e19f09f..b9c9da486f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpgtq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
index 95f6c703b9d..0f79385358e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpgtq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
index 8ba180d8e39..f59dad94a57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpgtq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
index 26e5fe3f900..136a2e44259 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmphiq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmphiq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
index 51396b8d0cd..5640b97afaf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmphiq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmphiq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
index 475f2e82345..e6474e45487 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmphiq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmphiq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
index 98ba895fde0..38b9b90c803 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmphiq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
index ee561b02d0c..97c8c1dfe05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmphiq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
index 0c5b29e2673..e2024ccda25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmphiq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
index d39b755441d..36107fc7b8d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmphiq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmphiq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
index dbedea9b078..d34de8f65c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmphiq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmphiq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
index 967bb206886..93a05b1a857 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmphiq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmphiq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
index f9399498a99..40e65dc52f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmphiq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
index becdef0696a..d87a4185762 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmphiq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
index 933cc69507d..80fd2a40b0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmphiq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
index c2e69a5de92..209d81096af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpleq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
index 923aee050d3..b92c5f66fd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpleq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
index 66a37192985..e6136898ded 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
index e679b338d58..2304e98d253 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
index 42049fd57a4..a61db2817c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpleq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
index c68bd4e5900..7a2cdb4059d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpleq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
index 0cdc14455a3..69fcab15b8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
index a955af8fa2b..617ebd6144f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
index d9951e4a8cf..b8ee50dd55c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
index f16aff86ef0..fcc376d6ec3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
index 2c4e659e9cf..9983e89d80c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
index 69b88cfb389..504e4feb5d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpleq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
index 3fa3c5e0310..cfa6dbc07c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpleq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpleq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
index 8349de7b68c..c89558f4076 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpleq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpleq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
index 5ecae572227..da73fc14b77 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpleq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
index 02320e7a552..0951a5c13fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpleq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
index a0ac97328b7..e4553354681 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpleq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
index 2fb4acd3d74..68500da9ddf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpleq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
index 2ae998efb7c..1966bcd94d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpleq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
index da06b019cc1..e9f6e47e5d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpleq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
index eab80b2ddd9..b4958816bd8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpltq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
index f17d16482dd..752ab2b3e49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpltq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
index 93c36f3a613..cbaacbe2b47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
index a17f0b02a95..96d0e7c7cc6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
index 45d0f51b4d7..1e5db53198e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpltq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
index 16e37ccaf8d..77de40ade01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpltq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
index d0e322fbede..beebe65a58f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
index 7ec7963267a..07260c56ed3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
index 22434e88cd6..7d1e9e7fbde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
index 359c0640784..c0f6dfc9432 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
index 3df7e89a6f5..b6fc4700e73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
index 1055c2b661c..545b76359ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpltq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
index 2d55af20dd3..401ef21ba2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpltq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpltq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
index 2590ca83c45..380f071e564 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpltq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpltq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
index 169f6ad4610..a1d12392dd2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpltq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
index 534047c2df3..6332f75f327 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpltq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
index da659f1f2be..e0ac80caeb0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpltq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
index da4c90a07de..23843ad88f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpltq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
index 5dc218a5f40..aeb7a6f9896 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpltq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
index ea5853c212c..2129b56a5f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpltq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
index 8d1c6096c56..c27ea2f0de8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpneq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
index 860bd69c129..609de44d8e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpneq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
index a4e62de7272..98f22337d61 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
index b18a2e5fd88..7f6e96ae47e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
index c127b3a68f6..71b3476fb18 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
index a8423d45708..d6dea8db865 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
index 63ee1c3bffb..e72c9b62829 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
index 10f6d448d76..47c90e31f49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
index 66e5d158c51..9d9da100046 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
index ffe6ff919cf..ea8cf24b358 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
index 55e796a1138..30291dcdd9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
index 3c8bd16647a..be75376a691 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
@@ -1,22 +1,63 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
index d3e1ce0e690..60e868141d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
index f5602ffd0da..780c544bef3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
index 84b8b1617b0..15f6d316cba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
index 3c8943719bb..300852ed7b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
index 980cc4124b2..227b5f01eca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
index 2615dcb37b9..cfcb59f49cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
index e9e2a9c7b04..29e43f3fdf8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpneq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpneq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
index eb64b17969c..688e77cd044 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpneq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpneq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
index 14689242ee4..2afc34d16e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpneq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
index 53418ff3923..6c323161316 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpneq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
index fa405c281b4..5483d6dd2fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpneq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
index cc8540b3a6c..d8edfb0d825 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmpneq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmpneq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
index 07c9b1ade96..2b7a6b56830 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmpneq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmpneq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
index eac5e96384e..2dab43af331 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
@@ -1,21 +1,51 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmpneq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmpneq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
index 6b04ce70ffc..d57b607baa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpneq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
index cfb98d7e650..e02171f6686 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpneq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
index ae69be4ba0b..0abef8c3e00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpneq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
index 51059f21191..7144f3ee2fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmpneq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
index 42e4a3f4f2d..a31134f2f1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmpneq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
index addacc15833..2801c8e3763 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
@@ -1,21 +1,37 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmpneq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 65f3196a223dbd731ddb887a79681f57228375da
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 16:21:40 2022

    arm: improve tests for vmin*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
    
    (cherry picked from commit d117647edc8fcae63abbdecbf38e9f22d0b1e3de)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
index 0324110c6a8..925b9154ca7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminaq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
index a2886d4f40f..296f69dfcda 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminaq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
index 95eb038efc0..cf6fecc3461 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminaq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
index 3a157e00a27..63f59f8c80a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmina.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vminaq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmina.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vminaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
index 5c732c65d63..eb0a54cbe19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmina.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vminaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmina.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vminaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
index 2e4dad141ce..b875308863d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmina.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vminaq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmina.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vminaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
index 9303ae02e39..5d3c40fb1fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminavq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b, mve_pred16_t p)
 {
-  return vminavq_p (a, b, p);
+  return vminavq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminavt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
index 36247f68b2c..ee4ff251d63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminavq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, mve_pred16_t p)
 {
-  return vminavq_p (a, b, p);
+  return vminavq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminavt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
index d3361615dcc..14602c29719 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminavq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b, mve_pred16_t p)
 {
-  return vminavq_p (a, b, p);
+  return vminavq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminavt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
index 17e4edca2f1..51f75ae1f6a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (uint16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b)
 {
   return vminavq (a, b);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b)
+/*
+**foo2:
+**	...
+**	vminav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b)
 {
-  return vminavq (a, b);
+  return vminavq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminav.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
index 032d02b8857..d1602cebe18 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b)
 {
@@ -11,18 +18,28 @@ foo (uint32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b)
 {
   return vminavq (a, b);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b)
+/*
+**foo2:
+**	...
+**	vminav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b)
 {
-  return vminavq (a, b);
+  return vminavq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminav.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
index 2a2bb3d6146..f4c9b045b90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b)
 {
@@ -11,18 +18,28 @@ foo (uint8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b)
 {
   return vminavq (a, b);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b)
+/*
+**foo2:
+**	...
+**	vminav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b)
 {
-  return vminavq (a, b);
+  return vminavq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminav.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
index cf32186d642..1728d104266 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vminnmaq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vminnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
index 1c3f19c9e1b..42b4265d9cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vminnmaq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vminnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
index 4423903e913..51b85bd2b04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmaq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
index 683f40ad3d8..2f0423ecb4f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmaq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
index fadb23e05c8..17e4ad16759 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vminnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vminnmavq (a, b);
+  return vminnmavq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmav.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
index 84714a96b9f..2758e59666e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vminnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vminnmavq (a, b);
+  return vminnmavq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmav.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
index c79fa307ae0..b60a6627aea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vminnmavq_p (a, b, p);
+  return vminnmavq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmavt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
index bea04c7aac6..6fa97b74a65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vminnmavq_p (a, b, p);
+  return vminnmavq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmavt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
index 18d4a4c1330..c0962b52631 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vminnmq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vminnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
index 34144cad17f..a9c3e5f74b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vminnmq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vminnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
index e5533d28035..466264249c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
index 382d16c4489..57edc8e1a80 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
index 04d606ce5cd..73b4ccba080 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
index 87cd970fd11..9a824566212 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
index 0eb3a4af14e..dc00d02df7d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vminnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vminnmvq (a, b);
+  return vminnmvq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmv.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
index f3183508f8e..ff23c818452 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vminnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vminnmvq (a, b);
+  return vminnmvq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmv.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
index 16f6ac514c8..ad99f586d11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vminnmvq_p (a, b, p);
+  return vminnmvq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmvt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
index a8e4f9ffba7..3c7e5c07a68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vminnmvq_p (a, b, p);
+  return vminnmvq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmvt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
index f257ddcf600..fe7368eeb38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
index 957da71d0e3..a90a1db8835 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
index fea8bfd7994..911bd3af0dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
index 7cc19a7dd5d..f80288aaf79 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
index 301fbfc751f..b480089f4f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
index 7a65b3557a3..73633c9612e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
index d46a3c4ee18..eb34dc4c41c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmin.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vminq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
index 601e918a5bf..60d29da4e14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmin.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vminq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
index e2ae2341ad8..675fb8edfb1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmin.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vminq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
index 3cac573f6ef..50f648d5133 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmin.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vminq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
index ca3ef245fe9..bcfead39c5a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmin.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vminq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
index b7ef4db22ff..e8eacae4da8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmin.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vminq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
index af93c78658e..0d8987e16b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
index 76f0831e48e..3c3595171ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
index fdd6e94497c..402c4aa121d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
index 9842954c761..e27a3416e38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
index 741e4508879..d3cb29bf60c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
index 13743fc87a1..3e05ef7dd13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
index 91bb63f6ba6..7c25c9d2f82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (int8_t a, int16x8_t b, mve_pred16_t p)
-{
-  return vminvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
index a846701312c..d5f7418af38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (int16_t a, int32x4_t b, mve_pred16_t p)
-{
-  return vminvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
index 716d414f3a7..6a42170fc19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (int32_t a, int8x16_t b, mve_pred16_t p)
-{
-  return vminvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
index cc7f8fe8933..8f2f68fef84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
-foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p)
+foo2 (uint16x8_t b, mve_pred16_t p)
 {
-  return vminvq_p (a, b, p);
+  return vminvq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
index 6bde0be29cc..9d14c39c1dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p)
+foo2 (uint32x4_t b, mve_pred16_t p)
 {
-  return vminvq_p (a, b, p);
+  return vminvq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
index bb894904f3c..4c1f4406852 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
-foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p)
+foo2 (uint8x16_t b, mve_pred16_t p)
 {
-  return vminvq_p (a, b, p);
+  return vminvq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
index 6d589aa4a05..e3242c0aa4d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b)
 {
@@ -11,17 +18,16 @@ foo (int16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b)
 {
   return vminvq (a, b);
 }
 
-int16_t
-foo2 (int8_t a, int16x8_t b)
-{
-  return vminvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
index 7c727d6d92b..1325b38411d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b)
 {
@@ -11,17 +18,16 @@ foo (int32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b)
 {
   return vminvq (a, b);
 }
 
-int32_t
-foo2 (int8_t a, int32x4_t b)
-{
-  return vminvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
index 76309482fc5..81c14a8ac6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b)
 {
@@ -11,17 +18,16 @@ foo (int8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b)
 {
   return vminvq (a, b);
 }
 
-int8_t
-foo2 (int32_t a, int8x16_t b)
-{
-  return vminvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
index 698975f456c..4372ac62388 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (uint16_t a, uint16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b)
 {
   return vminvq (a, b);
 }
 
-
-uint8_t
-foo2 (uint32_t a, uint16x8_t b)
+/*
+**foo2:
+**	...
+**	vminv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (uint16x8_t b)
 {
-  return vminvq (a, b);
+  return vminvq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
index 7489f81debf..aff3679f49d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b)
 {
@@ -11,17 +18,28 @@ foo (uint32_t a, uint32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b)
 {
   return vminvq (a, b);
 }
 
+/*
+**foo2:
+**	...
+**	vminv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint16_t a, uint32x4_t b)
+foo2 (uint32x4_t b)
 {
-  return vminvq (a, b);
+  return vminvq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
index aa2b986d558..883e5f2d2c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vminv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b)
 {
@@ -11,18 +18,28 @@ foo (uint8_t a, uint8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b)
 {
   return vminvq (a, b);
 }
 
-
-uint16_t
-foo2 (uint32_t a, uint8x16_t b)
+/*
+**foo2:
+**	...
+**	vminv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (uint8x16_t b)
 {
-  return vminvq (a, b);
+  return vminvq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 0aad406016e84bd34f878be4d91230c0597dbf7a
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 16:23:21 2022

    arm: improve tests for vmax*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
    
    (cherry picked from commit 2c5bb2513f2cfaf0c28aa933fb68dc09a4b01862)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
index 48d213277df..4c487ed7f60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxaq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
index 49273819861..5156467f0c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxaq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
index 5ecdb2c19dc..6564bd88c9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxaq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
index f9a9f896aa2..6cabf9f723b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxa.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vmaxaq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxa.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vmaxaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
index efe2fc16ff7..d0dd3c23600 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxa.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vmaxaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxa.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vmaxaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
index 5c2e35f71a6..a7344638dcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxa.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vmaxaq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxa.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vmaxaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
index 74ffad4e726..ac81c8fd1bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxavq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b, mve_pred16_t p)
 {
-  return vmaxavq_p (a, b, p);
+  return vmaxavq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxavt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
index 40800b0f12e..119c0c34c76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxavq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, mve_pred16_t p)
 {
-  return vmaxavq_p (a, b, p);
+  return vmaxavq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxavt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
index 7638737fb84..dfd7f828ef6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxavq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b, mve_pred16_t p)
 {
-  return vmaxavq_p (a, b, p);
+  return vmaxavq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxavt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
index 0dca149b3e8..9f59e8e4542 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (uint16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b)
 {
   return vmaxavq (a, b);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b)
+/*
+**foo2:
+**	...
+**	vmaxav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b)
 {
-  return vmaxavq (a, b);
+  return vmaxavq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxav.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
index f419a771017..716b8a2a979 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b)
 {
@@ -11,18 +18,28 @@ foo (uint32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b)
 {
   return vmaxavq (a, b);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b)
+/*
+**foo2:
+**	...
+**	vmaxav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b)
 {
-  return vmaxavq (a, b);
+  return vmaxavq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxav.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
index 214ad88f4aa..0f1a87af54b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b)
 {
@@ -11,18 +18,28 @@ foo (uint8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b)
 {
   return vmaxavq (a, b);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b)
+/*
+**foo2:
+**	...
+**	vmaxav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b)
 {
-  return vmaxavq (a, b);
+  return vmaxavq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxav.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
index f19707125db..cd4c813bf3b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vmaxnmaq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vmaxnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
index 94fc3a2aa28..527466fc131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vmaxnmaq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vmaxnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
index b2e82f5464c..39c68cdc172 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
index 8fa7344b054..f6f8bf07549 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
index 6d8cf19a341..4c1f20be036 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vmaxnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vmaxnmavq (a, b);
+  return vmaxnmavq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmav.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
index ef79030d8eb..86087335cea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vmaxnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vmaxnmavq (a, b);
+  return vmaxnmavq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmav.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
index f7f39f59dad..a4973567d5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vmaxnmavq_p (a, b, p);
+  return vmaxnmavq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmavt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
index 341f6254a5a..b229cb3a322 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vmaxnmavq_p (a, b, p);
+  return vmaxnmavq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmavt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
index 59a8070e07b..faf968ebb21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vmaxnmq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vmaxnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
index 5db42bd4b8c..f7ee01b1f14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vmaxnmq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vmaxnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
index 4668fd03c9d..ee3444393ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
index 9e8ccbc84b7..5d434432856 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
index ecca6069d22..dad76734fd8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
index c3965dda4f1..2fe8c0d4f3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
index 80bd1d4cda1..9787cc1ba90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vmaxnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vmaxnmvq (a, b);
+  return vmaxnmvq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmv.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
index bb2fc46f88a..b1191876850 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vmaxnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vmaxnmvq (a, b);
+  return vmaxnmvq (1.1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmv.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
index 3efe203007b..0b1740d5ed2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vmaxnmvq_p (a, b, p);
+  return vmaxnmvq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmvt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
index 6c13247f1f1..ca6ad91d24d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vmaxnmvq_p (a, b, p);
+  return vmaxnmvq_p (1.1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmvt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
index 2791ed4c562..548824fc58a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
index 27f7d5d7b16..e935729b47d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
index 23b7569f720..8028fa031c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
index 61e51e3b830..e872f9e72f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
index 23df7eeaed6..76606555881 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
index 138d5c87894..7ade467cafd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
index a42fc82a852..bf547a2420d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmax.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmaxq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
index 14c094a5d11..25bb950c0bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmax.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmaxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
index 0540a27bae9..33057f1a58e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmax.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmaxq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
index 6b9b5a73bcd..7717a9a5057 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmax.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmaxq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
index 3112302bf1a..36b5c276cfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmax.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmaxq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
index b1baa5083bd..e643e5f3e3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmax.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmaxq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
index 9d92f2ccd85..a32feb0d7cd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
index 200fd4b1bb1..3ac1994c4f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
index 2fe752558b9..c9ba33d1504 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
index 967622e331c..954a9e2f02a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
index 56b5d8fa8b8..022d418af84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
index 1816f959dd7..7e1687a8b72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
index 657efc51bea..a97703eb58c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (int8_t a, int16x8_t b, mve_pred16_t p)
-{
-  return vmaxvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
index 5882351c0fa..b4bddcb8312 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (int16_t a, int32x4_t b, mve_pred16_t p)
-{
-  return vmaxvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
index 3737ecd3307..ee8c3e9155f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (int32_t a, int8x16_t b, mve_pred16_t p)
-{
-  return vmaxvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
index 348cf39caa0..906adf85936 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
-foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p)
+foo2 (uint16x8_t b, mve_pred16_t p)
 {
-  return vmaxvq_p (a, b, p);
+  return vmaxvq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
index f2e976216c5..acc5367c5a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p)
+foo2 (uint32x4_t b, mve_pred16_t p)
 {
-  return vmaxvq_p (a, b, p);
+  return vmaxvq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
index 7df5b63c9bc..358cb40f829 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +22,36 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
-foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p)
+foo2 (uint8x16_t b, mve_pred16_t p)
 {
-  return vmaxvq_p (a, b, p);
+  return vmaxvq_p (1, b, p);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
index 8412452cf33..485355a7d72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b)
 {
@@ -11,18 +18,16 @@ foo (int16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b)
 {
   return vmaxvq (a, b);
 }
 
-
-int16_t
-foo2 (int8_t a, int16x8_t b)
-{
-  return vmaxvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
index 09f4909c9a8..3b9075689a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b)
 {
@@ -11,18 +18,16 @@ foo (int32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b)
 {
   return vmaxvq (a, b);
 }
 
-
-int32_t
-foo2 (int16_t a, int32x4_t b)
-{
-  return vmaxvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
index a087bbc6b64..f13a0168d9d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b)
 {
@@ -11,18 +18,16 @@ foo (int8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b)
 {
   return vmaxvq (a, b);
 }
 
-
-int8_t
-foo2 (int32_t a, int8x16_t b)
-{
-  return vmaxvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
index 47fe0d1cf0f..6a0fe254043 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b)
 {
@@ -11,18 +18,28 @@ foo (uint16_t a, uint16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b)
 {
   return vmaxvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
-foo2 (uint32_t a, uint16x8_t b)
+foo2 (uint16x8_t b)
 {
-  return vmaxvq (a, b);
+  return vmaxvq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
index aa723daf5dd..eed20046e53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b)
 {
@@ -11,18 +18,28 @@ foo (uint32_t a, uint32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b)
 {
   return vmaxvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint8_t a, uint32x4_t b)
+foo2 (uint32x4_t b)
 {
-  return vmaxvq (a, b);
+  return vmaxvq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
index 3aae785040c..d44a6d3bb02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
@@ -1,9 +1,16 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmaxv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b)
 {
@@ -11,18 +18,28 @@ foo (uint8_t a, uint8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b)
 {
   return vmaxvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
-foo2 (uint16_t a, uint8x16_t b)
+foo2 (uint8x16_t b)
 {
-  return vmaxvq (a, b);
+  return vmaxvq (1, b);
 }
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit c67e3f7b05d6f8275af8c829d32c96932a7deba2
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 16:25:17 2022

    arm: improve tests for vabavq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
    
    (cherry picked from commit 8965dd164b1c72dec9e5f3dcc6506813f8fbe4c3)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
index 78ac801fa3c..843d022c418 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vabavq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
index af4e30b6127..6ed9b9ac1c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vabavq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
index a76b6bd4bda..ec34be92a28 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vabavq_p_s8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
index 9627a00b812..440b603a18e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
 {
   return vabavq_p_u16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
index 298c2c38101..9500ee054b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vabavq_p_u32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
index 775072225f8..40c9a51fbe4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
 {
   return vabavq_p_u8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
index c2383f1865b..27684fa4a88 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int16x8_t b, int16x8_t c)
 {
   return vabavq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int16x8_t b, int16x8_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s16"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int16x8_t b, int16x8_t c)
+{
+  return vabavq (1, b, c);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
index 7170d013c3b..f595609a2a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, int32x4_t c)
 {
   return vabavq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, int32x4_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s32"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, int32x4_t c)
+{
+  return vabavq (1, b, c);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
index d75ecdbdbdf..60fa9e23b7b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int8x16_t b, int8x16_t c)
 {
   return vabavq_s8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int8x16_t b, int8x16_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s8"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int8x16_t b, int8x16_t c)
+{
+  return vabavq (1, b, c);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
index 40ab94d9083..f3255276eda 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b, uint16x8_t c)
 {
   return vabavq_u16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b, uint16x8_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b, uint16x8_t c)
+{
+  return vabavq (1, b, c);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
index 4b9f5c32f3d..f41fa1f3952 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, uint32x4_t c)
 {
   return vabavq_u32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, uint32x4_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b, uint32x4_t c)
+{
+  return vabavq (1, b, c);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
index 3638e9d7106..3a2654435df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b, uint8x16_t c)
 {
   return vabavq_u8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b, uint8x16_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b, uint8x16_t c)
+{
+  return vabavq (1, b, c);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 328de4f103e919026129fd9232f6b159fc2a1936
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 16:29:33 2022

    arm: improve tests for vabdq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
    
    (cherry picked from commit c548e1b22363960b05b2c36257e677da920ea228)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
index b55e826e4b6..f379b25c49e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vabdq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
index f1a95b14e03..3ba808e0b4d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vabdq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
index f92e671edec..903c6dfe861 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
index 5e30997c997..4ddf4ee5c61 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
index 35809895dea..c719a0b5e9c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
index 77d97e1db63..048554144cd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
index a0004d9f290..458b920b5cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
index c4dc9a469da..8e163edb153 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
index 18a64d3a19d..619d4706dc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
index 494f39cb857..079478df08a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
index 73773ac9ebc..0dce4c482ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vabdq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
index 3c552a2969e..f5908fe81d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vabdq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
index f7de6f707ac..3f249e1a622 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vabdq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
index 90d1c873cca..16a4b930d2c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vabdq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
index 405dca51466..2b5ee12945c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vabdq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
index 2b693c16520..50a4c162c9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vabdq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
index 9d771a3325f..da142f4394b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
index 498851348d5..1ff1bef258f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
index 1fa77cc5cae..6733e2bcc14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
index 24a62702482..8d7631b9ac6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
index f96c2dfd147..90784c1d389 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
index 820b8416330..f376374564a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
index 2d81930348a..d9467a1ccd7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
index 7f956850b52..1ea3713d12b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 8aa5cd69d89d18d056f1cc75a7400a6fdb1edef7
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Oct 10 16:34:06 2022

    arm: improve tests and fix vabsq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vabsq_f<mode>): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
    
    (cherry picked from commit ff2bf3dc61f453c2fe206cd8e9489300a1ca2763)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index b91d06faaeb..ffc25a46aa3 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -272,7 +272,7 @@
 	(abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vabs.f%#<V_sz_elem>  %q0, %q1"
+  "vabs.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
index 08e141baedc..f29ada8c058 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
@@ -1,13 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabs.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vabsq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vabs.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vabsq (a);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
index 3614a44fbdc..cc24744fb26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
@@ -1,13 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabs.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vabsq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vabs.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vabsq (a);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
index 30c14a151af..21cf284d045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vabsq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
index 652056aa98c..236830b3a9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vabsq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
index 2dcf488bd0d..22f7b37b30b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vabsq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
index 183909fef93..b3021edf52b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vabsq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
index cd17974838e..da9ff2f978a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vabsq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
index 243afebc38c..84906302c8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
@@ -1,21 +1,33 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vabsq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vabsq (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
index d9843503a48..117c787d595 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
@@ -1,21 +1,33 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vabsq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vabsq (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
index 93bf1520dd3..a7f1413505c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vabsq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vabsq (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
index d1fc7002ccb..f24a8cccb53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vabsq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
index 0beccac030d..fd4c2277969 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vabsq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
index fd67fd5ccac..0e1d1bb94d4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vabsq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
index 22d561d1e46..64d0e4b574d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vabsq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
index 6908a6ca20c..742bc701fae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vabsq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 7d3043505c770e96d5471edee2b97c8169f26316
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Nov 10 16:02:47 2022

    arm: further fix overloading of MVE vaddq[_m]_n intrinsic
    
    It was observed that in tests `vaddq_m_n_[s/u][8/16/32].c`, the _Generic
    resolution would fall back to the `__ARM_undef` failure state.
    
    This is a regression since `dc39db873670bea8d8e655444387ceaa53a01a79` and
    `6bd4ce64eb48a72eca300cb52773e6101d646004`, but it previously wasn't
    identified, because the tests were not checking for this kind of failure.
    
    The above commits changed the definitions of the intrinsics from using
    `[u]int[8/16/32]_t` types for the scalar argument to using `int`. This
    allowed `int` to be supported in user code through the overloaded
    `#defines`, but seems to have broken the `[u]int[8/16/32]_t` types
    
    The solution implemented by this patch is to explicitly use a new
    _Generic mapping from all the `[u]int[8/16/32]_t` types for int. With this
    change, both `int` and `[u]int[8/16/32]_t` parameters are supported from
    user code and are handled by the overloading mechanism correctly.
    
    Note that in these scalar cases it is safe to pass the raw p<n>, rather
    than the typeof-ed __p<n>, because we are not at risk of the _Generics
    being exponentially expanded on the `n` scalar argument to an `_n`
    intrinsic. Using p<n> instead will give a more accurate error message
    to the user, should something be wrong with that argument.
    
    gcc/ChangeLog:
            PR target/96795
            * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types.
            (__arm_vaddq_m_n_s32): Likewise.
            (__arm_vaddq_m_n_s16): Likewise.
            (__arm_vaddq_m_n_u8): Likewise.
            (__arm_vaddq_m_n_u32): Likewise.
            (__arm_vaddq_m_n_u16): Likewise.
            (__arm_vaddq_m): Fix Overloading.
            (__ARM_mve_coerce3): New.
    
    (cherry picked from commit e0dd75fe90ef4cda94f431747d239d6cfcf5656f)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 684f997520f..951dc25374b 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -9675,42 +9675,42 @@ __arm_vabdq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pr
 
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_sv16qi (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_sv4si (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_sv8hi (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_uv16qi (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_uv4si (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_uv8hi (__inactive, __a, __b, __p);
 }
@@ -26417,42 +26417,42 @@ __arm_vabdq_m (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16
 
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_s8 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_s32 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_s16 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_u8 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_u32 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_u16 (__inactive, __a, __b, __p);
 }
@@ -35657,6 +35657,8 @@ extern void *__ARM_undef;
     _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef)
 #define __ARM_mve_coerce2(param, type) \
     _Generic(param, type: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)
+#define __ARM_mve_coerce3(param, type) \
+    _Generic(param, type: param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef)
 
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
@@ -35871,14 +35873,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(p0, float16x8_t), __ARM_mve_coerce(p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(p0, float32x4_t), __ARM_mve_coerce(p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
 
@@ -37316,12 +37318,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
 
@@ -38820,12 +38822,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39641,12 +39643,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \

commit bbdf67595a57b1b029cfe17a581efe42c242b6e4
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Nov 10 16:02:52 2022

    arm: propagate fixed overloading of MVE intrinsic scalar parameters
    
    This is a mechanical patch that propagates the change proposed in
    my previous patch for vaddq[_m]_n
    across all other polymorphic MVE intrinsic overloads of scalar types.
    
    The find and Replace patterns used were:
    
    s/__ARM_mve_coerce\(__p(\d+), [u]?int(8|16|32|64)_t\)
    /__ARM_mve_coerce3(p$1, int)/g
    
    s/__ARM_mve_coerce2\(__p(\d+), double\)
    /__ARM_mve_coerce2(p$1, double)/g
    
    gcc/ChangeLog:
            PR target/96795
            * config/arm/arm_mve.h (__arm_vaddq): Fix Overloading.
            (__arm_vmulq): Likewise.
            (__arm_vcmpeqq): Likewise.
            (__arm_vcmpneq): Likewise.
            (__arm_vmaxnmavq): Likewise.
            (__arm_vmaxnmvq): Likewise.
            (__arm_vminnmavq): Likewise.
            (__arm_vsubq): Likewise.
            (__arm_vminnmvq): Likewise.
            (__arm_vrshlq): Likewise.
            (__arm_vqsubq): Likewise.
            (__arm_vqdmulltq): Likewise.
            (__arm_vqdmullbq): Likewise.
            (__arm_vqdmulhq): Likewise.
            (__arm_vqaddq): Likewise.
            (__arm_vhaddq): Likewise.
            (__arm_vhsubq): Likewise.
            (__arm_vqdmlashq): Likewise.
            (__arm_vqrdmlahq): Likewise.
            (__arm_vmlasq): Likewise.
            (__arm_vqdmlahq): Likewise.
            (__arm_vmaxnmavq_p): Likewise.
            (__arm_vmaxnmvq_p): Likewise.
            (__arm_vminnmavq_p): Likewise.
            (__arm_vminnmvq_p): Likewise.
            (__arm_vfmasq_m): Likewise.
            (__arm_vsetq_lane): Likewise.
            (__arm_vcmpneq_m): Likewise.
            (__arm_vhaddq_x): Likewise.
            (__arm_vhsubq_x): Likewise.
            (__arm_vqrdmlashq_m): Likewise.
            (__arm_vqdmlashq_m): Likewise.
            (__arm_vmlaldavaxq_p): Likewise.
            (__arm_vmlasq_m): Likewise.
            (__arm_vqdmulhq_m): Likewise.
            (__arm_vqdmulltq_m): Likewise.
            (__arm_viwdupq_m): Likewise.
            (__arm_viwdupq_u16): Likewise.
            (__arm_viwdupq_u32): Likewise.
            (__arm_viwdupq_u8): Likewise.
            (__arm_vdwdupq_m): Likewise.
            (__arm_vdwdupq_u16): Likewise.
            (__arm_vdwdupq_u32): Likewise.
            (__arm_vdwdupq_u8): Likewise.
            (__arm_vaddlvaq): Likewise.
            (__arm_vaddlvaq_p): Likewise.
            (__arm_vaddvaq): Likewise.
            (__arm_vaddvaq_p): Likewise.
            (__arm_vcmphiq_m): Likewise.
            (__arm_vmladavaq_p): Likewise.
            (__arm_vmladavaxq): Likewise.
            (__arm_vmlaldavaxq): Likewise.
            (__arm_vrmlaldavhaq_p): Likewise.
    
    (cherry picked from commit 31df339a50c30712c1e071d2b18f304b148a3165)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 951dc25374b..fd1876b57a0 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35881,8 +35881,8 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
 
 #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -35927,14 +35927,14 @@ extern void *__ARM_undef;
 #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35959,14 +35959,14 @@ extern void *__ARM_undef;
 #define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35997,16 +35997,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
 
 #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36014,13 +36014,13 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
 
 #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36030,11 +36030,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
 
 #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36042,25 +36042,25 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
 
 #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36115,8 +36115,8 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36127,14 +36127,14 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36145,8 +36145,8 @@ extern void *__ARM_undef;
 #define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36168,14 +36168,14 @@ extern void *__ARM_undef;
 #define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36188,8 +36188,8 @@ extern void *__ARM_undef;
 #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36244,12 +36244,12 @@ extern void *__ARM_undef;
 #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36280,12 +36280,12 @@ extern void *__ARM_undef;
 #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36336,12 +36336,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36349,9 +36349,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36384,8 +36384,8 @@ extern void *__ARM_undef;
 #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
@@ -36398,17 +36398,17 @@ extern void *__ARM_undef;
 #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
 #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -36416,12 +36416,12 @@ extern void *__ARM_undef;
 #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36454,12 +36454,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36484,12 +36484,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36632,12 +36632,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36716,44 +36716,44 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36943,11 +36943,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
@@ -36959,11 +36959,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
 
 #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36973,11 +36973,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36990,14 +36990,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
 
 #define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37051,8 +37051,8 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));})
 
@@ -37067,8 +37067,8 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)));})
 
 #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37091,14 +37091,14 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37109,14 +37109,14 @@ extern void *__ARM_undef;
 #define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37178,13 +37178,13 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
 
 #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37285,11 +37285,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
@@ -37324,8 +37324,8 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37466,15 +37466,15 @@ extern void *__ARM_undef;
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37509,14 +37509,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37543,14 +37543,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38023,19 +38023,19 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -38158,19 +38158,19 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -38258,8 +38258,8 @@ extern void *__ARM_undef;
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
 
 #define __arm_vcmulq_rot90_x(p1,p2,p3)  ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -38283,16 +38283,16 @@ extern void *__ARM_undef;
 #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #else /* MVE Integer.  */
 
@@ -38410,12 +38410,12 @@ extern void *__ARM_undef;
 #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38442,12 +38442,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38461,12 +38461,12 @@ extern void *__ARM_undef;
 #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38497,12 +38497,12 @@ extern void *__ARM_undef;
 #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38571,12 +38571,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38584,16 +38584,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -38601,12 +38601,12 @@ extern void *__ARM_undef;
 #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38637,12 +38637,12 @@ extern void *__ARM_undef;
 #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38717,12 +38717,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38747,12 +38747,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38858,12 +38858,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38944,16 +38944,16 @@ extern void *__ARM_undef;
 #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
 #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
@@ -38963,9 +38963,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38973,9 +38973,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38983,9 +38983,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38993,20 +38993,20 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
@@ -39031,12 +39031,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
 
 #define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -39146,25 +39146,25 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39227,9 +39227,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
 
 
 #define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
@@ -39238,9 +39238,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
 
 #define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39248,9 +39248,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
 
 #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39258,9 +39258,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39271,12 +39271,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
 
 #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39299,23 +39299,23 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39340,9 +39340,9 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
 
 #define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39505,12 +39505,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39610,12 +39610,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39660,12 +39660,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40002,15 +40002,15 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -40104,15 +40104,15 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -40234,14 +40234,14 @@ extern void *__ARM_undef;
 #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
 
 #endif /* MVE Integer.  */
 
@@ -40421,12 +40421,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40451,12 +40451,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40576,25 +40576,25 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40695,12 +40695,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40715,9 +40715,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40843,17 +40843,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
 #define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40992,12 +40992,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -41031,12 +41031,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41064,23 +41064,23 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41126,12 +41126,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -41143,17 +41143,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
@@ -41164,15 +41164,15 @@ extern void *__ARM_undef;
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
 
 #define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
@@ -41238,9 +41238,9 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
 #define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41311,51 +41311,51 @@ extern void *__ARM_undef;
 #define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, (const int) p2), \
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, (const int) p2), \
   int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));})
 
 #define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \
   int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
 
 #define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \
   int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, p2), \
   int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \
   int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \
   int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
@@ -41392,14 +41392,14 @@ extern void *__ARM_undef;
 #define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41414,22 +41414,22 @@ extern void *__ARM_undef;
 #define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41455,9 +41455,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41465,9 +41465,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
 
 #define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41475,16 +41475,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
@@ -41581,34 +41581,34 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41651,17 +41651,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
 
 #define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41856,15 +41856,15 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \

commit 79431d45e2c25dc8608c8ddc6d2798dbcb79650a
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Nov 10 16:06:47 2022

    arm: Explicitly specify other float types for _Generic overloading [PR107515]
    
    This patch adds explicit references to other float types
    to __ARM_mve_typeid in arm_mve.h.  Resolves PR 107515:
    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107515
    
    gcc/ChangeLog:
            PR target/107515
            * config/arm/arm_mve.h (__ARM_mve_typeid): Add float types.
    
    (cherry picked from commit 2fefb8931d566cc8a4cbba81601972b0d2002f95)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index fd1876b57a0..f6b42dc3fab 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35582,6 +35582,9 @@ enum {
 	short: __ARM_mve_type_int_n, \
 	int: __ARM_mve_type_int_n, \
 	long: __ARM_mve_type_int_n, \
+	_Float16: __ARM_mve_type_fp_n, \
+	__fp16: __ARM_mve_type_fp_n, \
+	float: __ARM_mve_type_fp_n, \
 	double: __ARM_mve_type_fp_n, \
 	long long: __ARM_mve_type_int_n, \
 	unsigned char: __ARM_mve_type_int_n, \

commit 37d0faa2aa9925a04a81c54c026309ccb95fe8c5
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Wed Nov 16 14:05:49 2022

    arm: Add integer vector overloading of vsubq_x instrinsic
    
    In the past we had only defined the vsubq_x generic overload of the
    vsubq_x_* intrinsics for float vector types.  This would cause them
    to fall back to the `__ARM_undef` failure state if they was called
    through the generic version.
    This patch simply adds these overloads.
    
    gcc/ChangeLog:
    
            * config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads.
            (__arm_vsubq_x Integer): New.
    
    (cherry picked from commit bf6b04c6baa12fccc0dad53d45ae808def34fb6c)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index f6b42dc3fab..09167ec118e 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -38259,6 +38259,18 @@ extern void *__ARM_undef;
 #define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
@@ -40223,6 +40235,22 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
   int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
 
+#define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+  __typeof(p2) __p2 = (p2); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+
 #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int8x16_t]: __arm_vgetq_lane_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \

commit 59e6d480c2c7324bedc3413328496a8bea09b611
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Tue Nov 15 10:29:31 2022

    arm: improve tests and fix vadd*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si)
            (mve_vaddq_n_<supf><mode>, mve_vaddvaq_<supf><mode>)
            (mve_vaddlvaq_<supf>v4si, mve_vaddq_n_f<mode>)
            (mve_vaddlvaq_p_<supf>v4si, mve_vaddq<mode>, mve_vaddq_f<mode>):
            Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
    
    (cherry picked from commit 78b5b76f935f5ba3a5d4b58ccd0ab21b7bfe6f39)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index ffc25a46aa3..053ca97fa2f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -629,7 +629,7 @@
 	 VADDLVQ))
   ]
   "TARGET_HAVE_MVE"
-  "vaddlv.<supf>32 %Q0, %R0, %q1"
+  "vaddlv.<supf>32\t%Q0, %R0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -810,7 +810,7 @@
 	 VADDLVQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
+  "vpst\;vaddlvt.<supf>32\t%Q0, %R0, %q1"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -873,7 +873,7 @@
 	 VADDQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vadd.i%#<V_sz_elem>	%q0, %q1, %2"
+  "vadd.i%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -888,7 +888,7 @@
 	 VADDVAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vaddva.<supf>%#<V_sz_elem>	%0, %q2"
+  "vaddva.<supf>%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1828,7 +1828,7 @@
 	 VADDLVAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vaddlva.<supf>32 %Q0, %R0, %q2"
+  "vaddlva.<supf>32\t%Q0, %R0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1843,7 +1843,7 @@
 	 VADDQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vadd.f%#<V_sz_elem>	%q0, %q1, %2"
+  "vadd.f%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -3712,7 +3712,7 @@
 	 VADDLVAQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
+  "vpst\;vaddlvat.<supf>32\t%Q0, %R0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -8923,7 +8923,7 @@
 		    (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vadd.i%#<V_sz_elem>  %q0, %q1, %q2"
+  "vadd.i%#<V_sz_elem>\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -8937,7 +8937,7 @@
 		    (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vadd.f%#<V_sz_elem> %q0, %q1, %q2"
+  "vadd.f%#<V_sz_elem>\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
index 0991ac1b355..3a9504df94e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
index 5af786e8e76..6e2613ee099 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b, mve_pred16_t p)
+{
+  return vaddlvaq_p (1, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
index 78f155f1586..180dc9b2deb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddlva.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b)
 {
   return vaddlvaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlva.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b)
 {
   return vaddlvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
index a7dfa2541ab..1f899e92c3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddlva.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b)
 {
   return vaddlvaq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlva.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b)
 {
   return vaddlvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vaddlva.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b)
+{
+  return vaddlvaq (1, b);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
index 8aa18323b53..5b22da49c1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
index a9cee74e2ee..2c85139435a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
index 4bd70aacc05..bdb04b5214f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
@@ -1,21 +1,33 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddlv.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a)
 {
   return vaddlvq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddlv.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlv.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a)
 {
-  return vaddlvq_s32 (a);
+  return vaddlvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddlv.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
index 2148bd9a32e..bcd9d21df4f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddlv.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a)
 {
-    return vaddlvq_u32 (a);
+  return vaddlvq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddlv.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlv.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a)
 {
-    return vaddlvq (a);
+  return vaddlvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddlv.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
index 3d1100a9e81..58462177473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vaddq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
index e15e0d13e4f..f3fcd286f4d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vaddq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
index 51d7020bd1f..291e65f32cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
index 7821bc241ff..0346f65a330 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
index 796bed47613..9d57bbd27b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
index afa3c4c722e..9939aa0012d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
index 0ef433724ba..50b138fc763 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
index 46ac88e940d..66c2be777ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
index 1867d5603d1..87dba75dff1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
index 1da993b5e31..a8e9ea576b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
index d7404c9f4ce..045e5024d5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
index 013e83938b2..3d17afcbe56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
index 244c88fcf89..87210a41dae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
index 7a59d75af11..1acb0b67fa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
index 5b8c74ab017..6136c54cbb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
index f28e3d789ab..b60d98e0691 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
index aeb836ce87d..d56bbae9b03 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
index c698df3a146..9f0b623c3e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
index 024fab5c0b2..5df23a6e61f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b)
 {
   return vaddq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a)
+{
+  return vaddq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
index 06b1528460e..d07927c427e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b)
 {
   return vaddq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a)
+{
+  return vaddq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
index 63765f41deb..9ae30406f51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vaddq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
index e462fbfab8e..3271d4d5af1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vaddq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
index ad7181fd8f5..119fd5d5528 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vaddq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
index dac7a9fb9ba..ef0722e4dcd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vaddq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
index 2f1feb89d32..67513819f39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vaddq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
index 325bdade765..2aa79e5e916 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vaddq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
index 31f6cb42e9f..24b12a6aee1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
index 96aead168cc..3fdfa3d86e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
index 6676a2e269b..6b32b8ccfd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
index 1b19876e09a..0deefa14ac6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
index 8f5acc69e79..44df963f0f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
index e5be2fa1b59..7349fa165bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
index bd2a198eb72..b1d48a1d260 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
index 5369f4d4876..047043d6526 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
index d2eed8cf66f..ed67007df51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
index 40d56da12b1..fa17d6b4aa2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
index e974cdf914b..d6c3252132a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
index a6ac9ccd3af..c2a861706d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
index f5539ef9c67..abc90a4c86b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
index f167df122a0..8866a07bc8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
index 653c3eed7a0..4123ad594ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
index 0ad65c8dde5..d610930a311 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
index 75b1491e17d..323010a6d33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
index 1aadebda459..98773e7ba6f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
index d6b07cee79a..bff0bda1109 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
index 5c9abc2492a..85f5cd4db7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
index d55ec735460..ad0e7afbc39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
index bcc058b3769..a3cfc5686e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
index c4bfe34aa91..16b51514be1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
index cdc32807a24..bbf04aa0d08 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
index d330411115a..f06623b1893 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
index 74d9246cd63..7bfb4bb9cbe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b, mve_pred16_t p)
+{
+  return vaddvaq_p (1, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
index e4ec42b2544..9aea5caa4fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b, mve_pred16_t p)
+{
+  return vaddvaq_p (1, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
index f9bed8379a4..b5113b209c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b, mve_pred16_t p)
+{
+  return vaddvaq_p (1, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
index 5f6a8cf9d89..1b9af185a0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddva.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b)
 {
   return vaddvaq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
index 29e27f59328..e25487954d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddva.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b)
 {
   return vaddvaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
index cac43464679..d37c916c94d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddva.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b)
 {
   return vaddvaq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
index c943fa5789f..b3583ce5725 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddva.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b)
 {
   return vaddvaq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vaddva.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b)
+{
+  return vaddvaq (1, b);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
index 0950ff50d0f..006c0a3734f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddva.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b)
 {
   return vaddvaq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vaddva.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b)
+{
+  return vaddvaq (1, b);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
index 2a58225fbe3..cfe29bfd7be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddva.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b)
 {
   return vaddvaq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vaddva.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b)
+{
+  return vaddvaq (1, b);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
index a786b8974b7..3d19b46fdc6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
index c688782180f..a148d15ead1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
index 8438448f86c..f0b0c499d0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
index ec7a5fa5a7f..2fb316c50ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
index b70968880ce..24bde90ec77 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
index 69381b78cc4..f6710941119 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
index b4fc11f4aa4..6b9a99f2b07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
@@ -1,21 +1,33 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a)
 {
   return vaddvq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a)
 {
-  return vaddvq_s16 (a);
+  return vaddvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
index 438b46ec246..50823b65ecc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
@@ -1,21 +1,33 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a)
 {
   return vaddvq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a)
 {
-  return vaddvq_s32 (a);
+  return vaddvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
index b60b1f2da98..131edbe2b3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
@@ -1,21 +1,33 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a)
 {
   return vaddvq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a)
 {
   return vaddvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
index de782127faf..7c0ac0e1395 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint16x8_t a)
 {
-    return vaddvq_u16 (a);
+  return vaddvq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint16x8_t a)
 {
-    return vaddvq (a);
+  return vaddvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
index c4672e42288..40779ed0f99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32x4_t a)
 {
-    return vaddvq_u32 (a);
+  return vaddvq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32x4_t a)
 {
-    return vaddvq (a);
+  return vaddvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
index e4e149cfb61..d2a6ba8f0fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vaddv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint8x16_t a)
 {
-    return vaddvq_u8 (a);
+  return vaddvq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint8x16_t a)
 {
-    return vaddvq (a);
+  return vaddvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 58a9a52375634888d68b9078dfb21e628bfc5337
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Tue Nov 15 14:52:50 2022

    arm: improve tests for vmulq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
    
    (cherry picked from commit 49681b1d90920bd98b0cc51b2bb9f3fcaabc22c1)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
index 68fb012ad34..9251809bfa1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vmulq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
index 512661aeec7..3dacb7ad77c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vmulq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
index d05d48f6261..8f47e962633 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
index 8c2ec81da3b..41f3786e5fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
index 1f1d408d5b9..2f4fecbf56b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
index 4aae0849e2b..2ad4108d637 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
index 9a87f7d3643..b10bd5af687 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
index da7d38b9968..e8bdf7278ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
index 227b3a50a92..001e888e075 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
index e09334df1de..5015f20a4be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
index 62d6c262e5a..a6013a42721 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
index e7993ab3c31..42fc7264229 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
index 61cdf656c19..04fdc010f5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
index 622407b96da..96178d02e37 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
index bb2943cc727..aa3b8061122 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
index a0680174753..e56ab77f3ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
index 586a32560d7..72e313cfd78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
index 0a8e49a5982..1ae6a93934c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
index a3f693f06f7..d77aeb219ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b)
 {
   return vmulq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a)
+{
+  return vmulq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
index 5d1cfa368a7..9ef6a21b2bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b)
 {
   return vmulq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a)
+{
+  return vmulq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
index 98e84cbf202..7ea25dce4a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vmulq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
index adbfd6fe10b..b884603ac5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vmulq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
index c845f108f88..8e6e17cd593 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vmulq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
index e52acdc53b9..907bb0a4009 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vmulq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vmulq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
index 9da4bc1f359..1164b29fc76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vmulq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vmulq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
index e0f152db729..ccc950e3ccf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vmulq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vmulq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
index 89cc604fda0..a1fc1fc8f04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmulq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
index f87fbf1249c..4fcf0dd88d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmulq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
index 4e40065ad22..d0c147ef912 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmulq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
index ae95bf68afe..d4a24ba95b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
index 4f8e9762d5f..c9194b73eaf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmulq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
index a3776ff8314..d69402021ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
index 1f864cf481a..169871b47d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
index 07cc3d0277c..f800731b3ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
index 8fa6c759d54..a4dc47725b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
index 654713c1348..e8428fe9b2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
index 4ec5ab397e1..27ef55d932a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
index c52180067cf..929f420bd4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
index a2a7c734de8..31885a2d90f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
index 419a3cb6ea6..5972a525092 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
index 5acfcf6bf61..3e02a542988 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
index 27e95ced0b5..9b59b189a5f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
index 5c232bfdc34..09b7169a68b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
index 685fe45e4d0..a57ef2da840 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
index 19ecc6bcafc..7fb5e007990 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
index 0700ca818ab..7b1c6b2acc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
index a1cb2aa221e..bc53faff33f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
index 3b29852c830..f43760861d4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit f47b54aaef92d589ee69211eb853c0da4212f733
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:20:01 2022

    arm: improve tests and fix vsubq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
    
    (cherry picked from commit 9b8dc6379d600706d3ed790d3ef4c6b25678d289)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 053ca97fa2f..5f25ea6725f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -672,7 +672,7 @@
 	 VSUBQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vsub.f<V_sz_elem>  %q0, %q1, %2"
+  "vsub.f<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
index 8e3ce24fa49..3d82b081ca2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vsubq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
index 5cb239d70fa..d0f64bb9872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vsubq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
index f4b3f806822..434b0a7ced8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
index 75dbf9335c9..0b8e056647e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
index 556a0845087..abbd60060a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
index e53f5f1966a..40ca4284a1f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
index 73443d500ba..f13eff8ad2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
index b4031111678..21ba17ba869 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
index 5c4e1019225..c75b8b5420d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
index 04a3036ede8..700bc01833c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
index a21f9366373..25dd37ae5b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
index 18f635f1e1a..4fed154d258 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
index 598d648887b..dde77dc51b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
index af6750278f1..8770e31ad95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
index 5effbe2e017..c9813313594 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vsubq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
index 12218ae6791..eebc3ad6929 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
index 3a63eeb2b3d..d85bbec7ebf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
index a17a2741a47..a104a74e259 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vsubq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
index 10e27dae907..4db52649ab4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b)
 {
   return vsubq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a)
+{
+  return vsubq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
index 9e16d6c075c..fe97eed7d37 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b)
 {
   return vsubq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a)
+{
+  return vsubq (a, 1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
index 7f2af8691c0..d695fc83e06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
@@ -1,22 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vsubq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
index a5e6bf486fd..c281e21ab0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
@@ -1,22 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vsubq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
index 5754379358d..ef36b4d6330 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
@@ -1,22 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vsubq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
index ea0a3f9260c..be754d894a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vsubq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
index cc409b59438..ef0aaa4cf08 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vsubq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
index 8a18a89b353..c55aefc3307 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vsubq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
index 15e732f1f66..469395452bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vsubq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
index 5b4ee855711..0e60e1c6f60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vsubq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
index b23893af605..882d63dfcf7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vsubq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
index edb5e354411..fe9baf3d52c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vsubq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
index 68040afd52b..b82051d69d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vsubq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
index 92c4f059b0e..630b2f79f1f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vsubq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
index 4cb8be0ea7f..c48bea7e9f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_f16 (a, b, p);
+  return vsubq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
index f6711d7f207..d3e129bb6ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_f32 (a, b, p);
+  return vsubq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
index c4adacbf5be..2dcaff58c09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_f16 (a, b, p);
+  return vsubq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
index a4affa0a3a9..92bafa3c4cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_f32 (a, b, p);
+  return vsubq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
index 99c59b1a6c1..f01e8d7d490 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s16 (a, b, p);
+  return vsubq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
index 6c29ebec05c..506966424cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s32 (a, b, p);
+  return vsubq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
index 0f83c305473..3c4a5d8129c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s8 (a, b, p);
+  return vsubq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
index 9a372d762d1..958e5aa2ce8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u16 (a, b, p);
+  return vsubq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
index 5219f154fa9..ba39c75bb2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u32 (a, b, p);
+  return vsubq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
index 0a0bcf8623a..19204d1d80f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
@@ -1,15 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u8 (a, b, p);
+  return vsubq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
index 37936a6d647..8dcc5477c6f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_s16 (a, b, p);
+  return vsubq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
index c085f59c6a2..a2d43323227 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_s32 (a, b, p);
+  return vsubq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
index 361507821ea..8ead3d22439 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-    return vsubq_x_s8 (a, b, p);
+  return vsubq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
index 21423dc4f80..f0faf8165d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_u16 (a, b, p);
+  return vsubq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
index 38dd09ad8f7..67a70931859 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_u32 (a, b, p);
+  return vsubq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
index 406cbf760fd..19002336cbd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
@@ -1,15 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-    return vsubq_x_u8 (a, b, p);
+  return vsubq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit c2d80e30cebfb6daaa84a62e505eeea8e344d2e9
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:24:14 2022

    arm: improve tests for vfmasq_m*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
    
    (cherry picked from commit 253efaac2d5e97b09bc841d6f85ff908de5760df)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
index 06d2d114e46..03b376c9bbe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo (float16x8_t m1, float16x8_t m2, float16_t add, mve_pred16_t p)
 {
-  return vfmasq_m_n_f16 (a, b, c, p);
+  return vfmasq_m_n_f16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo1 (float16x8_t m1, float16x8_t m2, float16_t add, mve_pred16_t p)
 {
-  return vfmasq_m (a, b, c, p);
+  return vfmasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p)
+{
+  return vfmasq_m (m1, m2, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
index bf1773d0eeb..ecf30ba9826 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo (float32x4_t m1, float32x4_t m2, float32_t add, mve_pred16_t p)
 {
-  return vfmasq_m_n_f32 (a, b, c, p);
+  return vfmasq_m_n_f32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo1 (float32x4_t m1, float32x4_t m2, float32_t add, mve_pred16_t p)
 {
-  return vfmasq_m (a, b, c, p);
+  return vfmasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p)
+{
+  return vfmasq_m (m1, m2, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit cfc47e6e672764c4f80d426531444caafb8caa8b
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:25:20 2022

    arm: improve tests for vhaddq_m*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
    
    (cherry picked from commit 4b440ef5bc199a2a994aeb748b3a65d0c35cc4ed)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
index e90af963697..0bd03832ff5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
index fcce85fd1bd..42fe35dc746 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
index 56558b7033a..1f4a4016c74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
index d7ee0febab9..7d7ebebd638 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vhaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
index 1117b9813ce..31f7ee2fa54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vhaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
index 90c66595d3f..2120472af46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vhaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
index e8b87283a73..4b4ce40efb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
index ddcfd11198e..e532055c675 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
index ef5fcd02cc5..25b81629ec3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
index d7b9aaab62c..4a9e9f3f438 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
index c8d7f6c4cf3..1e68099ebf2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
index 9792941b091..6dd75d7336e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
index d0d77f5a7fd..20a999da1d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vhaddq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
index a8b4f3415a1..986cb8d3ba5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vhaddq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
index 2459ba0a7ab..57a4b36f5fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vhaddq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
index cd681e7a5f9..abed33b0e37 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vhaddq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vhaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
index d2cb7f6284e..5e5204fb3a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vhaddq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vhaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
index 509e1746259..b35221ef81b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vhaddq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vhaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
index 47afc591cdb..310964f3440 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
index fdc6476d0ee..d8222645c21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
index 3321765e909..85b2feee346 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
index ad46355feab..2da0aa053e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vhaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
index 7477585fe55..49b865a123b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vhaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
index 9edf8e5eb90..5ecd3cbf6ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vhaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
index 5a9302129c7..a4e277d4e1f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
index 0a4ef00afa1..c79b88d6ced 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
index ae6c27a8878..61893536231 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
index ddc99a82f79..146d226f36f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vhaddq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
index dce9bc212e2..b70014fb6a5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vhaddq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
index 262c5937a91..03978dfa28a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vhaddq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
index 65df0093401..c3c787583dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
index 7ff76e7170a..a1ab196d3d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
index 23f545c45cd..061ae89315e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
index 97674c1f73c..0ee88520f8f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
index b6404ce9d17..0a0e512c5fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
index 7c2d74a2662..c495641c532 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit b6314488b4d6fae84cab5d24e99f7f2d32d7091b
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:26:06 2022

    arm: improve tests for vhsubq_m*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
    
    (cherry picked from commit d63992a20ae196be73acc0098a957b6e11dbca53)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
index 27dcb7be957..6390589808f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
index 75ae735f30d..db09d0f2c21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
index 84cdeb42952..89ea3f2aaf8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
index bc6610c3812..e6fb8be673b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vhsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
index e94bfc95027..7ab815d5623 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vhsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
index c2a5674afd1..0bf695aded4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vhsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
index 9f62a385554..3bad177ad28 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
index 486ae6b7d58..cc5cdb07059 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
index 9faaa4fbb0d..4c651091e59 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
index aa5838cdad2..daed202c055 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
index 00282ad6444..cf71e6dab13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
index 187d5bcf8a1..a8183dd48ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
index ce766486aed..af4f534d7ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vhsubq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
index 1d820ffaf5a..941d38074a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vhsubq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
index 90110b78f0d..9ceb4ef3c6f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vhsubq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
index e744ef58663..037ed2c637d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vhsubq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vhsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
index b1ce3f07904..f51eb10ecbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vhsubq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vhsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
index 68872a8f900..24dd45db152 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vhsubq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vhsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
index 03bd6d595cb..0f275d48753 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhsubq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
index 515acb84e66..21aeb9d2a59 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhsubq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
index 41fb2589924..b3ee94341b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhsubq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
index dda18779dca..690ef2de5ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vhsubq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
index 86a5576bedf..cfe12573fa0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vhsubq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
index d339ca0e5e4..1926bc34219 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vhsubq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
index 09da5c2f040..fcda4c541a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
index f3c032987bc..55637221f21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
index 1d86f7d72b3..ecfe188f3fa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
index df6b7ea427a..bf3d6c38b85 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vhsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
index bea6f2d1f96..4ae75b09950 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vhsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
index e1fafd7a9f5..edfa4216a31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vhsubq_x (a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
index c9d3ffb45b7..bd2771b0978 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
index 36343cffc85..0ea40df3d9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
index d1b134fe480..90ee94defb0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
index 4da0fb3f340..d700741169a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
index dfb0a6d371f..f43c9626829 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
index d549892ef8b..a0908ba786b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 31d6b46658c55827bb8f515e7bbf67955a576efa
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:28:00 2022

    arm: improve tests for viwdupq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Improve tests.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
    
    (cherry picked from commit ce9dd996b9de7727e092769055931f07bc6f4e5c)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
index 0f999cc672b..67a2465f435 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_n_u16 (inactive, a, b, 2, p);
+  return viwdupq_m_n_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 2, p);
+  return viwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
index f79c91eaf4c..9fc2518acc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_n_u32 (inactive, a, b, 4, p);
+  return viwdupq_m_n_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 4, p);
+  return viwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
index c0fee9fa752..39f4071bfa1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_n_u8 (inactive, a, b, 8, p);
+  return viwdupq_m_n_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 8, p);
+  return viwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
index 468ba179f62..8bb680e0d77 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_wb_u16 (inactive, a, b, 2, p);
+  return viwdupq_m_wb_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 2, p);
+  return viwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
index e9190302717..2dc8d5f3442 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_wb_u32 (inactive, a, b, 4, p);
+  return viwdupq_m_wb_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 4, p);
+  return viwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
index 309ce95a333..ff3a5f520e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_wb_u8 (inactive, a, b, 8, p);
+  return viwdupq_m_wb_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 8, p);
+  return viwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
index 599d9078464..5f37290759a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b)
 {
-  return viwdupq_n_u16 (a, b, 2);
+  return viwdupq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return viwdupq_u16 (a, b, 2);
+  return viwdupq_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return viwdupq_u16 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
index 7c2af74b3f0..de93f8a7ec4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b)
 {
-  return viwdupq_n_u32 (a, b, 4);
+  return viwdupq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return viwdupq_u32 (a, b, 4);
+  return viwdupq_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return viwdupq_u32 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
index 4ff60791f3b..089025c3401 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b)
 {
   return viwdupq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b)
 {
   return viwdupq_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return viwdupq_u8 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
index 1e5ce88dcca..fc3e9c6fac4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint32_t * a, uint32_t b)
+foo (uint32_t *a, uint32_t b)
 {
-  return viwdupq_wb_u16 (a, b, 4);
+  return viwdupq_wb_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint32_t * a, uint32_t b)
+foo1 (uint32_t *a, uint32_t b)
 {
-  return viwdupq_u16 (a, b, 4);
+  return viwdupq_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
+/*
+**foo2:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return viwdupq_u16 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
index 0c076f7b751..4c098dd8f02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t * a, uint32_t b)
+foo (uint32_t *a, uint32_t b)
 {
-  return viwdupq_wb_u32 (a, b, 8);
+  return viwdupq_wb_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t * a, uint32_t b)
+foo1 (uint32_t *a, uint32_t b)
 {
-  return viwdupq_u32 (a, b, 8);
+  return viwdupq_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return viwdupq_u32 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
index 9e5118ba2b6..44cb53fe344 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint32_t * a, uint32_t b)
+foo (uint32_t *a, uint32_t b)
 {
-  return viwdupq_wb_u8 (a, b, 2);
+  return viwdupq_wb_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint32_t * a, uint32_t b)
+foo1 (uint32_t *a, uint32_t b)
 {
-  return viwdupq_u8 (a, b, 2);
+  return viwdupq_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return viwdupq_u8 (1, 1, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
index fdaf6be282d..2242877881f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_n_u16 (a, b, 2, p);
+  return viwdupq_x_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u16 (a, b, 2, p);
+  return viwdupq_x_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u16 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
index affc6162015..4b2b650e21a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_n_u32 (a, b, 4, p);
+  return viwdupq_x_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u32 (a, b, 4, p);
+  return viwdupq_x_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u32 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
index 8137c623c2a..873952b6c2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_n_u8 (a, b, 8, p);
+  return viwdupq_x_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u8 (a, b, 8, p);
+  return viwdupq_x_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u8 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
index d7aa141f384..b6c94797380 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_wb_u16 (a, b, 8, p);
+  return viwdupq_x_wb_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u16 (a, b, 8, p);
+  return viwdupq_x_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u16 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
index 7fe56963452..5fd84963d01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_wb_u32 (a, b, 2, p);
+  return viwdupq_x_wb_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u32 (a, b, 2, p);
+  return viwdupq_x_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u32 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
index 8e3ecefdedb..abbb40fa8da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_wb_u8 (a, b, 4, p);
+  return viwdupq_x_wb_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u8 (a, b, 4, p);
+  return viwdupq_x_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u8 (1, 1, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 4cd5d4d335d86144994b0baf3b6674fcd8e6ab42
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:29:57 2022

    arm: improve tests for vmladavaq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Improve tests.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
    
    (cherry picked from commit 69405ebb53323f5c32062b75ab7af304e7eb6656)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
index e458204c41b..f3e5eba3b08 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_s16 (a, b, c, p);
+  return vmladavaq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s16"  }  } */
-/* { dg-final { scan-assembler "vmladavat.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
index e3544787adb..71f6957bfc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_s32 (a, b, c, p);
+  return vmladavaq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s32"  }  } */
-/* { dg-final { scan-assembler "vmladavat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
index 1d4ca722f44..a74317aeff9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_s8 (a, b, c, p);
+  return vmladavaq_p_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s8"  }  } */
-/* { dg-final { scan-assembler "vmladavat.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
index 91a11c8b8b1..9ac84d46a07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo (uint32_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_u16 (a, b, c, p);
+  return vmladavaq_p_u16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo1 (uint32_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u16"  }  } */
-/* { dg-final { scan-assembler "vmladavat.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+  return vmladavaq_p (1, m1, m2, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
index 0efe8d0902f..4a3d109ed90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo (uint32_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_u32 (a, b, c, p);
+  return vmladavaq_p_u32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo1 (uint32_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u32"  }  } */
-/* { dg-final { scan-assembler "vmladavat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+  return vmladavaq_p (1, m1, m2, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
index a8da9b0d2ef..a17440f4675 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
@@ -1,22 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+foo (uint32_t add, uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_u8 (a, b, c, p);
+  return vmladavaq_p_u8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+foo1 (uint32_t add, uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u8"  }  } */
-/* { dg-final { scan-assembler "vmladavat.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
+{
+  return vmladavaq_p (1, m1, m2, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
index 838717e3e43..f201d5fa047 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p_s16 (a, b, c, p);
+  return vmladavaxq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p (a, b, c, p);
+  return vmladavaxq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s16"  }  } */
-/* { dg-final { scan-assembler "vmladavaxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
index a50c5ecf802..c90647a5064 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p_s32 (a, b, c, p);
+  return vmladavaxq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p (a, b, c, p);
+  return vmladavaxq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s32"  }  } */
-/* { dg-final { scan-assembler "vmladavaxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
index e4705cecad9..57af7bc1c78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p_s8 (a, b, c, p);
+  return vmladavaxq_p_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p (a, b, c, p);
+  return vmladavaxq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s8"  }  } */
-/* { dg-final { scan-assembler "vmladavaxt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
index ffd542a062f..684580d1c36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmladavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c)
+foo (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaxq_s16 (a, b, c);
+  return vmladavaxq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaxq (a, b, c);
+  return vmladavaxq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
index b91e54d79e6..5d152647b55 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmladavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c)
+foo (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaxq_s32 (a, b, c);
+  return vmladavaxq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaxq (a, b, c);
+  return vmladavaxq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
index 61949c416fc..71bcdc9b55e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmladavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c)
+foo (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaxq_s8 (a, b, c);
+  return vmladavaxq_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaxq (a, b, c);
+  return vmladavaxq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit fd2b43d3ba21d8b6fe271efff2db04d2c970696d
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:35:24 2022

    arm: improve tests and fix vmlaldavaxq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
            (mve_vmlaldavaxq_s<mode>, mve_vmlaldavaxq_p_<supf><mode>): Fix
            spacing vs tabs.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
    
    (cherry picked from commit 5a21c1451fc68c8d97e19aac62ed53fa0b803242)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 5f25ea6725f..5dd5189c251 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -4158,7 +4158,7 @@
 	 VMLALDAVAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlaldava.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4174,7 +4174,7 @@
 	 VMLALDAVAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlaldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -6121,7 +6121,7 @@
 	 VMLALDAVAXQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
index f33d3880236..87f0354a636 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p_s16 (a, b, c, p);
+  return vmlaldavaxq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p (a, b, c, p);
+  return vmlaldavaxq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
index ab072a9850e..d26bf5b90af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p_s32 (a, b, c, p);
+  return vmlaldavaxq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p (a, b, c, p);
+  return vmlaldavaxq_p (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
index e68fbd2df94..3a37e7a58a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlaldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c)
+foo (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaxq_s16 (a, b, c);
+  return vmlaldavaxq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaxq (a, b, c);
+  return vmlaldavaxq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavax.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
index 7b6fea289da..155b8be70f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlaldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c)
+foo (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaxq_s32 (a, b, c);
+  return vmlaldavaxq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaxq (a, b, c);
+  return vmlaldavaxq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavax.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 06c2f5154960f8164fd3d3142ee7ca682b9c5fa4
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:38:41 2022

    arm: improve tests for vmlasq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
    
    (cherry picked from commit 4e73978c92be03d54f81d047ad79102c0efcbc5b)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
index bf66e616ec7..af6e588adad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_s16 (a, b, c, p);
+  return vmlasq_m_n_s16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
index 53c21e2e5b6..9d0cc3076d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_s32 (a, b, c, p);
+  return vmlasq_m_n_s32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
index ac08b15fdbe..772ad8b1e76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_s8 (a, b, c, p);
+  return vmlasq_m_n_s8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
index 99f1e28c7d5..b02dc64a31b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, uint16_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_u16 (a, b, c, p);
+  return vmlasq_m_n_u16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, uint16_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+  return vmlasq_m (m1, m2, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
index 8d8edca6024..0214cf2136e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, uint32_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_u32 (a, b, c, p);
+  return vmlasq_m_n_u32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, uint32_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+  return vmlasq_m (m1, m2, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
index e7f685bbcaa..c9824e332f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo (uint8x16_t m1, uint8x16_t m2, uint8_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_u8 (a, b, c, p);
+  return vmlasq_m_n_u8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo1 (uint8x16_t m1, uint8x16_t m2, uint8_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
+{
+  return vmlasq_m (m1, m2, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
index 8bfe3c31096..6708a741790 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlas.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vmlasq_n_s16 (a, b, c);
+  return vmlasq_n_s16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
index db06182abec..4e8bf32e016 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlas.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vmlasq_n_s32 (a, b, c);
+  return vmlasq_n_s32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
index 3a151650ef4..1cb1a31459c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlas.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vmlasq_n_s8 (a, b, c);
+  return vmlasq_n_s8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
index b9444f2f6a3..e03c91ef298 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlas.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo (uint16x8_t m1, uint16x8_t m2, uint16_t add)
 {
-  return vmlasq_n_u16 (a, b, c);
+  return vmlasq_n_u16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo1 (uint16x8_t m1, uint16x8_t m2, uint16_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmlas.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+  return vmlasq (m1, m2, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
index 5708a0658a6..b80c3c7631f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlas.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo (uint32x4_t m1, uint32x4_t m2, uint32_t add)
 {
-  return vmlasq_n_u32 (a, b, c);
+  return vmlasq_n_u32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo1 (uint32x4_t m1, uint32x4_t m2, uint32_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmlas.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+  return vmlasq (m1, m2, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
index d83940c7232..0f37550160e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmlas.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo (uint8x16_t m1, uint8x16_t m2, uint8_t add)
 {
-  return vmlasq_n_u8 (a, b, c);
+  return vmlasq_n_u8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo1 (uint8x16_t m1, uint8x16_t m2, uint8_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmlas.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t m1, uint8x16_t m2)
+{
+  return vmlasq (m1, m2, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit aa1c6b2a3c278a9425a8ae31553f03882c7588d8
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:39:25 2022

    arm: improve tests for vqaddq_m*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
    
    (cherry picked from commit 7e8cf19eee2ec215ff6b714cbf4e6e150e6eb04a)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
index 65d3f770fe2..a659373d441 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
index 4499a0eaa41..8ffc6a67762 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
index d3e1d555cb1..2e88b7fabac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
index baadfe72e8d..61cf9fcf2aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vqaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
index 80808777d9a..bbd255ac1f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vqaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
index 32f2894422d..9cee8c65333 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vqaddq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
index d5b7fa63f6a..8bb8a957423 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
index 015bc3eb206..9959724fc11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
index b241fddd069..6b918978880 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
index fa752355d64..c0a8d9ba9c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
index 0729b6bb30f..7a72ce57840 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
index f1541658399..f7e6ca9b5a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
index 5eeda2bc2dd..0fac7abeac0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqaddq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
index 5b914d18b98..d750b1f2c14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqaddq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
index 06f22c2b8df..5fc796edf75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqaddq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
index 5403f0b6646..decad65c188 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vqaddq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vqaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
index 77185808a16..b0a6d79093e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vqaddq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vqaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
index f0fa9bf3f5d..f9ca9a1f042 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vqaddq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vqaddq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
index 83cd3475a6f..ffa31463372 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
index d26dd206912..c5937a967ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
index de03264b4cc..9f937512811 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
index cd4efc1dd7c..aa4be43f244 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vqaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
index 8b3afb4bd04..daef60eb5ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vqaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
index da2ff1bb25c..e28807ec708 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vqaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit ec357ce4bce80544fca424549e25d58117849899
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:40:05 2022

    arm: improve tests for vqdmlahq_m*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
    
    (cherry picked from commit f974a7b3ecd0c3a0676dc7413af2e8faef005add)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
index d8c4f4bab8e..94d93874542 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m_n_s16 (a, b, c, p);
+  return vqdmlahq_m_n_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m (a, b, c, p);
+  return vqdmlahq_m (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
index 361f5d00bdf..a3dab7fa02e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m_n_s32 (a, b, c, p);
+  return vqdmlahq_m_n_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m (a, b, c, p);
+  return vqdmlahq_m (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
index a9eaea89ba4..610580478a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m_n_s8 (a, b, c, p);
+  return vqdmlahq_m_n_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m (a, b, c, p);
+  return vqdmlahq_m (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
index c109dd47444..210bacec2fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqdmlahq_n_s16 (a, b, c);
+  return vqdmlahq_n_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqdmlahq (a, b, c);
+  return vqdmlahq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
index 752d9d9e3e0..dbb2494b216 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqdmlahq_n_s32 (a, b, c);
+  return vqdmlahq_n_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqdmlahq (a, b, c);
+  return vqdmlahq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
index 8dffa0e1852..a7962f82d38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqdmlahq_n_s8 (a, b, c);
+  return vqdmlahq_n_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqdmlahq (a, b, c);
+  return vqdmlahq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
index 7c2e5cf89dd..34d407f0142 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m_n_s16 (a, b, c, p);
+  return vqdmlashq_m_n_s16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m (a, b, c, p);
+  return vqdmlashq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
index cea9d9b683f..50a665ea7e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m_n_s32 (a, b, c, p);
+  return vqdmlashq_m_n_s32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m (a, b, c, p);
+  return vqdmlashq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
index 83ee258876a..45f34b60382 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m_n_s8 (a, b, c, p);
+  return vqdmlashq_m_n_s8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m (a, b, c, p);
+  return vqdmlashq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
index c71a61c54f6..a3f1ae8d6b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqdmlashq_n_s16 (a, b, c);
+  return vqdmlashq_n_s16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqdmlashq (a, b, c);
+  return vqdmlashq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
index 61f6c6671cc..cf867e56874 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqdmlashq_n_s32 (a, b, c);
+  return vqdmlashq_n_s32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqdmlashq (a, b, c);
+  return vqdmlashq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
index a07892863c1..7e9362cab60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqdmlashq_n_s8 (a, b, c);
+  return vqdmlashq_n_s8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqdmlashq (a, b, c);
+  return vqdmlashq (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 82eb1588060b52652b6b884cf020433e09d8fef3
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:40:46 2022

    arm: improve tests for vqdmul*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
    
    (cherry picked from commit 020708443d6bbb288f53da32faa2d76dbdb8d0dd)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
index 57ab85eaf52..a5c1a106205 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
index 256353a0a21..c78d4db1591 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
index c24be9ed5ad..b5ab6eb292c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
index 49efeefcf63..2f5fb0e53a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
index a5614830622..80a938a8a5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
index 2e016f57e35..bfb755af4ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
index 19534b60b27..e34689d203d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqdmulhq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
index eff9f6ecc4b..f967b8a286a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqdmulhq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
index 188cf7c616f..5e1928fd51b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqdmulhq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
index 513a30f67e6..7c0a434e48f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqdmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
index 9cf147dc7c5..19f4b03f6f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqdmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
index 87211ad054a..1784c967f3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqdmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
index f0a4ad5b9f4..4f96e192732 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
index 1c7b2e4a1fc..d0bca6e3015 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
index 6a056cf86a1..8448cdc88cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
index 019c536e7f2..48cddcd791e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
index ec501c34539..cd7c394139d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16_t b)
 {
   return vqdmullbq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
index 78fe3d6b289..b4d82f55987 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32_t b)
 {
   return vqdmullbq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
index 9a423d3cc66..6f0fdabf67f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqdmullbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
index f0278cd8a86..2bf952bfd77 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqdmullbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
index 85f03149da4..6c756ebf3e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
index 6bb5004e201..e46f6b2c384 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
index a85393b5bc1..8526b3ad628 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
index 82f25b2ebbe..809e0740e46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
index f9ad32a8411..44f0036bc51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16_t b)
 {
   return vqdmulltq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
index 311b023431e..b025886ff15 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32_t b)
 {
   return vqdmulltq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
index 851f27a63b6..95084876349 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqdmulltq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
index 1e81cc3dea5..ab27aeddc29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqdmulltq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 374aefaae67489d3c8282bc9f75fa3fcf5a26bd1
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:41:19 2022

    arm: improve tests for vqrdmlahq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
    
    (cherry picked from commit 5ea0ea55cd062b1a043ba6e30ee2c2e30f8dc2fc)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
index 70c3fa0e9b1..07d689279ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m_n_s16 (a, b, c, p);
+  return vqrdmlahq_m_n_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m (a, b, c, p);
+  return vqrdmlahq_m (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
index 75ed9911276..3b02ca16038 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m_n_s32 (a, b, c, p);
+  return vqrdmlahq_m_n_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m (a, b, c, p);
+  return vqrdmlahq_m (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
index ddaea545f40..b661bdcb4cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m_n_s8 (a, b, c, p);
+  return vqrdmlahq_m_n_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m (a, b, c, p);
+  return vqrdmlahq_m (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
index 45e74971838..16804735b32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqrdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqrdmlahq_n_s16 (a, b, c);
+  return vqrdmlahq_n_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqrdmlahq (a, b, c);
+  return vqrdmlahq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
index 79bb9c98b12..d7d3dc06d7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqrdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqrdmlahq_n_s32 (a, b, c);
+  return vqrdmlahq_n_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqrdmlahq (a, b, c);
+  return vqrdmlahq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
index 220518ae698..d3f9f25f11c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqrdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqrdmlahq_n_s8 (a, b, c);
+  return vqrdmlahq_n_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqrdmlahq (a, b, c);
+  return vqrdmlahq (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 321c5596a2674b59c195f741bb139c538a1f9d6d
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:43:45 2022

    arm: improve tests for vqrdmlashq_m*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c:
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c:
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c:
    
    (cherry picked from commit 354172c5708888d5c6dfec10a0b334775fe9f1fe)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
index 35b9618ca47..da4d724bb46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m_n_s16 (a, b, c, p);
+  return vqrdmlashq_m_n_s16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m (a, b, c, p);
+  return vqrdmlashq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
index 8517835eb61..2430f1cb102 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m_n_s32 (a, b, c, p);
+  return vqrdmlashq_m_n_s32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m (a, b, c, p);
+  return vqrdmlashq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
index e42cc63fa74..30915b24e5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m_n_s8 (a, b, c, p);
+  return vqrdmlashq_m_n_s8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m (a, b, c, p);
+  return vqrdmlashq_m (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 77268ac037386d39aaa561fb749850bd8daa953c
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:44:19 2022

    arm: improve tests for vqsubq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_s16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_s32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_s8.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_u16.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_u32.c:
            * gcc.target/arm/mve/intrinsics/vqsubq_u8.c:
    
    (cherry picked from commit 329ccff3be53bfad4bb6aace2c77382099271a4a)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
index abcff4f0e3c..39b8089919d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
index 23e59ff12a2..ed6b92ddcf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
index d783ab55f65..c69ed2aeb84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
index 5244efb340c..57ba7428bef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vqsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
index 4427f87f456..eda9e74309d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vqsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
index 0abfa5dc132..f6f61b52f52 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vqsubq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
index faa189f8466..1a8ea29e83e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
index 62a4dd0979f..c49b7497f6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
index 71fb6f5632e..17d6471bcd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
index 68d642dfef5..0ce93fdf9be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
index 8f76c5f47da..1eac57545b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
index af335ae9752..56bdda2da6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
index 33a79180289..b9a46f5ff6f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqsubq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
index a2b338839fa..732e6c01b78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqsubq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
index e8d7e99d19d..fb3c4404fba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqsubq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
index f7b48c546a6..aa09d1831e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vqsubq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vqsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
index f74a968f5a7..19b62e3a8a5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vqsubq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vqsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
index ce7b4ce0151..c8eeb38b266 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vqsubq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vqsubq (a, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
index 85bf265eeb0..6c66b4d75d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqsubq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
index 35d17e8bc4e..8432197b9e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqsubq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
index 50cfccff7a5..ad16cae08bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqsubq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
index 15f0b7244b7..264df1a0398 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vqsubq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
index 7d695e23474..a4bf15cd9df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vqsubq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
index c0552d100d4..1804d6484e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vqsubq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 8b7e613b9d99f040fe45dc717342d83501f945e4
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:44:57 2022

    arm: improve tests and fix vrmlaldavhaq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si,
            mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
    
    (cherry picked from commit a59b9af355d69db7fa656c7a3bb6dd8e0d29f98b)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 5dd5189c251..649d10d085f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2538,7 +2538,7 @@
 	 VRMLALDAVHQ))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
+  "vrmlaldavh.<supf>32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2644,7 +2644,7 @@
 	 VRMLALDAVHAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
+  "vrmlaldavha.<supf>32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
index 263d3509771..dec4a969dfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
index 83ab68c001b..f3c8bfd121c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
@@ -1,21 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p_u32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 92c75bf33c141661ae4b60258e0cd70b456b93e8
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Nov 16 14:47:11 2022

    arm: improve tests for vrshlq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
    
    (cherry picked from commit 32be9d72f9c485068b5fb30ede0ab7572cdd1c21)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
index cf51de6aa9c..c7d1f3a5b1c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
index dcfd99773e3..a8713e6a06a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
index cc1b746dc0d..8160d1bdb04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
index 93a95ba9065..b08f4c076d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
index 4b8c82aba21..59f9a13d8c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
index f1ff9dd33b7..fda65f7c592 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
index 57f343cd3b9..20c9f5fcd7c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
index 2598b1719fd..af7a5158458 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
index 6e4f1bdddf4..59d283ebb71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
index d4d98913b75..e731cb71675 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
index 5d60f1fe799..0379e0455c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
index 913ba36c925..1e20486253e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
@@ -1,23 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
index 713c6a218b2..c846e9f06ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vrshlq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
index 18906fe44d1..1c6144212f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vrshlq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
index d5b1286d943..3b9d0a389dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vrshlq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
index 49bb21663d7..77994bd3a29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vrshlq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
index 8ed67395b42..82774c794fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vrshlq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
index ccc6a00b98a..e9badb7297e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vrshlq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
index c28ad31c6f9..4a64fc7b410 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vrshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
index 2e279b6fb0a..c5cbe266c0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
index 4d18419d1bf..85305921f9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vrshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
index e0a9ea9cebc..905a18c4f20 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vrshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
index 788a4b1b6fa..16c7578df39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vrshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
index d860e9cccb9..8bf21eeaef5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
@@ -1,21 +1,33 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vrshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
index 800a1e8e48f..4dfb6a65842 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
index 921072a44c9..7f1f6dbb760 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
index 217b257ed24..69bf0a50fa6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
index 5c0cad9ec89..b5a89892070 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
index 2754d20841c..59ab2662021 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
index 46dada44559..b81d8d03da4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 8baa54ba478ba980234d89aa51a0be84f0bb08bf
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Thu Nov 17 11:06:29 2022

    arm: improve tests for vsetq_lane*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
    
    (cherry picked from commit f2b54e5b796b00f0072b61f9cd6a964c66ead29b)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
index e03e9620528..6b148a4b03d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
@@ -1,15 +1,45 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16_t a, float16x8_t b)
 {
-    return vsetq_lane_f16 (a, b, 0);
+  return vsetq_lane_f16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16_t a, float16x8_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t b)
+{
+  return vsetq_lane (1.1, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
index 2b9f1a7e627..e4e7f892e97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
@@ -1,15 +1,45 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32_t a, float32x4_t b)
 {
-    return vsetq_lane_f32 (a, b, 0);
+  return vsetq_lane_f32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32_t a, float32x4_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t b)
+{
+  return vsetq_lane (1.1, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
index 92ad0dd16a8..950cd016b76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
@@ -1,15 +1,33 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16_t a, int16x8_t b)
 {
-    return vsetq_lane_s16 (a, b, 0);
+  return vsetq_lane_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16_t a, int16x8_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
index e60c8f26700..6b49ccd91e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
@@ -1,15 +1,33 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32_t a, int32x4_t b)
 {
-    return vsetq_lane_s32 (a, b, 0);
+  return vsetq_lane_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32_t a, int32x4_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
index 430df669f2a..95ba4da1f51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
@@ -1,16 +1,33 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64_t a, int64x2_t b)
 {
-    return vsetq_lane_s64 (a, b, 0);
+  return vsetq_lane_s64 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]}  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int64x2_t
+foo1 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
index d8ccbb524fd..91a5baee55f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
@@ -1,15 +1,33 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8_t a, int8x16_t b)
 {
-    return vsetq_lane_s8 (a, b, 0);
+  return vsetq_lane_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8_t a, int8x16_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
index 156a5d1de1b..53986a5c1b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
@@ -1,15 +1,45 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16_t a, uint16x8_t b)
 {
-    return vsetq_lane_u16 (a, b, 0);
+  return vsetq_lane_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16_t a, uint16x8_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
index e9575483cc9..3f17db9623a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
@@ -1,15 +1,45 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32x4_t b)
 {
-    return vsetq_lane_u32 (a, b, 0);
+  return vsetq_lane_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32_t a, uint32x4_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
index 0e040121cf0..5ce4c544c25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
@@ -1,16 +1,45 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64_t a, uint64x2_t b)
 {
-    return vsetq_lane_u64 (a, b, 0);
+  return vsetq_lane_u64 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]}  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64x2_t
+foo1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64x2_t
+foo2 (uint64x2_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
index 668b3fea953..58e932b85e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
@@ -1,15 +1,45 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8_t a, uint8x16_t b)
 {
-    return vsetq_lane_u8 (a, b, 0);
+  return vsetq_lane_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8_t a, uint8x16_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 3de0d4c749f2dd08bafc333cd4922d72757c09ee
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Thu Dec 1 13:50:55 2022

    arm: Fix MVE testsuite fallouts
    
    After the recent patches to improve / tidy up MVE tests and patterns,
    a few more tests need to be updated (replacing spaces with tabs).
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/simd/mve-compare-1.c: Update.
            * gcc.target/arm/simd/mve-compare-scalar-1.c: Update.
            * gcc.target/arm/simd/mve-vabs.c: Update.
            * gcc.target/arm/simd/mve-vadd-1.c: Update.
            * gcc.target/arm/simd/mve-vadd-scalar-1.c: Update.
            * gcc.target/arm/simd/mve-vcmp.c: Update.
            * gcc.target/arm/simd/pr101325.c: Update.
    
    (cherry picked from commit ecc363971aeac52481d92de8b37521f6cc2d38e6)

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c
index 029c931f47f..887f8dbddd9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c
@@ -50,31 +50,31 @@ TEST_TYPE (vs32, __INT32_TYPE__, COMPARE_REG_AND_ZERO, 16)
 TEST_TYPE (vu32, __UINT32_TYPE__, COMPARE_REG, 16)
 
 /* { 8 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i8  eq, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i8  ne, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  lt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  le, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  gt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  ge, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\teq, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\tne, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tle, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tge, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 16 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i16  eq, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i16  ne, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  lt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  le, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  gt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  ge, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\teq, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\tne, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tle, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tge, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 32 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i32  eq, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i32  ne, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  lt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  le, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  gt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  ge, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\teq, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\tne, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tle, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tge, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c
index 77749723693..20ab0a2f040 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c
@@ -39,31 +39,31 @@ TEST_TYPE (vs32, __INT32_TYPE__, 16)
 TEST_TYPE (vu32, __UINT32_TYPE__, 16)
 
 /* { 8 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i8  eq, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i8  ne, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  lt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  le, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  gt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  ge, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\teq, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\tne, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tlt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tle, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tgt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tge, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 16 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i16  eq, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i16  ne, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  lt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  le, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  gt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  ge, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\teq, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\tne, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tlt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tle, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tgt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tge, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 32 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i32  eq, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i32  ne, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  lt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  le, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  gt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  ge, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\teq, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\tne, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tlt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tle, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tgt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tge, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c b/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c
index 64cd1c2eb4a..f2f9ee34990 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c
@@ -38,7 +38,7 @@ FUNC(f, float, 16, 8, vabs)
    integer optimizations actually generate a call to memmove, the other ones a
    'vabs'.  */
 /* { dg-final { scan-assembler-times {vabs.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
-/* { dg-final { scan-assembler-times {vabs.f[0-9]+  q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vabs.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 5 } } */
 /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 5 } } */
 /* { dg-final { scan-assembler-times {memmove} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
index 15a9daacecf..f31d1cc7f42 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
@@ -22,9 +22,9 @@ FUNC(u, uint, 16, 8, +, vadd)
 FUNC(s, int, 8, 16, +, vadd)
 FUNC(u, uint, 8, 16, +, vadd)
 
-/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i32\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
 
 void test_vadd_f32 (float * dest, float * a, float * b) {
   int i;
@@ -32,7 +32,7 @@ void test_vadd_f32 (float * dest, float * a, float * b) {
     dest[i] = a[i] + b[i];
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
 
 void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
   int i;
@@ -40,4 +40,4 @@ void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
     dest[i] = a[i] + b[i];
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c
index bbf70e14146..7eec2346faa 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c
@@ -24,9 +24,9 @@ FUNC_IMM(u, uint, 8, 16, +, vaddimm)
 
 /* For the moment we do not select the T2 vadd variant operating on a scalar
    final argument.  */
-/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.i32\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.i16\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.i8\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
 
 void test_vaddimm_f32 (float * dest, float * a) {
   int i;
@@ -34,7 +34,7 @@ void test_vaddimm_f32 (float * dest, float * a) {
     dest[i] = a[i] + 5.0;
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.f32\tq[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
 
 /* Note that dest[i] = a[i] + 5.0f16 is not vectorized.  */
 void test_vaddimm_f16 (__fp16 * dest, __fp16 * a) {
@@ -44,4 +44,4 @@ void test_vaddimm_f16 (__fp16 * dest, __fp16 * a) {
     dest[i] = a[i] + b;
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c
index 8da15e762eb..806b1458cf3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c
@@ -36,15 +36,15 @@ ALL_FUNCS(>=, vcmpge)
 
 /* MVE has only 128-bit vectors, so we can vectorize only half of the
    functions above.  */
-/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+  eq, q[0-9]+, q[0-9]+\n} 6 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+  ne, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+\teq, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+\tne, q[0-9]+, q[0-9]+\n} 6 } } */
 
 /* lt, le, gt, ge apply to signed types, cs and hi to unsigned types.  */
 /* lt and le with unsigned types are replaced with the opposite condition, hence
    the double number of matches for cs and hi.  */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  lt, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  le, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  gt, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  ge, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+  cs, q[0-9]+, q[0-9]+\n} 6 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+  hi, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tlt, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tle, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tgt, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tge, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+\tcs, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+\thi, q[0-9]+, q[0-9]+\n} 6 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325.c b/gcc/testsuite/gcc.target/arm/simd/pr101325.c
index 4cb2513da87..ce9ce3a8c19 100644
--- a/gcc/testsuite/gcc.target/arm/simd/pr101325.c
+++ b/gcc/testsuite/gcc.target/arm/simd/pr101325.c
@@ -9,6 +9,6 @@ unsigned foo(int8x16_t v, int8x16_t w)
 {
   return vcmpeqq (v, w);
 }
-/* { dg-final { scan-assembler {\tvcmp.i8  eq} } } */
-/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, P0} } } */
+/* { dg-final { scan-assembler {\tvcmp.i8\teq} } } */
+/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, p0} } } */
 /* { dg-final { scan-assembler {\tuxth} } } */

commit 51df90d7fca8c96f35f71dc1bb4d2ecf7f820e70
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Mon Oct 3 12:26:03 2022

    arm: Add missing early clobber to MVE vrev64q_m patterns
    
    Like the non-predicated vrev64q patterns, mve_vrev64q_m_<supf><mode>
    and mve_vrev64q_m_f<mode> need an early clobber constraint, otherwise
    we can generate an unpredictable instruction:
    
    Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE
    when calling vrevq64_m* with the same first and second arguments.
    
    OK for trunk?
    
    Thanks,
    
    Christophe
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vrev64q_m_<supf><mode>): Add early
            clobber.
            (mve_vrev64q_m_f<mode>): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c: New test.
    
    (cherry picked from commit 06aa66af7d0dacc1b247d9e38175e789ef159191)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 649d10d085f..6e2bac55599 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -3498,7 +3498,7 @@
 ;;
 (define_insn "mve_vrev64q_m_<supf><mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:MVE_2 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
@@ -4593,7 +4593,7 @@
 ;;
 (define_insn "mve_vrev64q_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
 		       (match_operand:MVE_0 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c
new file mode 100644
index 00000000000..6464c96181d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c
@@ -0,0 +1,17 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, mve_pred16_t p)
+{
+  return vrev64q_m_s16 (a, a, p);
+}
+
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vrev64q_m_f16 (a, a, p);
+}

commit 37601980933e867813f6c7ac112e1942ad40bd47
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Thu Sep 29 15:34:11 2022

    testsuite: [arm] Relax expected register names in MVE tests
    
    These two tests have hardcoded q0 as destination/source of load/store
    instructions, but this register is actually used only under
    -mfloat-abi=hard. When using -mfloat-abi=softfp, other registers
    (eg. q3) can be used to transfer function arguments from core
    registers to MVE registers, making the expected regexp fail.
    
    This small patch replaces q0 with q[0-7] to accept any 'q' register.
    In several places where we had q[0-9]+, replace it with q[0-7] as MVE
    only has q0-q7 registers.
    
    OK for trunk?
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/mve_load_memory_modes.c: Update expected
            registers.
            * gcc.target/arm/mve/mve_store_memory_modes.c: Likewise.
    
    (cherry picked from commit c09663eabfb84ac56ddd8d44abcab3f4902c83bd)

diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c b/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c
index e35eb1108aa..816980d1203 100644
--- a/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c
@@ -7,7 +7,7 @@
 /*
 **off_load8_0:
 **	...
-**	vldrb.8	q0, \[r0, #16\]
+**	vldrb.8	q[0-7], \[r0, #16\]
 **	...
 */
 int8x16_t off_load8_0 (int8_t * a)
@@ -18,7 +18,7 @@ int8x16_t off_load8_0 (int8_t * a)
 /*
 **off_load8_1:
 **	...
-**	vldrb.u16	q0, \[r0, #1\]
+**	vldrb.u16	q[0-7], \[r0, #1\]
 **	...
 */
 uint16x8_t off_load8_1 (uint8_t * a)
@@ -29,7 +29,7 @@ uint16x8_t off_load8_1 (uint8_t * a)
 /*
 **off_load8_2:
 **	...
-**	vldrb.s32	q0, \[r0, #127\]
+**	vldrb.s32	q[0-7], \[r0, #127\]
 **	...
 */
 int32x4_t off_load8_2 (int8_t * a)
@@ -40,7 +40,7 @@ int32x4_t off_load8_2 (int8_t * a)
 /*
 **off_load8_3:
 **	...
-**	vldrb.8	q0, \[r0, #-127\]
+**	vldrb.8	q[0-7], \[r0, #-127\]
 **	...
 */
 uint8x16_t off_load8_3 (uint8_t * a)
@@ -51,7 +51,7 @@ uint8x16_t off_load8_3 (uint8_t * a)
 /*
 **not_off_load8_0:
 **	...
-**	vldrb.8	q0, \[r[0-9]+\]
+**	vldrb.8	q[0-7], \[r[0-7]+\]
 **	...
 */
 int8x16_t not_off_load8_0 (int8_t * a)
@@ -62,7 +62,7 @@ int8x16_t not_off_load8_0 (int8_t * a)
 /*
 **off_loadfp16_0:
 **	...
-**	vldrh.16	q0, \[r0, #-244\]
+**	vldrh.16	q[0-7], \[r0, #-244\]
 **	...
 */
 float16x8_t off_loadfp16_0 (float16_t *a)
@@ -73,7 +73,7 @@ float16x8_t off_loadfp16_0 (float16_t *a)
 /*
 **off_load16_0:
 **	...
-**	vldrh.16	q0, \[r0, #-2\]
+**	vldrh.16	q[0-7], \[r0, #-2\]
 **	...
 */
 uint16x8_t off_load16_0 (uint16_t * a)
@@ -84,7 +84,7 @@ uint16x8_t off_load16_0 (uint16_t * a)
 /*
 **off_load16_1:
 **	...
-**	vldrh.u32	q0, \[r0, #254\]
+**	vldrh.u32	q[0-7], \[r0, #254\]
 **	...
 */
 uint32x4_t off_load16_1 (uint16_t * a)
@@ -95,7 +95,7 @@ uint32x4_t off_load16_1 (uint16_t * a)
 /*
 **not_off_load16_0:
 **	...
-**	vldrh.16	q0, \[r[0-9]+\]
+**	vldrh.16	q[0-7], \[r[0-7]+\]
 **	...
 */
 int16x8_t not_off_load16_0 (int8_t * a)
@@ -106,7 +106,7 @@ int16x8_t not_off_load16_0 (int8_t * a)
 /*
 **not_off_load16_1:
 **	...
-**	vldrh.u32	q0, \[r[0-9]+\]
+**	vldrh.u32	q[0-7], \[r[0-7]+\]
 **	...
 */
 uint32x4_t not_off_load16_1 (uint16_t * a)
@@ -117,7 +117,7 @@ uint32x4_t not_off_load16_1 (uint16_t * a)
 /*
 **off_loadfp32_0:
 **	...
-**	vldrw.32	q0, \[r0, #24\]
+**	vldrw.32	q[0-7], \[r0, #24\]
 **	...
 */
 float32x4_t off_loadfp32_0 (float32_t *a)
@@ -128,7 +128,7 @@ float32x4_t off_loadfp32_0 (float32_t *a)
 /*
 **off_load32_0:
 **	...
-**	vldrw.32	q0, \[r0, #4\]
+**	vldrw.32	q[0-7], \[r0, #4\]
 **	...
 */
 uint32x4_t off_load32_0 (uint32_t * a)
@@ -139,7 +139,7 @@ uint32x4_t off_load32_0 (uint32_t * a)
 /*
 **off_load32_1:
 **	...
-**	vldrw.32	q0, \[r0, #-508\]
+**	vldrw.32	q[0-7], \[r0, #-508\]
 **	...
 */
 int32x4_t off_load32_1 (int32_t * a)
@@ -149,7 +149,7 @@ int32x4_t off_load32_1 (int32_t * a)
 /*
 **pre_load8_0:
 **	...
-**	vldrb.8	q[0-9]+, \[r0, #16\]!
+**	vldrb.8	q[0-7], \[r0, #16\]!
 **	...
 */
 int8_t* pre_load8_0 (int8_t * a, int8x16_t *v)
@@ -162,7 +162,7 @@ int8_t* pre_load8_0 (int8_t * a, int8x16_t *v)
 /*
 **pre_load8_1:
 **	...
-**	vldrb.u16	q[0-9]+, \[r0, #4\]!
+**	vldrb.u16	q[0-7], \[r0, #4\]!
 **	...
 */
 uint8_t* pre_load8_1 (uint8_t * a, uint16x8_t *v)
@@ -175,7 +175,7 @@ uint8_t* pre_load8_1 (uint8_t * a, uint16x8_t *v)
 /*
 **pre_loadfp16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0, #128\]!
+**	vldrh.16	q[0-7], \[r0, #128\]!
 **	...
 */
 float16_t* pre_loadfp16_0 (float16_t *a, float16x8_t *v)
@@ -188,7 +188,7 @@ float16_t* pre_loadfp16_0 (float16_t *a, float16x8_t *v)
 /*
 **pre_load16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0, #-254\]!
+**	vldrh.16	q[0-7], \[r0, #-254\]!
 **	...
 */
 int16_t* pre_load16_0 (int16_t * a, int16x8_t *v)
@@ -201,7 +201,7 @@ int16_t* pre_load16_0 (int16_t * a, int16x8_t *v)
 /*
 **pre_load16_1:
 **	...
-**	vldrh.s32	q[0-9]+, \[r0, #52\]!
+**	vldrh.s32	q[0-7], \[r0, #52\]!
 **	...
 */
 int16_t* pre_load16_1 (int16_t * a, int32x4_t *v)
@@ -214,7 +214,7 @@ int16_t* pre_load16_1 (int16_t * a, int32x4_t *v)
 /*
 **pre_loadfp32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0, #-72\]!
+**	vldrw.32	q[0-7], \[r0, #-72\]!
 **	...
 */
 float32_t* pre_loadfp32_0 (float32_t *a, float32x4_t *v)
@@ -228,7 +228,7 @@ float32_t* pre_loadfp32_0 (float32_t *a, float32x4_t *v)
 /*
 **pre_load32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0, #-4\]!
+**	vldrw.32	q[0-7], \[r0, #-4\]!
 **	...
 */
 uint32_t* pre_load32_0 (uint32_t * a, uint32x4_t *v)
@@ -242,7 +242,7 @@ uint32_t* pre_load32_0 (uint32_t * a, uint32x4_t *v)
 /*
 **post_load8_0:
 **	...
-**	vldrb.8	q[0-9]+, \[r0\], #26
+**	vldrb.8	q[0-7], \[r0\], #26
 **	...
 */
 uint8_t* post_load8_0 (uint8_t * a, uint8x16_t *v)
@@ -255,7 +255,7 @@ uint8_t* post_load8_0 (uint8_t * a, uint8x16_t *v)
 /*
 **post_load8_1:
 **	...
-**	vldrb.s16	q[0-9]+, \[r0\], #-1
+**	vldrb.s16	q[0-7], \[r0\], #-1
 **	...
 */
 int8_t* post_load8_1 (int8_t * a, int16x8_t *v)
@@ -268,7 +268,7 @@ int8_t* post_load8_1 (int8_t * a, int16x8_t *v)
 /*
 **post_load8_2:
 **	...
-**	vldrb.8	q[0-9]+, \[r0\], #26
+**	vldrb.8	q[0-7], \[r0\], #26
 **	...
 */
 uint8_t* post_load8_2 (uint8_t * a, uint8x16_t *v)
@@ -281,7 +281,7 @@ uint8_t* post_load8_2 (uint8_t * a, uint8x16_t *v)
 /*
 **post_load8_3:
 **	...
-**	vldrb.s16	q[0-9]+, \[r0\], #-1
+**	vldrb.s16	q[0-7], \[r0\], #-1
 **	...
 */
 int8_t* post_load8_3 (int8_t * a, int16x8_t *v)
@@ -294,7 +294,7 @@ int8_t* post_load8_3 (int8_t * a, int16x8_t *v)
 /*
 **post_loadfp16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0\], #-24
+**	vldrh.16	q[0-7], \[r0\], #-24
 **	...
 */
 float16_t* post_loadfp16_0 (float16_t *a, float16x8_t *v)
@@ -307,7 +307,7 @@ float16_t* post_loadfp16_0 (float16_t *a, float16x8_t *v)
 /*
 **post_load16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0\], #-126
+**	vldrh.16	q[0-7], \[r0\], #-126
 **	...
 */
 uint16_t* post_load16_0 (uint16_t * a, uint16x8_t *v)
@@ -320,7 +320,7 @@ uint16_t* post_load16_0 (uint16_t * a, uint16x8_t *v)
 /*
 **post_load16_1:
 **	...
-**	vldrh.u32	q[0-9]+, \[r0\], #16
+**	vldrh.u32	q[0-7], \[r0\], #16
 **	...
 */
 uint16_t* post_load16_1 (uint16_t * a, uint32x4_t *v)
@@ -333,7 +333,7 @@ uint16_t* post_load16_1 (uint16_t * a, uint32x4_t *v)
 /*
 **post_loadfp32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0\], #4
+**	vldrw.32	q[0-7], \[r0\], #4
 **	...
 */
 float32_t* post_loadfp32_0 (float32_t *a, float32x4_t *v)
@@ -346,7 +346,7 @@ float32_t* post_loadfp32_0 (float32_t *a, float32x4_t *v)
 /*
 **post_load32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0\], #-16
+**	vldrw.32	q[0-7], \[r0\], #-16
 **	...
 */
 int32_t* post_load32_0 (int32_t * a, int32x4_t *v)
diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c b/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c
index 632f5b44f0b..11df1144064 100644
--- a/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c
@@ -7,7 +7,7 @@
 /*
 **off_store8_0:
 **	...
-**	vstrb.8	q0, \[r0, #16\]
+**	vstrb.8	q[0-7], \[r0, #16\]
 **	...
 */
 uint8_t *off_store8_0 (uint8_t * a, uint8x16_t v)
@@ -19,7 +19,7 @@ uint8_t *off_store8_0 (uint8_t * a, uint8x16_t v)
 /*
 **off_store8_1:
 **	...
-**	vstrb.16	q0, \[r0, #-1\]
+**	vstrb.16	q[0-7], \[r0, #-1\]
 **	...
 */
 int8_t *off_store8_1 (int8_t * a, int16x8_t v)
@@ -31,7 +31,7 @@ int8_t *off_store8_1 (int8_t * a, int16x8_t v)
 /*
 **off_store8_2:
 **	...
-**	vstrb.32	q0, \[r0, #-127\]
+**	vstrb.32	q[0-7], \[r0, #-127\]
 **	...
 */
 uint8_t *off_store8_2 (uint8_t * a, uint32x4_t v)
@@ -43,7 +43,7 @@ uint8_t *off_store8_2 (uint8_t * a, uint32x4_t v)
 /*
 **off_store8_3:
 **	...
-**	vstrb.8	q0, \[r0, #127\]
+**	vstrb.8	q[0-7], \[r0, #127\]
 **	...
 */
 int8_t *off_store8_3 (int8_t * a, int8x16_t v)
@@ -55,7 +55,7 @@ int8_t *off_store8_3 (int8_t * a, int8x16_t v)
 /*
 **not_off_store8_0:
 **	...
-**	vstrb.8	q0, \[r[0-9]+\]
+**	vstrb.8	q[0-7], \[r[0-7]+\]
 **	...
 */
 uint8_t *not_off_store8_0 (uint8_t * a, uint8x16_t v)
@@ -67,7 +67,7 @@ uint8_t *not_off_store8_0 (uint8_t * a, uint8x16_t v)
 /*
 **off_storefp16_0:
 **	...
-**	vstrh.16	q0, \[r0, #250\]
+**	vstrh.16	q[0-7], \[r0, #250\]
 **	...
 */
 float16_t *off_storefp16_0 (float16_t *a, float16x8_t v)
@@ -79,7 +79,7 @@ float16_t *off_storefp16_0 (float16_t *a, float16x8_t v)
 /*
 **off_store16_0:
 **	...
-**	vstrh.16	q0, \[r0, #4\]
+**	vstrh.16	q[0-7], \[r0, #4\]
 **	...
 */
 int16_t *off_store16_0 (int16_t * a, int16x8_t v)
@@ -91,7 +91,7 @@ int16_t *off_store16_0 (int16_t * a, int16x8_t v)
 /*
 **off_store16_1:
 **	...
-**	vstrh.32	q0, \[r0, #-254\]
+**	vstrh.32	q[0-7], \[r0, #-254\]
 **	...
 */
 int16_t *off_store16_1 (int16_t * a, int32x4_t v)
@@ -103,7 +103,7 @@ int16_t *off_store16_1 (int16_t * a, int32x4_t v)
 /*
 **not_off_store16_0:
 **	...
-**	vstrh.16	q0, \[r[0-9]+\]
+**	vstrh.16	q[0-7], \[r[0-7]+\]
 **	...
 */
 uint8_t *not_off_store16_0 (uint8_t * a, uint16x8_t v)
@@ -115,7 +115,7 @@ uint8_t *not_off_store16_0 (uint8_t * a, uint16x8_t v)
 /*
 **not_off_store16_1:
 **	...
-**	vstrh.32	q0, \[r[0-9]+\]
+**	vstrh.32	q[0-7], \[r[0-7]+\]
 **	...
 */
 int16_t *not_off_store16_1 (int16_t * a, int32x4_t v)
@@ -127,7 +127,7 @@ int16_t *not_off_store16_1 (int16_t * a, int32x4_t v)
 /*
 **off_storefp32_0:
 **	...
-**	vstrw.32	q0, \[r0, #-412\]
+**	vstrw.32	q[0-7], \[r0, #-412\]
 **	...
 */
 float32_t *off_storefp32_0 (float32_t *a, float32x4_t v)
@@ -139,7 +139,7 @@ float32_t *off_storefp32_0 (float32_t *a, float32x4_t v)
 /*
 **off_store32_0:
 **	...
-**	vstrw.32	q0, \[r0, #-4\]
+**	vstrw.32	q[0-7], \[r0, #-4\]
 **	...
 */
 int32_t *off_store32_0 (int32_t * a, int32x4_t v)
@@ -151,7 +151,7 @@ int32_t *off_store32_0 (int32_t * a, int32x4_t v)
 /*
 **off_store32_1:
 **	...
-**	vstrw.32	q0, \[r0, #508\]
+**	vstrw.32	q[0-7], \[r0, #508\]
 **	...
 */
 uint32_t *off_store32_1 (uint32_t * a, uint32x4_t v)
@@ -163,7 +163,7 @@ uint32_t *off_store32_1 (uint32_t * a, uint32x4_t v)
 /*
 **pre_store8_0:
 **	...
-**	vstrb.8	q[0-9]+, \[r0, #-16\]!
+**	vstrb.8	q[0-7], \[r0, #-16\]!
 **	...
 */
 uint8_t* pre_store8_0 (uint8_t * a, uint8x16_t v)
@@ -176,7 +176,7 @@ uint8_t* pre_store8_0 (uint8_t * a, uint8x16_t v)
 /*
 **pre_store8_1:
 **	...
-**	vstrb.16	q[0-9]+, \[r0, #4\]!
+**	vstrb.16	q[0-7], \[r0, #4\]!
 **	...
 */
 int8_t* pre_store8_1 (int8_t * a, int16x8_t v)
@@ -189,7 +189,7 @@ int8_t* pre_store8_1 (int8_t * a, int16x8_t v)
 /*
 **pre_storefp16_0:
 **	...
-**	vstrh.16	q0, \[r0, #8\]!
+**	vstrh.16	q[0-7], \[r0, #8\]!
 **	...
 */
 float16_t *pre_storefp16_0 (float16_t *a, float16x8_t v)
@@ -202,7 +202,7 @@ float16_t *pre_storefp16_0 (float16_t *a, float16x8_t v)
 /*
 **pre_store16_0:
 **	...
-**	vstrh.16	q[0-9]+, \[r0, #254\]!
+**	vstrh.16	q[0-7], \[r0, #254\]!
 **	...
 */
 uint16_t* pre_store16_0 (uint16_t * a, uint16x8_t v)
@@ -215,7 +215,7 @@ uint16_t* pre_store16_0 (uint16_t * a, uint16x8_t v)
 /*
 **pre_store16_1:
 **	...
-**	vstrh.32	q[0-9]+, \[r0, #-52\]!
+**	vstrh.32	q[0-7], \[r0, #-52\]!
 **	...
 */
 int16_t* pre_store16_1 (int16_t * a, int32x4_t v)
@@ -228,7 +228,7 @@ int16_t* pre_store16_1 (int16_t * a, int32x4_t v)
 /*
 **pre_storefp32_0:
 **	...
-**	vstrw.32	q0, \[r0, #-4\]!
+**	vstrw.32	q[0-7], \[r0, #-4\]!
 **	...
 */
 float32_t *pre_storefp32_0 (float32_t *a, float32x4_t v)
@@ -241,7 +241,7 @@ float32_t *pre_storefp32_0 (float32_t *a, float32x4_t v)
 /*
 **pre_store32_0:
 **	...
-**	vstrw.32	q[0-9]+, \[r0, #4\]!
+**	vstrw.32	q[0-7], \[r0, #4\]!
 **	...
 */
 int32_t* pre_store32_0 (int32_t * a, int32x4_t v)
@@ -255,7 +255,7 @@ int32_t* pre_store32_0 (int32_t * a, int32x4_t v)
 /*
 **post_store8_0:
 **	...
-**	vstrb.8	q[0-9]+, \[r0\], #-26
+**	vstrb.8	q[0-7], \[r0\], #-26
 **	...
 */
 int8_t* post_store8_0 (int8_t * a, int8x16_t v)
@@ -268,7 +268,7 @@ int8_t* post_store8_0 (int8_t * a, int8x16_t v)
 /*
 **post_store8_1:
 **	...
-**	vstrb.16	q[0-9]+, \[r0\], #1
+**	vstrb.16	q[0-7], \[r0\], #1
 **	...
 */
 uint8_t* post_store8_1 (uint8_t * a, uint16x8_t v)
@@ -281,7 +281,7 @@ uint8_t* post_store8_1 (uint8_t * a, uint16x8_t v)
 /*
 **post_store8_2:
 **	...
-**	vstrb.8	q[0-9]+, \[r0\], #-26
+**	vstrb.8	q[0-7], \[r0\], #-26
 **	...
 */
 int8_t* post_store8_2 (int8_t * a, int8x16_t v)
@@ -294,7 +294,7 @@ int8_t* post_store8_2 (int8_t * a, int8x16_t v)
 /*
 **post_store8_3:
 **	...
-**	vstrb.16	q[0-9]+, \[r0\], #7
+**	vstrb.16	q[0-7], \[r0\], #7
 **	...
 */
 uint8_t* post_store8_3 (uint8_t * a, uint16x8_t v)
@@ -307,7 +307,7 @@ uint8_t* post_store8_3 (uint8_t * a, uint16x8_t v)
 /*
 **post_storefp16_0:
 **	...
-**	vstrh.16	q[0-9]+, \[r0\], #-16
+**	vstrh.16	q[0-7], \[r0\], #-16
 **	...
 */
 float16_t *post_storefp16_0 (float16_t *a, float16x8_t v)
@@ -320,7 +320,7 @@ float16_t *post_storefp16_0 (float16_t *a, float16x8_t v)
 /*
 **post_store16_0:
 **	...
-**	vstrh.16	q[0-9]+, \[r0\], #126
+**	vstrh.16	q[0-7], \[r0\], #126
 **	...
 */
 int16_t* post_store16_0 (int16_t * a, int16x8_t v)
@@ -333,7 +333,7 @@ int16_t* post_store16_0 (int16_t * a, int16x8_t v)
 /*
 **post_store16_1:
 **	...
-**	vstrh.32	q[0-9]+, \[r0\], #-16
+**	vstrh.32	q[0-7], \[r0\], #-16
 **	...
 */
 uint16_t* post_store16_1 (uint16_t * a, uint32x4_t v)
@@ -346,7 +346,7 @@ uint16_t* post_store16_1 (uint16_t * a, uint32x4_t v)
 /*
 **post_storefp32_0:
 **	...
-**	vstrw.32	q[0-9]+, \[r0\], #-16
+**	vstrw.32	q[0-7], \[r0\], #-16
 **	...
 */
 float32_t* post_storefp32_0 (float32_t * a, float32x4_t v)
@@ -359,7 +359,7 @@ float32_t* post_storefp32_0 (float32_t * a, float32x4_t v)
 /*
 **post_store32_0:
 **	...
-**	vstrw.32	q[0-9]+, \[r0\], #16
+**	vstrw.32	q[0-7], \[r0\], #16
 **	...
 */
 int32_t* post_store32_0 (int32_t * a, int32x4_t v)

commit 537b7a344626ff8a77f1c8fb6626eaf6d5d36277
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Mon Jan 30 17:30:12 2023

    arm: [MVE] Add missing length=8 attribute
    
    I have noticed that the "length" "8" attribute is missing in a few
    patterns in mve.md.
    
            gcc/
            * config/arm/mve.md (mve_vabavq_p_<supf><mode>): Add length
            attribute.
            (mve_vqshluq_m_n_s<mode>): Likewise.
            (mve_vshlq_m_<supf><mode>): Likewise.
            (mve_vsriq_m_n_<supf><mode>): Likewise.
            (mve_vsubq_m_<supf><mode>): Likewise.
    
    (cherry picked from commit 330d665ce6dcc63ed0bd78d807e69bbfc55255b6)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 6e2bac55599..78d1472e024 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -4972,7 +4972,7 @@
   "TARGET_HAVE_MVE"
   "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
   [(set_attr "type" "mve_move")
-])
+   (set_attr "length" "8")])
 
 ;;
 ;; [vqshluq_m_n_s])
@@ -4988,7 +4988,8 @@
   ]
   "TARGET_HAVE_MVE"
   "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vshlq_m_s, vshlq_m_u])
@@ -5004,7 +5005,8 @@
   ]
   "TARGET_HAVE_MVE"
   "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vsriq_m_n_s, vsriq_m_n_u])
@@ -5020,7 +5022,8 @@
   ]
   "TARGET_HAVE_MVE"
   "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vsubq_m_u, vsubq_m_s])
@@ -5036,7 +5039,8 @@
   ]
   "TARGET_HAVE_MVE"
   "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])

commit c2dbbfbd9b118bfa26217d3de19d23c973300310
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Thu Dec 1 15:42:52 2022

    arm: fix mve intrinsics scan body tests for C++
    
    Hi all,
    
    this patch is to export the functions defined in these MVE tests as C
    so the body scan assembler works as expected also for our C++ tests.
    
    Best Regards and sorry for the regression!
    
      Andrea
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Extern functions
            as "C".
            * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
    
    (cherry picked from commit 8d4f007398bc3f8fea812fb8cff4d7d0556d12f1)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
index 843d022c418..3b95fb140f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int16x8_t b, int16x8_t c, mve_pred16_t p)
   return vabavq_p (1, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
index 6ed9b9ac1c4..b9f84e581bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int32x4_t b, int32x4_t c, mve_pred16_t p)
   return vabavq_p (1, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
index ec34be92a28..fa76cd20e1b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int8x16_t b, int8x16_t c, mve_pred16_t p)
   return vabavq_p (1, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
index 440b603a18e..93deb664eda 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t b, uint16x8_t c, mve_pred16_t p)
   return vabavq_p (1, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
index 9500ee054b1..c11fc704b34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
   return vabavq_p (1, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
index 40c9a51fbe4..04b9a6e2e35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t b, uint8x16_t c, mve_pred16_t p)
   return vabavq_p (1, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
index 27684fa4a88..d1a1c967581 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int16x8_t b, int16x8_t c)
   return vabavq (1, b, c);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
index f595609a2a0..9ccfc73f79c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int32x4_t b, int32x4_t c)
   return vabavq (1, b, c);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
index 60fa9e23b7b..5184d7a068d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int8x16_t b, int8x16_t c)
   return vabavq (1, b, c);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
index f3255276eda..c800d79d351 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t b, uint16x8_t c)
   return vabavq (1, b, c);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
index f41fa1f3952..b1733bae333 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t b, uint32x4_t c)
   return vabavq (1, b, c);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
index 3a2654435df..897cd32b1bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t b, uint8x16_t c)
   return vabavq (1, b, c);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
index f379b25c49e..338514621ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
index 3ba808e0b4d..9a600384822 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
index 903c6dfe861..3584f182e9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
index 4ddf4ee5c61..8b64f39a758 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
index c719a0b5e9c..aeb9879f91c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
index 048554144cd..294c6f17467 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
index 458b920b5cb..c4c414691cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
index 8e163edb153..4567b0f7da8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
index 619d4706dc5..fc58f5c9001 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
index 079478df08a..6c5e2fe479a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vabdq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
index 0dce4c482ac..ac300d287dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
index f5908fe81d8..6170a59c0b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
index 3f249e1a622..9cf62f9742d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
index 16a4b930d2c..c283d7482cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
index 2b5ee12945c..be9abda0cab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
index 50a4c162c9b..227af07d0e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vabdq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
index da142f4394b..ae54ef21c3e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
index 1ff1bef258f..d8781db3fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
index 6733e2bcc14..9d141616047 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
index 8d7631b9ac6..7eb6fad3499 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
index 90784c1d389..8431703f4ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
index f376374564a..7d2f3dcea48 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
index d9467a1ccd7..b94358fb4ae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
index 1ea3713d12b..a88e1e5346f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vabdq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
index f29ada8c058..d4bc9110f38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a)
   return vabsq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
index cc24744fb26..9f2955829f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a)
   return vabsq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
index 21cf284d045..33d113241e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
   return vabsq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
index 236830b3a9e..a588f5fc94c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
   return vabsq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
index 22f7b37b30b..360087db4e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
   return vabsq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
index b3021edf52b..590d0204385 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
   return vabsq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
index da9ff2f978a..518c19fdf79 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
   return vabsq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
index 84906302c8a..6f40447eb1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a)
   return vabsq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
index 117c787d595..3da8b740fc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a)
   return vabsq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
index a7f1413505c..5fa4ce42f5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a)
   return vabsq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
index f24a8cccb53..fda43efcf96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, mve_pred16_t p)
   return vabsq_x (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
index fd4c2277969..281e07468ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, mve_pred16_t p)
   return vabsq_x (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
index 0e1d1bb94d4..93d4ff5a473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, mve_pred16_t p)
   return vabsq_x (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
index 64d0e4b574d..1ddc8b81cf6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, mve_pred16_t p)
   return vabsq_x (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
index 742bc701fae..0dfcf3e62fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, mve_pred16_t p)
   return vabsq_x (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
index 3a9504df94e..174f3e3b958 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64_t a, int32x4_t b, mve_pred16_t p)
   return vaddlvaq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
index 6e2613ee099..41b93675b74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t b, mve_pred16_t p)
   return vaddlvaq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
index 180dc9b2deb..d692df30d55 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int64_t a, int32x4_t b)
   return vaddlvaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
index 1f899e92c3c..4daba29620c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t b)
   return vaddlvaq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
index 5b22da49c1d..df71bf107b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, mve_pred16_t p)
   return vaddlvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
index 2c85139435a..40d6f4c1082 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, mve_pred16_t p)
   return vaddlvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
index bdb04b5214f..4c87fb6dd2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a)
   return vaddlvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
index bcd9d21df4f..3a9037addbb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a)
   return vaddlvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
index 58462177473..b0e6d5d2c59 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
index f3fcd286f4d..be459e68d3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
index 291e65f32cc..1631969a87f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
index 0346f65a330..bd00b2056a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
index 9d57bbd27b9..5622365dd96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
   return vaddq_m (inactive, a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
index 9939aa0012d..e8bdb6a6a98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
   return vaddq_m (inactive, a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
index 50b138fc763..b1c41e2b3bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
index 66c2be777ce..1ff3dff685a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
index 87dba75dff1..3c7ed0f8e3e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
index a8e9ea576b3..a8e7b989ba9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
   return vaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
index 045e5024d5d..0cbc89d37d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
   return vaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
index 3d17afcbe56..db95f28d548 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
   return vaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
index 87210a41dae..4306e61b57b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
index 1acb0b67fa9..fad289c8a41 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
index 6136c54cbb8..0b39c3dce21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
index b60d98e0691..c7a846a2dba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
index d56bbae9b03..bbead6073ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
index 9f0b623c3e8..3097756d53e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
index 5df23a6e61f..dbb86b7083c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t a)
   return vaddq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
index d07927c427e..61cbe4d03cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t a)
   return vaddq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
index 9ae30406f51..237838cb0e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
index 3271d4d5af1..c2cee5dc69b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
index 119fd5d5528..d815eaaa16e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
index ef0722e4dcd..35527a63ef4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t a)
   return vaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
index 67513819f39..66de687bef0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t a)
   return vaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
index 2aa79e5e916..9d4f8073810 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t a)
   return vaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
index 24b12a6aee1..370e4332e65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
index 3fdfa3d86e6..8c3bd3316d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
index 6b32b8ccfd5..3d126df3c3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
index 0deefa14ac6..e8ed91457b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
index 44df963f0f8..172ed24016a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
index 7349fa165bf..b60b877bdba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
index b1d48a1d260..e7a3693f4a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
index 047043d6526..f38c6b1f7af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
index ed67007df51..e092b28afa8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vaddq_x (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
index fa17d6b4aa2..c58a5e50608 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vaddq_x (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
index d6c3252132a..876afc7367b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
index c2a861706d9..c25ec006918 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
index abc90a4c86b..b6389224fe6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
index 8866a07bc8e..006a872034a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vaddq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
index 4123ad594ed..0cc940b449c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vaddq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
index d610930a311..214a8decd83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vaddq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
index 323010a6d33..a79531abf14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
index 98773e7ba6f..019ed62813c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
index bff0bda1109..4f390d109dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
index 85f5cd4db7a..e528a9ef1bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
index ad0e7afbc39..fa622f0a520 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
index a3cfc5686e2..8ce1fe36015 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
index 16b51514be1..95224809f66 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t a, int16x8_t b, mve_pred16_t p)
   return vaddvaq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
index bbf04aa0d08..80281819f06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
   return vaddvaq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
index f06623b1893..53a92513511 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t a, int8x16_t b, mve_pred16_t p)
   return vaddvaq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
index 7bfb4bb9cbe..da61820c552 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t b, mve_pred16_t p)
   return vaddvaq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
index 9aea5caa4fe..0b7892c8b9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t b, mve_pred16_t p)
   return vaddvaq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
index b5113b209c0..51cba0385a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t b, mve_pred16_t p)
   return vaddvaq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
index 1b9af185a0d..2a4dd6c33d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t a, int16x8_t b)
   return vaddvaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
index e25487954d2..9f1c8515142 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t a, int32x4_t b)
   return vaddvaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
index d37c916c94d..6f77cdb46f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t a, int8x16_t b)
   return vaddvaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
index b3583ce5725..a3e0e39502f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t b)
   return vaddvaq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
index 006c0a3734f..e6b2f85cdae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t b)
   return vaddvaq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
index cfe29bfd7be..5bad0ca996e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t b)
   return vaddvaq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
index 3d19b46fdc6..f4e499b631e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, mve_pred16_t p)
   return vaddvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
index a148d15ead1..9417d86d6fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, mve_pred16_t p)
   return vaddvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
index f0b0c499d0d..757bc5759ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, mve_pred16_t p)
   return vaddvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
index 2fb316c50ab..cc9673f7326 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, mve_pred16_t p)
   return vaddvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
index 24bde90ec77..9ead886d3e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, mve_pred16_t p)
   return vaddvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
index f6710941119..45ed62f8b58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, mve_pred16_t p)
   return vaddvq_p (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
index 6b9a99f2b07..468cc810cc4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a)
   return vaddvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
index 50823b65ecc..791e27bdbb5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a)
   return vaddvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
index 131edbe2b3f..3a13efc93dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a)
   return vaddvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
index 7c0ac0e1395..6aabcdce2c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a)
   return vaddvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
index 40779ed0f99..8b5ba816623 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a)
   return vaddvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
index d2a6ba8f0fb..2576d9c66d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a)
   return vaddvq (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
index de9fe5e7d01..373acbd31b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vcmpcsq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
index 04df1b2dc61..25263654930 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vcmpcsq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
index 34ebadca248..60120e88ef9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vcmpcsq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
index bc03bf687de..fcdc41fdc81 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vcmpcsq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
index 8e216d49a02..b294c8593d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vcmpcsq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
index ac4196a2e48..00c118a68c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vcmpcsq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
index 6038f4c8c65..dc63c527743 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint16x8_t a)
   return vcmpcsq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
index 9f39aa761c8..8c5d185ca22 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint32x4_t a)
   return vcmpcsq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
index 0ce2cd13a7b..2296f3e1655 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint8x16_t a)
   return vcmpcsq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
index 5598d06875c..5ae4d0ceaef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vcmpcsq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
index 99b232b05dd..4695e7e3405 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vcmpcsq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
index 571e57135ab..3075050a943 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vcmpcsq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
index 57b276a1d4c..82b24a83f8b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
index ab1b25e2888..1d7bda0a986 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
index c5587884d0e..0a0406b3b74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
index 4e9675fff51..ba8a946591c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
index a3cae828e79..f095b4aff1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vcmpeqq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
index a7ce9e0c7e3..dd244db5e46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vcmpeqq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
index 7ba481e169f..bbf5326d2b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
index 13c88eaabb5..b66949b7633 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
index dcf276dee44..5730eebb47b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
index d59d5149a30..6009e951beb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vcmpeqq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
index 1fbf385d030..2bce70de33e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vcmpeqq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
index 92758c98c9a..6c6fa8a7720 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vcmpeqq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
index 1ea35ed924b..4b5feb26a62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
index a9bc9733842..60db456c60d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
index a9fe771a101..45cdc28fb2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
index 826901874d7..41c3653b892 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
index 512b7f9c889..2e7bf175e63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
index 01b4507ba63..e9d333f6661 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vcmpeqq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
index cf2812558ff..1d870428c55 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float16x8_t a)
   return vcmpeqq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
index 13817174282..8b8610b0617 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float32x4_t a)
   return vcmpeqq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
index bd29828492e..2f146d937ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
index 2a0d84e9b51..f77743c00d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
index 524bbe9f3cb..690ed1b811d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
index 3eeaa49aa97..409c9de58ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint16x8_t a)
   return vcmpeqq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
index a881bb841af..c3b1736bfa1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint32x4_t a)
   return vcmpeqq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
index 429b2e35eb7..3728c738b54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint8x16_t a)
   return vcmpeqq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
index 92a87c08773..24f34a24ee3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
index d3b87d59bfa..ae5d870d2b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
index 2b71bbf75f6..81538a9957a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
index 1830b667bb6..39778cf1b6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
index 2b2a5f920f3..8afd39e89b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
index 9450c203394..84610a10445 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vcmpeqq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
index fd8bcab4f25..f11dc28376d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
index a2d50b580e7..8eb38db2021 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
index a631825fadd..c3a8df2ec46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
index b94e0738ef0..8069e426b73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
index 9f4903d9cfd..3a9be99bc0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vcmpgeq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
index 679e644f165..a785cfb52f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vcmpgeq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
index 45e26d0a77b..0a2544e7ac4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
index 3a6cad921f2..fa453774d06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
index ce1ca30d6ea..34d632b03e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
index 51587a38b72..1c5ce785a63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
index 3ff0aaaa414..3ac4d59bf1f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
index df71ee57945..3c3a584e075 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vcmpgeq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
index 2ca1b9d6684..4e9a346ab14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float16x8_t a)
   return vcmpgeq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
index 3af110bd2b2..2cf1d1ab0b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float32x4_t a)
   return vcmpgeq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
index 3c1af8a93ab..e0488dc0003 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
index 8b4e0f426e5..b448e8a15e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
index c1669bcdd90..9f609b9f243 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
index 593c7410dcb..c835d99b47a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
index 9e26ea9938a..37d9524b4f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
index 3cb2832e159..a752510621b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vcmpgeq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
index 8835fe08dba..d8f151a19f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
index e1470884708..6f601889e85 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
index cb9d5f4036f..f724387023e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
index b249b831782..6eebe92b797 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
index b375983f01e..be4da4b50da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vcmpgtq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
index 208a285cb39..e8244345eb2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vcmpgtq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
index 248e3093d2a..12d5540ba39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
index 9843288296e..dca726fde38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
index 80f1aa9ead0..07216ac242f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
index 9289c00b5af..bd0ac3d927a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
index 8a3d7606bb7..0c2f3acf2bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
index 2760795eb86..3f2f28b839b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vcmpgtq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
index 9f2a4be319a..0339fbcafc6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float16x8_t a)
   return vcmpgtq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
index bbf18ebe6e7..482ac094cf3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float32x4_t a)
   return vcmpgtq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
index d833cb6f58e..9c8611d924c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
index 28cd51b9582..ef285c9692b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
index 5a953ca55f4..8cabf987c9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
index b9c9da486f5..da107d414b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
index 0f79385358e..4508698a856 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
index f59dad94a57..d65d27704d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vcmpgtq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
index 136a2e44259..403ad11fee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vcmphiq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
index 5640b97afaf..a9c9816976d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vcmphiq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
index e6474e45487..16e3af1d556 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vcmphiq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
index 38b9b90c803..139f69e392b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vcmphiq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
index 97c8c1dfe05..a33aed0a005 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vcmphiq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
index e2024ccda25..18e9b1907b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vcmphiq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
index 36107fc7b8d..085b8277736 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint16x8_t a)
   return vcmphiq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
index d34de8f65c7..a62a73ff24c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint32x4_t a)
   return vcmphiq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
index 93a05b1a857..f05c9d24643 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint8x16_t a)
   return vcmphiq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
index 40e65dc52f4..3cff050425d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vcmphiq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
index d87a4185762..39f0c12a75b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vcmphiq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
index 80fd2a40b0f..69103f502f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vcmphiq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
index 209d81096af..fb92b67325f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
index b92c5f66fd9..61ab55d83da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
index e6136898ded..f866469eadb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
index 2304e98d253..5704e6d7a0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
index a61db2817c1..5fa3be11c2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vcmpleq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
index 7a2cdb4059d..cbab9606b3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vcmpleq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
index 69fcab15b8a..d16b5c49e83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
index 617ebd6144f..e9504fad271 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
index b8ee50dd55c..10709a8520c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
index fcc376d6ec3..59102a6eb60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
index 9983e89d80c..42d7d7fdbb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
index 504e4feb5d1..3d1407baebf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vcmpleq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
index cfa6dbc07c7..4f6276484ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float16x8_t a)
   return vcmpleq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
index c89558f4076..e71dcb8f174 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float32x4_t a)
   return vcmpleq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
index da73fc14b77..6aad8de937a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
index 0951a5c13fb..fedc87fa318 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
index e4553354681..066dd808771 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
index 68500da9ddf..00872c3503c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
index 1966bcd94d3..8f595a0d24b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
index e9f6e47e5d6..a827b9b6f5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vcmpleq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
index b4958816bd8..15855e1bbed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
index 752ab2b3e49..d11c9e2f1e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
index cbaacbe2b47..efb525cacce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
index 96d0e7c7cc6..6c788202199 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
index 1e5db53198e..2b29d72bbf6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vcmpltq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
index 77de40ade01..0c89d2982e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vcmpltq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
index beebe65a58f..34984fa7772 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
index 07260c56ed3..bb7c0a26bf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
index 7d1e9e7fbde..035ce454073 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
index c0f6dfc9432..9776a4a64e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
index b6fc4700e73..6a7459806ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
index 545b76359ad..ca08e1dadf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vcmpltq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
index 401ef21ba2b..c6fdb08d8ae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float16x8_t a)
   return vcmpltq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
index 380f071e564..4f1ac3c0977 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float32x4_t a)
   return vcmpltq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
index a1d12392dd2..4c9d1d3d887 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
index 6332f75f327..632c4aeca13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
index e0ac80caeb0..1eabc2e70bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
index 23843ad88f3..85117199a90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
index aeb7a6f9896..11379cf7ff8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
index 2129b56a5f7..686ccd8eedb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vcmpltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
index c27ea2f0de8..20d722ca649 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
index 609de44d8e7..1e4dcde89b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
index 98f22337d61..bafb7e8a956 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
index 7f6e96ae47e..168633d05c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
index 71b3476fb18..3b7951f4ee1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vcmpneq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
index d6dea8db865..47b972cdeeb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vcmpneq_m (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
index e72c9b62829..b16c6445942 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
index 47c90e31f49..2f8057050f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
index 9d9da100046..4637bd10d2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
index ea8cf24b358..90b23531f49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vcmpneq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
index 30291dcdd9b..c8b0c952730 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vcmpneq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
index be75376a691..d458b9ad15b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -60,4 +64,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vcmpneq_m (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
index 60e868141d0..ea83993bd72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
index 780c544bef3..817060f8d73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
index 15f6d316cba..9c0473d228e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
index 300852ed7b3..4f10b5a787e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
index 227b5f01eca..ba440459d5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
index cfcb59f49cf..ffe091bd082 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vcmpneq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
index 29e43f3fdf8..e36d8a95a85 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float16x8_t a)
   return vcmpneq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
index 688e77cd044..7262503eee6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (float32x4_t a)
   return vcmpneq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
index 2afc34d16e5..2e39b66b34c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
index 6c323161316..9471935d96f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
index 5483d6dd2fe..7d3d4ddd2c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
index d8edfb0d825..71d878dff9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint16x8_t a)
   return vcmpneq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
index 2b7a6b56830..3f997e8e487 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint32x4_t a)
   return vcmpneq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
index 2dab43af331..9917a95ffb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -48,4 +52,8 @@ foo2 (uint8x16_t a)
   return vcmpneq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
index d57b607baa9..a3b0572c011 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
index e02171f6686..c6bf6ca82d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
index 0abef8c3e00..99b343b0427 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
index 7144f3ee2fc..d676d9b3c22 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
index a31134f2f1d..56c39968035 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
index 2801c8e3763..f906574d5e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -34,4 +38,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vcmpneq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
index c39303daa03..0458bb1bb7c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_f16 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
index ad66f4407cd..af782b5ac53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_f32 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
index 7e70a486513..8a3e91843f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_s16 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
index ffcfc80ff40..5e385dfeee0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_s32 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
index 26642f9cd68..df901680c2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_s64 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
index 7e7e4d5948d..e853395af0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_s8 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
index 858a3a4546f..bf4a137bb43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_u16 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
index 5f27cf68845..efb58ddff8b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_u32 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
index 78553dec701..91dd885dce1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_u64 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
index 4a8ab61f865..d5d001158ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -31,4 +35,8 @@ foo1 ()
   return vcreateq_u8 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
index 7c8b0152763..86e6e0ed5c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return vddupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
index 810a1a7e21b..c5aa5323edc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return vddupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
index 6642b9f4b88..e326a00062f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return vddupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
index cc6a19516d9..2a907417b40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return vddupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
index cd6c6f86eea..ffaf3734923 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return vddupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
index fe186e743da..ae7a4e25fe2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return vddupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
index 2dba2d74b61..dbaf372e446 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vddupq_u16 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
index 6b5cf6c75b0..cf932541023 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vddupq_u32 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
index 174e422f4ef..60088880776 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vddupq_u8 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
index 6a471a7f72f..6c54e325155 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vddupq_u16 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
index debf420d3e8..a8de90f7b12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vddupq_u32 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
index 8e6ef8adccd..5a90e069b1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vddupq_u8 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
index 1aafaf87b82..12e13ad5af7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vddupq_x_u16 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
index 2e3e268dbee..ebe7270f28d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vddupq_x_u32 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
index bdf563a8074..d53d45fc852 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vddupq_x_u8 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
index 713d8b731c8..dab65e08320 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vddupq_x_u16 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
index 9f484b3b8fb..c7abcaef942 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vddupq_x_u32 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
index aa83bfed125..d2c299d4e3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vddupq_x_u8 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
index bfa471bcb31..df7438bf0a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t inactive, mve_pred16_t p)
   return vdupq_m (inactive, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
index e1dd8f58ad0..6397b902705 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t inactive, mve_pred16_t p)
   return vdupq_m (inactive, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
index 52304ace03a..bf05c73fc1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16_t a, mve_pred16_t p)
   return vdupq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
index 44a80c5d5bc..71789bb620e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32_t a, mve_pred16_t p)
   return vdupq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
index 1630a3b9234..48c4fbd1f82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8_t a, mve_pred16_t p)
   return vdupq_m (inactive, a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
index d3df8b69248..511be48ebae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return vdupq_m (inactive, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
index e6bb0cc2c38..f3a2c25f5ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return vdupq_m (inactive, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
index ad6f6d04ae3..a99d8f3d86b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return vdupq_m (inactive, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
index fc5a7933653..44112190fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -29,4 +33,8 @@ foo1 ()
   return vdupq_n_f16 (1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
index a6be82e5927..059e3e42dd0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -29,4 +33,8 @@ foo1 ()
   return vdupq_n_f32 (1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
index f842b96c3b1..d8ba299cb15 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -17,4 +21,8 @@ foo (int16_t a)
   return vdupq_n_s16 (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
index 05cbff8fdae..a81c6d1e220 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -17,4 +21,8 @@ foo (int32_t a)
   return vdupq_n_s32 (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
index 1d141161604..b0bac4fce89 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -17,4 +21,8 @@ foo (int8_t a)
   return vdupq_n_s8 (a);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
index 4839d427e65..55e0a601110 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -29,4 +33,8 @@ foo1 ()
   return vdupq_n_u16 (1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
index f0069eb7280..bf73bc17fc7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -29,4 +33,8 @@ foo1 ()
   return vdupq_n_u32 (1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
index fe26687ae45..48cbdb2a1da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -29,4 +33,8 @@ foo1 ()
   return vdupq_n_u8 (1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
index 11ebb47f94f..7821e365293 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -37,4 +41,8 @@ foo1 (mve_pred16_t p)
   return vdupq_x_n_f16 (1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
index 4e79bd54f71..af82b3ebdbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -37,4 +41,8 @@ foo1 (mve_pred16_t p)
   return vdupq_x_n_f32 (1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
index 90288777df7..6756502ab21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -21,4 +25,8 @@ foo (int16_t a, mve_pred16_t p)
   return vdupq_x_n_s16 (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
index c4c906e0682..b04afb3834b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -21,4 +25,8 @@ foo (int32_t a, mve_pred16_t p)
   return vdupq_x_n_s32 (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
index 6234730827e..b23facd5e94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -21,4 +25,8 @@ foo (int8_t a, mve_pred16_t p)
   return vdupq_x_n_s8 (a, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
index 821fcddcab1..62dc42c6eae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -37,4 +41,8 @@ foo1 (mve_pred16_t p)
   return vdupq_x_n_u16 (1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
index 20125df6226..098fdfbd233 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -37,4 +41,8 @@ foo1 (mve_pred16_t p)
   return vdupq_x_n_u32 (1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
index defaaeebfcf..02a4253e74a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -37,4 +41,8 @@ foo1 (mve_pred16_t p)
   return vdupq_x_n_u8 (1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
index 8f53f5ef0cb..dc4dbb9f432 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return vdwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
index 30e971fb733..edfc4c464be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return vdwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
index 0abc19a2318..009048fdb05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return vdwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
index b3e6affbf8f..b24e7a2f5af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return vdwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
index 60c52b0d850..75c41450a38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return vdwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
index 459321a7984..90d64671dcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return vdwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
index 9f76dbf35eb..6235b1422b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vdwdupq_u16 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
index 962f766b496..b6ce427015a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vdwdupq_u32 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
index c73b1b69661..bec1eb5165d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vdwdupq_u8 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
index 3b1968d78aa..87af2b6817a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vdwdupq_u16 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
index 8554f62ee6b..ec136dc3222 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vdwdupq_u32 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
index eb91a80daf5..3653d00bc5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vdwdupq_u8 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
index 9c0fd1e253c..e9ef2df77c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vdwdupq_x_u16 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
index 3107e2fdbbe..6cc1582c22b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vdwdupq_x_u32 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
index 03d01e0dd43..3216d250aa4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vdwdupq_x_u8 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
index f7dca660c03..e9d994ccfc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vdwdupq_x_u16 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
index 032ae94e8c3..07438b02351 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vdwdupq_x_u32 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
index 5d238a7a865..96280225351 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vdwdupq_x_u8 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
index 03b376c9bbe..7f427bd6140 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p)
   return vfmasq_m (m1, m2, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
index ecf30ba9826..99a106982fa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p)
   return vfmasq_m (m1, m2, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
index 0bd03832ff5..dbcc3b3aec2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
index 42fe35dc746..134409e8f09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
index 1f4a4016c74..fb295f2d245 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
index 7d7ebebd638..2ed1262e5ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
   return vhaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
index 31f7ee2fa54..852fe64cf8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
   return vhaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
index 2120472af46..5700f7ec818 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
   return vhaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
index 4b4ce40efb8..fce31dada68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
index e532055c675..dbc1b835482 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
index 25b81629ec3..32e6bebf8ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
index 4a9e9f3f438..d824bd3d39a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
index 1e68099ebf2..5f033d255f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
index 6dd75d7336e..f3ea63f75b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vhaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
index 6390589808f..0f9eb59646f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
index db09d0f2c21..5b41bf193b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
index 89ea3f2aaf8..48e88781ce3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
index e6fb8be673b..3d7314673b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
   return vhsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
index 7ab815d5623..f6509a5472e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
   return vhsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
index 0bf695aded4..db75b389138 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
   return vhsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
index 3bad177ad28..d8f3f3c9504 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
index cc5cdb07059..94252c80324 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
index 4c651091e59..d4f6c247503 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
index daed202c055..a921ba6ab51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
index cf71e6dab13..73a544f9147 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
index a8183dd48ed..fd2aa22de0e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vhsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
index b4ee7af36e3..397be9f3e1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return vidupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
index b13a7a80dcb..02b38cc6415 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return vidupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
index b731002724a..f44aa21f324 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return vidupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
index 0e2ad6a2b55..19d04601809 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return vidupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
index 786a05eee35..36a8ac30564 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return vidupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
index 3fcc3ba0d67..75695304c65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return vidupq_m (inactive, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
index a6ffdc05ce5..6b5d8815e1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vidupq_u16 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
index 8cd43e38255..0b829a43a10 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vidupq_u32 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
index 4005eabb45d..12523757737 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vidupq_u8 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
index 3ad89c0536c..83d9cc2a563 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vidupq_u16 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
index 45eb1b09a5b..d73face505d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vidupq_u32 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
index beb0aae67a9..75187b0eb25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return vidupq_u8 (1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
index 74cd4310213..5df5035e340 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vidupq_x_u16 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
index 3111b1a54e6..02c6d7784dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vidupq_x_u32 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
index 5bedb4f9e79..3a1d3c0317f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vidupq_x_u8 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
index caf334fa32f..31ddde4bd3a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vidupq_x_u16 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
index 11895e303cf..c8193465a72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vidupq_x_u32 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
index b951d4cfe94..f7a628990c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return vidupq_x_u8 (1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
index 67a2465f435..d96a89017e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return viwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
index 9fc2518acc5..ca1ac6ebe24 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return viwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
index 39f4071bfa1..9590e023335 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return viwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
index 8bb680e0d77..84733f94e7c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, mve_pred16_t p)
   return viwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
index 2dc8d5f3442..a175744b654 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, mve_pred16_t p)
   return viwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
index ff3a5f520e8..7240b6e72bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, mve_pred16_t p)
   return viwdupq_m (inactive, 1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
index 5f37290759a..a5eb3094d44 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return viwdupq_u16 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
index de93f8a7ec4..63f6bdf52b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return viwdupq_u32 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
index 089025c3401..65d1062ac96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return viwdupq_u8 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
index fc3e9c6fac4..eaa496bb2da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return viwdupq_u16 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
index 4c098dd8f02..c1912d77486 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return viwdupq_u32 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
index 44cb53fe344..f0d66a9ba29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 ()
   return viwdupq_u8 (1, 1, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
index 2242877881f..7f8cc38e4c2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return viwdupq_x_u16 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
index 4b2b650e21a..f97b599373c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return viwdupq_x_u32 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
index 873952b6c2e..c0ceead5267 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return viwdupq_x_u8 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
index b6c94797380..265aef42c92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return viwdupq_x_u16 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
index 5fd84963d01..585e41075db 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return viwdupq_x_u32 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
index abbb40fa8da..ca39081dfc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (mve_pred16_t p)
   return viwdupq_x_u8 (1, 1, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
index 4c487ed7f60..6d011177c21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
   return vmaxaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
index 5156467f0c1..f8f960af752 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
   return vmaxaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
index 6564bd88c9b..69313d5ecc3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
   return vmaxaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
index 6cabf9f723b..aefe76a63e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, int16x8_t b)
   return vmaxaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
index d0dd3c23600..f5e018e3be5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, int32x4_t b)
   return vmaxaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
index a7344638dcf..186b92a3d2f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, int8x16_t b)
   return vmaxaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
index ac81c8fd1bd..10478e9d97b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int16x8_t b, mve_pred16_t p)
   return vmaxavq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
index 119c0c34c76..d43afbce273 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int32x4_t b, mve_pred16_t p)
   return vmaxavq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
index dfd7f828ef6..beb34db720c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int8x16_t b, mve_pred16_t p)
   return vmaxavq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
index 9f59e8e4542..b997f308963 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int16x8_t b)
   return vmaxavq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
index 716b8a2a979..e969f572bd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int32x4_t b)
   return vmaxavq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
index 0f1a87af54b..e668c378a03 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int8x16_t b)
   return vmaxavq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
index cd4c813bf3b..1f6902e952c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vmaxnmaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
index 527466fc131..dc79d1bf14b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vmaxnmaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
index 39c68cdc172..aa6d3a5f2a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vmaxnmaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
index f6f8bf07549..8637c6efa7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vmaxnmaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
index 4c1f20be036..7e3708cc5cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t b)
   return vmaxnmavq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
index 86087335cea..5f63fa52a1c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t b)
   return vmaxnmavq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
index a4973567d5e..1cc89f89a27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t b, mve_pred16_t p)
   return vmaxnmavq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
index b229cb3a322..339be113753 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t b, mve_pred16_t p)
   return vmaxnmavq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
index faf968ebb21..2c2ac3c4edd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vmaxnmq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
index f7ee01b1f14..18f4f0817ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vmaxnmq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
index ee3444393ed..5cf0d72b8af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vmaxnmq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
index 5d434432856..4a10383bb3b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vmaxnmq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
index dad76734fd8..c52bfce7425 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vmaxnmq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
index 2fe8c0d4f3d..a940a08691d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vmaxnmq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
index 9787cc1ba90..d2a67445849 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t b)
   return vmaxnmvq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
index b1191876850..b56620693e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t b)
   return vmaxnmvq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
index 0b1740d5ed2..9c4df6b2642 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t b, mve_pred16_t p)
   return vmaxnmvq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
index ca6ad91d24d..fa4b5830679 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t b, mve_pred16_t p)
   return vmaxnmvq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
index 548824fc58a..5ae4d8addb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vmaxq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
index e935729b47d..6963a987176 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vmaxq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
index 8028fa031c7..e7064300952 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vmaxq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
index e872f9e72f8..41117d46b25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vmaxq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
index 76606555881..9ce6f831785 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vmaxq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
index 7ade467cafd..fcd90fb6f90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vmaxq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
index bf547a2420d..7c532dcac7b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vmaxq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
index 25bb950c0bf..e8e3a4eeb0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vmaxq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
index 33057f1a58e..ad529c03d8f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vmaxq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
index 7717a9a5057..04d8c64fdd3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vmaxq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
index 36b5c276cfe..d68ae2b43cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vmaxq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
index e643e5f3e3c..944353ef2d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vmaxq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
index a32feb0d7cd..843a4cc4a70 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vmaxq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
index 3ac1994c4f8..ff81a393f3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vmaxq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
index c9ba33d1504..68563747f3b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vmaxq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
index 954a9e2f02a..85c21e6ab1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vmaxq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
index 022d418af84..b45d7bd3ea4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vmaxq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
index 7e1687a8b72..de8b2d4a48c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vmaxq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
index a97703eb58c..ac29f91bdf2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16_t a, int16x8_t b, mve_pred16_t p)
   return vmaxvq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
index b4bddcb8312..4290484f847 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
   return vmaxvq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
index ee8c3e9155f..6a9b1cedf0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8_t a, int8x16_t b, mve_pred16_t p)
   return vmaxvq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
index 906adf85936..3cc1dbb0bbd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t b, mve_pred16_t p)
   return vmaxvq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
index acc5367c5a2..99264f3a2b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t b, mve_pred16_t p)
   return vmaxvq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
index 358cb40f829..6aac76b8798 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t b, mve_pred16_t p)
   return vmaxvq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
index 485355a7d72..18938d86396 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16_t a, int16x8_t b)
   return vmaxvq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
index 3b9075689a0..26ee10b0c27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t a, int32x4_t b)
   return vmaxvq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
index f13a0168d9d..b5bbfc3bd11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8_t a, int8x16_t b)
   return vmaxvq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
index 6a0fe254043..f806cfa7e36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t b)
   return vmaxvq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
index eed20046e53..b46dc06611f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t b)
   return vmaxvq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
index d44a6d3bb02..1a64f5528c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t b)
   return vmaxvq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
index 925b9154ca7..50a98bf0780 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
   return vminaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
index 296f69dfcda..3870cf5226a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
   return vminaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
index cf6fecc3461..74a3122b18f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
   return vminaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
index 63f59f8c80a..f78ee9de4f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, int16x8_t b)
   return vminaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
index eb0a54cbe19..cbe18e05e26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, int32x4_t b)
   return vminaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
index b875308863d..e8030958284 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, int8x16_t b)
   return vminaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
index 5d3c40fb1fc..ff77b8e72c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int16x8_t b, mve_pred16_t p)
   return vminavq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
index ee4ff251d63..4c1433d67f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int32x4_t b, mve_pred16_t p)
   return vminavq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
index 14602c29719..ef923f8d022 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (int8x16_t b, mve_pred16_t p)
   return vminavq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
index 51f75ae1f6a..3f66002e46c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int16x8_t b)
   return vminavq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
index d1602cebe18..69daa328374 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int32x4_t b)
   return vminavq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
index f4c9b045b90..95fb6cf51b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (int8x16_t b)
   return vminavq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
index 1728d104266..19c736cd318 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vminnmaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
index 42b4265d9cc..8dc7ea9a72d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vminnmaq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
index 51b85bd2b04..c57b3842a31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vminnmaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
index 2f0423ecb4f..8c51328c148 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vminnmaq_m (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
index 17e4ad16759..79503f2b212 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t b)
   return vminnmavq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
index 2758e59666e..34dd9ddbb17 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t b)
   return vminnmavq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
index b60a6627aea..ae7931fc966 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t b, mve_pred16_t p)
   return vminnmavq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
index 6fa97b74a65..2d6aad6bc51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t b, mve_pred16_t p)
   return vminnmavq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
index c0962b52631..251d35e9c6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vminnmq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
index a9c3e5f74b1..7d77e215823 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vminnmq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
index 466264249c5..fb741991a41 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vminnmq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
index 57edc8e1a80..fa3c47c23de 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vminnmq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
index 73b4ccba080..632dcaa9dbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vminnmq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
index 9a824566212..5c290687e60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vminnmq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
index dc00d02df7d..2ef50208def 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t b)
   return vminnmvq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
index ff23c818452..1a65fca220a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t b)
   return vminnmvq (1.1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
index ad99f586d11..8cb61904dfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t b, mve_pred16_t p)
   return vminnmvq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
index 3c7e5c07a68..93bad1ec334 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t b, mve_pred16_t p)
   return vminnmvq_p (1.1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
index fe7368eeb38..1b3bbe163fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vminq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
index a90a1db8835..b45cc91f79b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vminq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
index 911bd3af0dc..fa7c43bb392 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vminq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
index f80288aaf79..65dbf136d27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vminq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
index b480089f4f3..256ee84ee40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vminq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
index 73633c9612e..9399ac4ab83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vminq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
index eb34dc4c41c..8d3a948ec51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vminq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
index 60d29da4e14..51970d67d5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vminq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
index 675fb8edfb1..d5e671fe3b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vminq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
index 50f648d5133..ade8c016637 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vminq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
index bcfead39c5a..bb15d1b4575 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vminq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
index e8eacae4da8..ff9b23288eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vminq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
index 0d8987e16b8..6ae37c58b64 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vminq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
index 3c3595171ea..395907dc7ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vminq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
index 402c4aa121d..16f6ef3cd66 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vminq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
index e27a3416e38..c25dc747801 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vminq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
index d3cb29bf60c..bf2764d6ac0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vminq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
index 3e05ef7dd13..f4a35535f68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vminq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
index 7c25c9d2f82..6562d6ae757 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16_t a, int16x8_t b, mve_pred16_t p)
   return vminvq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
index d5f7418af38..6e3715e3ef3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
   return vminvq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
index 6a42170fc19..dc06d0f5e7e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8_t a, int8x16_t b, mve_pred16_t p)
   return vminvq_p (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
index 8f2f68fef84..16cc419fce2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t b, mve_pred16_t p)
   return vminvq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
index 9d14c39c1dc..bef29dc40e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t b, mve_pred16_t p)
   return vminvq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
index 4c1f4406852..42beaee1d45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t b, mve_pred16_t p)
   return vminvq_p (1, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
index e3242c0aa4d..9fc314d2573 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16_t a, int16x8_t b)
   return vminvq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
index 1325b38411d..3546b69e9a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t a, int32x4_t b)
   return vminvq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
index 81c14a8ac6b..e512a7df254 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8_t a, int8x16_t b)
   return vminvq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
index 4372ac62388..29746c3184a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t b)
   return vminvq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
index aff3679f49d..d12764ddfa7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t b)
   return vminvq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
index 883e5f2d2c7..60175116e9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t b)
   return vminvq (1, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
index f3e5eba3b08..258adfa989d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
   return vmladavaq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
index 71f6957bfc5..78d3333a9fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
   return vmladavaq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
index a74317aeff9..1529e9466f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
   return vmladavaq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
index 9ac84d46a07..3266c3a6d1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
   return vmladavaq_p (1, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
index 4a3d109ed90..a555e5f3fb0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
   return vmladavaq_p (1, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
index a17440f4675..4f9596f4958 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
   return vmladavaq_p (1, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c
index a45ea90b60f..9f7c0eeb04f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c)
+foo (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaq_s16 (a, b, c);
+  return vmladavaq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c
index 6533addcfaf..012a06988e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c)
+foo (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaq_s32 (a, b, c);
+  return vmladavaq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c
index 6fed506e7c4..f41230f3ac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c)
+foo (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaq_s8 (a, b, c);
+  return vmladavaq_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c
index 3c5f689ba92..62a3c0e5027 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint16x8_t b, uint16x8_t c)
+foo (uint32_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavaq_u16 (a, b, c);
+  return vmladavaq_u16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint16x8_t b, uint16x8_t c)
+foo1 (uint32_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmladava.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+  return vmladavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c
index 6172f82aaaa..a186953d9dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint32x4_t b, uint32x4_t c)
+foo (uint32_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavaq_u32 (a, b, c);
+  return vmladavaq_u32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint32x4_t b, uint32x4_t c)
+foo1 (uint32_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmladava.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+  return vmladavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c
index 2aff5552053..0df91990ead 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint8x16_t b, uint8x16_t c)
+foo (uint32_t add, uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavaq_u8 (a, b, c);
+  return vmladavaq_u8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint8x16_t b, uint8x16_t c)
+foo1 (uint32_t add, uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmladava.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t m1, uint8x16_t m2)
+{
+  return vmladavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
index 87f0354a636..11e32c76d5a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
   return vmlaldavaxq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
index d26bf5b90af..937fab4166c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
   return vmlaldavaxq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
index 3a37e7a58a9..4f10ec7d098 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
   return vmlaldavaxq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
index 155b8be70f0..1d78a7cd269 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
   return vmlaldavaxq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
index af6e588adad..83af9bb4355 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
   return vmlasq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
index 9d0cc3076d9..f6bf6444bdd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
   return vmlasq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
index 772ad8b1e76..021fc0373a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
   return vmlasq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
index b02dc64a31b..1b478da34da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
   return vmlasq_m (m1, m2, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
index 0214cf2136e..99fc605d1b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
   return vmlasq_m (m1, m2, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
index c9824e332f7..43128266673 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
   return vmlasq_m (m1, m2, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
index 6708a741790..0ab8e9f431f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
   return vmlasq (m1, m2, add);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
index 4e8bf32e016..88f1dc53682 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
   return vmlasq (m1, m2, add);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
index 1cb1a31459c..a5cb99ebf50 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
   return vmlasq (m1, m2, add);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
index e03c91ef298..f455fc10146 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t m1, uint16x8_t m2)
   return vmlasq (m1, m2, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
index b80c3c7631f..561b4f7a24e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t m1, uint32x4_t m2)
   return vmlasq (m1, m2, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
index 0f37550160e..414cba1fba8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t m1, uint8x16_t m2)
   return vmlasq (m1, m2, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
index 9251809bfa1..3c9b82deed5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
index 3dacb7ad77c..adebaee5f00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
index 8f47e962633..4737ac3c75b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
index 41f3786e5fe..2c09a9ee90a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
index 2f4fecbf56b..8de0d38f97c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
   return vmulq_m (inactive, a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
index 2ad4108d637..36e9aa99b33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
   return vmulq_m (inactive, a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
index b10bd5af687..163d4259338 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
index e8bdf7278ad..89e4c212147 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
index 001e888e075..4055959ec8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
index 5015f20a4be..2ea47a6df96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
   return vmulq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
index a6013a42721..c818c4556d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
   return vmulq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
index 42fc7264229..d0380864af6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
   return vmulq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
index 04fdc010f5b..72f5d3cefc3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
index 96178d02e37..2ee86e9e163 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
index aa3b8061122..6356f4adce0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
index e56ab77f3ee..903bccbf0ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
index 72e313cfd78..8d386c0727a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
index 1ae6a93934c..de3f6096fa4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vmulq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
index d77aeb219ca..e4efd6b279f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t a)
   return vmulq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
index 9ef6a21b2bd..97c71ab0a2c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t a)
   return vmulq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
index 7ea25dce4a7..c2f3c1df51c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
index b884603ac5b..50b5f0c0ccb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
index 8e6e17cd593..425b576caf7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
index 907bb0a4009..1e02ad0077c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t a)
   return vmulq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
index 1164b29fc76..6a05f542a37 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t a)
   return vmulq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
index ccc950e3ccf..7ba29e6a482 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t a)
   return vmulq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
index a1fc1fc8f04..026bbaecc9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
index 4fcf0dd88d1..75a17e07cf0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
index d0c147ef912..a7762893e93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
index d4a24ba95b6..4150c390fab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
index c9194b73eaf..3bdc5df35c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
index d69402021ec..dc988fd9b4a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vmulq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
index 169871b47d8..bde0536d9cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
index f800731b3ff..162569cbad4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
index a4dc47725b5..b37a9ae7411 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vmulq_x (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
index e8428fe9b2d..a2be895bea5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vmulq_x (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
index 27ef55d932a..70e169975c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
index 929f420bd4c..4e3e2320c10 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
index 31885a2d90f..a7a2cca4e59 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
index 5972a525092..76b8a7e0f11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vmulq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
index 3e02a542988..cba98561403 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vmulq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
index 9b59b189a5f..33836662b2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vmulq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
index 09b7169a68b..a1a60030a2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
index a57ef2da840..f3a2917bd45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
index 7fb5e007990..cdd311d41a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
index 7b1c6b2acc8..c8d4eed010e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
index bc53faff33f..497e542f9ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
index f43760861d4..e54b95f5ee4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vmulq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
index a659373d441..8884a7c8318 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
index 8ffc6a67762..77d4b36b94c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
index 2e88b7fabac..943fae8657f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
index 61cf9fcf2aa..b8808066322 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
   return vqaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
index bbd255ac1f1..b9815bd5ca3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
   return vqaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
index 9cee8c65333..674d0c578ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
   return vqaddq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
index 8bb8a957423..ce1cedd7e1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
index 9959724fc11..9b6717ef8f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
index 6b918978880..46ce20b7cae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
index c0a8d9ba9c8..ed1ffbf8721 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
index 7a72ce57840..50450ff3361 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
index f7e6ca9b5a4..a260e96a95d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vqaddq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
index 94d93874542..42b3e25fc3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
   return vqdmlahq_m (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
index a3dab7fa02e..03e50f14e00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
   return vqdmlahq_m (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
index 610580478a3..d7f8a153c63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
   return vqdmlahq_m (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
index a5c1a106205..17c43c4e4b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vqdmulhq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
index c78d4db1591..62e7988f107 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vqdmulhq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
index b5ab6eb292c..3bd8b4f9632 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vqdmulhq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
index 2f5fb0e53a4..b1efee53278 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vqdmulhq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
index 80a938a8a5b..3492c17c3fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vqdmulhq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
index bfb755af4ee..41118e0dcda 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vqdmulhq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
index e34689d203d..dfff38bf59b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vqdmulhq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
index f967b8a286a..ac0812b438d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vqdmulhq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
index 5e1928fd51b..db8db5cb855 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vqdmulhq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
index 7c0a434e48f..e8927845ab4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vqdmulhq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
index 19f4b03f6f0..c15c8e29273 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vqdmulhq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
index 1784c967f3c..1f7a556e1fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vqdmulhq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
index 4f96e192732..57ad651188c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vqdmullbq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
index d0bca6e3015..c7153b35cef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vqdmullbq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
index 8448cdc88cf..d7abff0b3f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vqdmullbq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
index 48cddcd791e..503cd27735a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vqdmullbq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
index cd7c394139d..31a3a244355 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vqdmullbq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
index b4d82f55987..dbc07187165 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vqdmullbq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
index 6f0fdabf67f..7d5fd25a1e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vqdmullbq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
index 2bf952bfd77..503b1751250 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vqdmullbq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
index 6c756ebf3e7..a36afd8a3a5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vqdmulltq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
index e46f6b2c384..fdbbfee27ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vqdmulltq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
index 8526b3ad628..f5d5c6ce04e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vqdmulltq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
index 809e0740e46..91dad0e506d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vqdmulltq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
index 44f0036bc51..e4f09d0f45c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vqdmulltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
index b025886ff15..80694b686c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vqdmulltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
index 95084876349..4f8b1eef4bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vqdmulltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
index ab27aeddc29..e3ebacc4f36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vqdmulltq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
index 07d689279ac..304f86c6e51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
   return vqrdmlahq_m (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
index 3b02ca16038..265fecaf806 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
   return vqrdmlahq_m (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
index b661bdcb4cf..d1687f79311 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
   return vqrdmlahq_m (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
index 16804735b32..4595d55711e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
   return vqrdmlahq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
index d7d3dc06d7f..22d9ce56a35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
   return vqrdmlahq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
index d3f9f25f11c..36a23ad2078 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
   return vqrdmlahq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
index da4d724bb46..2995682f252 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
   return vqrdmlashq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
index 2430f1cb102..7e637e6900f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
   return vqrdmlashq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
index 30915b24e5e..d81472d933a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
   return vqrdmlashq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
index 39b8089919d..a64b6649938 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
index ed6b92ddcf5..350629cf234 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
index c69ed2aeb84..e5fa4c486bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
index 57ba7428bef..734ac2da8f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
   return vqsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
index eda9e74309d..f54aec8dd00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
   return vqsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
index f6f61b52f52..c96a8398bad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
   return vqsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
index 1a8ea29e83e..bd6a05e858d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
index c49b7497f6d..baa9e9f192c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
index 17d6471bcd9..746001d0efa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
index 0ce93fdf9be..ed504fe3817 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
index 1eac57545b3..508b54ff41f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
index 56bdda2da6e..5cfb2c58940 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vqsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
index b9a46f5ff6f..a4407cc802f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
index 732e6c01b78..80634f0a797 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
index fb3c4404fba..172609a94e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
index aa09d1831e0..0a95d0ab3ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t a)
   return vqsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
index 19b62e3a8a5..9964ea66ee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t a)
   return vqsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
index c8eeb38b266..b28a93ffd00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t a)
   return vqsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
index 6c66b4d75d8..1c5edd730ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
index 8432197b9e8..a7b6c07fb4b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
index ad16cae08bc..92676fdca4f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
index 264df1a0398..0b816c6b765 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
index a4bf15cd9df..565508db865 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
index 1804d6484e2..cca60ff7247 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vqsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
index dec4a969dfe..2134e3fc0dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
   return vrmlaldavhaq_p (a, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
index f3c8bfd121c..4ebd337e8ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
   return vrmlaldavhaq_p (1, b, c, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
index 09cd9ee99ff..2efde824eb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
index 1d6f64e0879..745655f31d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavha.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b, uint32x4_t c)
 {
   return vrmlaldavhaq_u32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavha.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
 {
   return vrmlaldavhaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vrmlaldavha.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b, uint32x4_t c)
+{
+  return vrmlaldavhaq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
index c7d1f3a5b1c..4c064515f0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
   return vrshlq_m_n (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
index a8713e6a06a..2c9c15b13b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vrshlq_m_n (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
index 8160d1bdb04..48c394e21e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
   return vrshlq_m_n (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
index b08f4c076d1..2fe162b7051 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
   return vrshlq_m_n (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
index 59f9a13d8c0..49ccaf81c0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
   return vrshlq_m_n (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
index fda65f7c592..df2f38f9cd2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
   return vrshlq_m_n (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
index 20c9f5fcd7c..0cb1511f778 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vrshlq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
index af7a5158458..52872e30d8d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vrshlq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
index 59d283ebb71..887f3fd8ef8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vrshlq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
index e731cb71675..9f55d180efb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
   return vrshlq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
index 0379e0455c9..f52e9d474c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
   return vrshlq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
index 1e20486253e..7241e3174c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
   return vrshlq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
index c846e9f06ee..feceb6dae9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int32_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
index 1c6144212f7..4fe4e4fe209 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
index 3b9d0a389dc..fc8fd2d3bee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int32_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
index 77994bd3a29..7d3a77a1928 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, int32_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
index 82774c794fe..e5d688a67c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, int32_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
index e9badb7297e..9f594e9cbce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, int32_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
index 4a64fc7b410..facb0c957a5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
index c5cbe266c0f..d30d987eeb0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
index 85305921f9a..52d1f41e5fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
index 905a18c4f20..b729151774c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, int16x8_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
index 16c7578df39..12b46421e69 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, int32x4_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
index 8bf21eeaef5..37b9194a6a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, int8x16_t b)
   return vrshlq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
index 4dfb6a65842..b813647839c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vrshlq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
index 7f1f6dbb760..d06d0f93b10 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vrshlq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
index 69bf0a50fa6..0d1d8858e54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vrshlq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
index b5a89892070..ae050e4cda3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
   return vrshlq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
index 59ab2662021..00a2edc55d4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
   return vrshlq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
index b81d8d03da4..1172a62d0b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
   return vrshlq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
index 3d82b081ca2..5114f9f6e85 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float16x8_t a, float16x8_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
index d0f64bb9872..d0524ba6196 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (float32x4_t a, float32x4_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
index 434b0a7ced8..e8536dc51f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
index 0b8e056647e..eca850b63b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
index abbd60060a7..1753d6c8045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
   return vsubq_m (inactive, a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
index 40ca4284a1f..056810f4b06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
   return vsubq_m (inactive, a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
index f13eff8ad2d..a55ed63d635 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
index 21ba17ba869..480fed3a112 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
index c75b8b5420d..9aaa540a990 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
index 700bc01833c..5d033129356 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
   return vsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
index 25dd37ae5b2..3f9494005cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
   return vsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
index 4fed154d258..c6ee8887e62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
   return vsubq_m (inactive, a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
index dde77dc51b7..cfd43b07258 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
index 8770e31ad95..6c382ba6f45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
index c9813313594..0408dd0e2c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
index eebc3ad6929..9d860e9b224 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
index d85bbec7ebf..c409b0a9d58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
index a104a74e259..7d568c17173 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vsubq_m (inactive, a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
index 4db52649ab4..3c31189e52e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t a)
   return vsubq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
index fe97eed7d37..041266b3b7d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t a)
   return vsubq (a, 1.1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
index d695fc83e06..78a2b911c97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
index c281e21ab0c..98ab34e89d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
index ef36b4d6330..07173eaa1ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
index be754d894a8..f0744f5c501 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t a)
   return vsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
index ef0aaa4cf08..600d6290cde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t a)
   return vsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
index c55aefc3307..34d4725b27b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t a)
   return vsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
index 469395452bd..80213e828e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
index 0e60e1c6f60..262ec5ce5c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
index 882d63dfcf7..9a2d55f1307 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
index fe9baf3d52c..62a5942396d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
index b82051d69d5..3c824b0fb75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
index 630b2f79f1f..c9c7f6ca085 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
index c48bea7e9f0..cb233e9897c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
index d3e129bb6ee..227e9349206 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
index 2dcaff58c09..14574d5074e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float16x8_t a, mve_pred16_t p)
   return vsubq_x (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
index 92bafa3c4cc..864f6fee264 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (float32x4_t a, mve_pred16_t p)
   return vsubq_x (a, 1.1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
index f01e8d7d490..ee9e7bcb45f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
index 506966424cc..551f46c92ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
index 3c4a5d8129c..04a9d7285c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
index 958e5aa2ce8..a07d4955224 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vsubq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
index ba39c75bb2b..1055769ee1f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vsubq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
index 19204d1d80f..a67d303107a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vsubq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
index 8dcc5477c6f..9bf363275cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
index a2d43323227..19707f684ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
index 8ead3d22439..ef4d831a117 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
index f0faf8165d2..6c3d6697c92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
index 67a70931859..97f9f744f2f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
index 19002336cbd..75e75e5d028 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 4036a318fc9ec66604cca5566d45fd7fe11f87cc
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:01:26 2022

    arm: improve tests and fix vclsq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vclsq_s<mode>): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks. Use extern
            "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise.
    
    (cherry picked from commit dd4424ef898608321b60610c4f3c98737ace3680)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 78d1472e024..9ad26c963c1 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -462,7 +462,7 @@
 	 VCLSQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vcls.s%#<V_sz_elem>  %q0, %q1"
+  "vcls.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c
index d0eb7008537..1996ac8b03e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclsq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c
index b6d7088a8e7..f51841d024e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclsq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c
index 28d4d966802..2975c4cda56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclsq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c
index e57fbb97080..ed1b5c75b40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcls.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vclsq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcls.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vclsq (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c
index 7fa3038d361..9e5369e04c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcls.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vclsq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcls.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vclsq (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c
index b0985484d1d..c4a9468f8e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcls.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vclsq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcls.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vclsq (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c
index ab09c9944ae..ea11eceb730 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vclsq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vclsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c
index 09a8dab2f51..1737c561a0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vclsq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vclsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c
index af40f7fa510..a7cdb612ee1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vclsq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vclsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit a47749ddad831939c177fdd005fe5e6ce9f4499a
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:04:41 2022

    arm: improve tests and fix vclzq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (@mve_vclzq_s<mode>): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise.
            * gcc.target/arm/simd/mve-vclz.c: Update test.
    
    (cherry picked from commit 16452c63e10f7a44c70bec0216358ac405abfcf6)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 9ad26c963c1..b6615f24103 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -441,7 +441,7 @@
 	(clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vclz.i%#<V_sz_elem>  %q0, %q1"
+  "vclz.i%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 (define_expand "mve_vclzq_u<mode>"
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c
index 9670f8f56f3..620314e4ff2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclzq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c
index 18427354570..dfda1e67287 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclzq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c
index 2697d039d70..1300fe6f8c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclzq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c
index 8405b16314c..922819d388e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c
index 350e6e7e661..6e75a0463cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_m_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c
index d455526f975..3c450e8eca0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c
index f71a0a4eded..17be53f395b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vclzq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vclzq (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c
index 46a002bc1c5..5e440febb29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vclzq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vclzq (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c
index 3cab6f32310..9eaa9a4269a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vclzq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vclzq (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c
index cada68b6d65..37179b22a5c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vclzq_u16 (a);
+  return vclzq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vclzq (a);
+  return vclzq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c
index 0291b0cea4c..65ee44d41d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-    return vclzq_u32 (a);
+  return vclzq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-    return vclzq (a);
+  return vclzq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c
index 5eb7bab5e0d..bed4ab1878a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vclzq_u8 (a);
+  return vclzq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vclzq (a);
+  return vclzq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c
index daddd1b4421..ea78bf20066 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vclzq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c
index d4f443f7f56..cc85d4d27e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vclzq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c
index b33d2c51c3f..0f809167a4f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vclzq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c
index 6d9bc79261b..a9b662d40f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c
index c3b053b9f1f..5446938c3fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_x_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c
index 678b2eb898d..548a74e8367 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c b/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c
index 7068736bc28..38e91fc5bce 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c
@@ -23,6 +23,6 @@ FUNC(u, uint, 8, clz)
 
 /* 16 and 8-bit versions are not vectorized because they need pack/unpack
    patterns since __builtin_clz uses 32-bit parameter and return value.  */
-/* { dg-final { scan-assembler-times {vclz\.i32  q[0-9]+, q[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {vclz\.i16  q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times {vclz\.i8  q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vclz\.i32\tq[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vclz\.i16\tq[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vclz\.i8\tq[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */

commit cb444c6df76b786b445163751e803281f62c61ce
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:09:16 2022

    arm: improve tests and fix vnegq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vnegq_f<mode>, mve_vnegq_s<mode>):
            Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise.
            * gcc.target/arm/simd/mve-vneg.c: Update test.
            * gcc.target/arm/simd/mve-vshr.c: Likewise
    
    (cherry picked from commit c8cb7e062664e5db5969de4239be513dfd6ab1d1)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index b6615f24103..3a1db782203 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -245,7 +245,7 @@
 	(neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vneg.f%#<V_sz_elem>  %q0, %q1"
+  "vneg.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -394,7 +394,7 @@
 	(neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vneg.s%#<V_sz_elem>  %q0, %q1"
+  "vneg.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
index 9572c140d7e..9853cf6e6dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vnegq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vneg.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vnegq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
index be73cc0c5f5..489cfc760ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vnegq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vneg.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vnegq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
index 0d917b80cd7..c8b307ea50e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vnegq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
index f1c0e9a99b0..a530a05e644 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vnegq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
index 9a945ee62a3..46d6e794dbe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vnegq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
index 811f1df0565..5fb1f5c2a4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vnegq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
index 430ebc73783..868a9680858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vnegq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
index a47f9b3423e..3b518c8e0f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vnegq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vnegq (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
index 50401f53bd7..f8682575892 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vnegq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vnegq (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
index fd5de3dab56..1be5901740e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vnegq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vnegq (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
index e7af36691dc..c10d6d2aebf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vnegq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
index d9c3818855a..0ee5ecc8262 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vnegq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
index 16f1fa452ce..d774a055d72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vnegq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
index d74683c6f24..77bf1a67cfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vnegq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
index eda4c7fcf7e..ca44512e37a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vnegq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
index 7945a060e25..1379cae579f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
@@ -45,8 +45,8 @@ FUNC(f, float, 16, 8, -, vneg)
 
 /* MVE has only 128-bit vectors, so we can vectorize only half of the
    functions above.  */
-/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {vneg.f[0-9]+  q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vneg.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-not {orr\tr[0-9]+, r[0-9]+, r[0-9]+} } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
index d4258e9fefe..8c7adef9ed8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
@@ -58,7 +58,7 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
 /* Vector right shifts use vneg and left shifts.  */
 /* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
-/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */
 
 
 /* Shift by immediate.  */

commit 4fdbf8cb806575df6e6c8f249ab2e778bee70899
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:11:01 2022

    arm: improve tests for vmulhq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise.
    
    (cherry picked from commit 6c61fac9016891c5444be859b080872ce96b63cf)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c
index 4971869a27b..a7d8460c265 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c
index 3006de7fd24..997fdbe8d23 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c
index fbcef24ffc3..567461ff111 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c
index 7059fecf047..9b813829cd6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c
index 1c2de7081cf..248432a2fe0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c
index 5eed85fb2d9..464180c1988 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c
index a7260df0f51..0950c06ee05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c
index 4fe46e62fc8..db2ab42a1e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c
index acc08039bb5..8bb2239005f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c
index 37e40f06d72..bb88136589c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulhq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c
index 5673d91486c..d42c41acb73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmulhq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c
index 29c6312bb7c..c666a9631af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulhq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c
index b783570be19..a323c961838 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c
index 003485be70b..98168b1be06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c
index d2359cd371b..b50f59b3df4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c
index c052c4ac007..afa803c2917 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c
index 7eeba8be611..221795478cd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c
index ff2a53fc160..4383e2e7574 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit b821e3502632ef6fb2e136ca80c00a14101983c5
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:12:08 2022

    arm: improve tests for vmullbq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise.
    
    (cherry picked from commit e6f52130d0db50ca3f59e45676db9431fa44457c)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c
index be933274d77..a4cc5e52773 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c
index 3dfc26761be..a195884567b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c
index f8c449b28a0..3a5d7705d45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c
index dd6ed6b71a6..5e327d25a9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c
index 85ce75e7dd8..fb2de994dd8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c
index d131a5d9fd7..4cc06c4ef28 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c
index 22f4d27f6cc..16c0982386b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmullbq_int_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c
index 6e677f26b84..e0a82d6e640 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmullbq_int_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c
index f40b8a6c4dd..031a433c2bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmullbq_int_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c
index 3529ab2772d..4bb19bf5cff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_int_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c
index d843d2bf5fe..d461ed9f9c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmullbq_int_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c
index 6268c463ead..c0790778b2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_int_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c
index 87f8e21a7d0..ee83ca61158 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c
index 5e563728a4a..42ae3324cd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c
index b2ca4134ee5..8dcf9b726b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c
index 15269101fe5..31330da9a93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c
index 7a7836303ec..b882d644347 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c
index f422a3c66f0..4b402374eb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c
index 527acb74e09..2efb87dff01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m_p16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c
index 5403394e870..b435f44cb32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m_p8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c
index d01d5997ff4..bfd052222fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_poly_p16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c
index de97134add7..a2a53e8a3dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_poly_p8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c
index f94d9052433..bee45f95939 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x_p16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c
index 6fdc94496bc..7cd15f3a7f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x_p8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 99bcb2f22e3d45aeba2bf582d53307408b8ecbf2
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:14:13 2022

    arm: improve tests for vmulltq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise.
    
    (cherry picked from commit 59d46d5ba0bf81a7431c0bae1ad8d1024249be47)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c
index 25ecf7a2c51..7f573e9109e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c
index f8d02880ea0..da440dd1365 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c
index 3f2fc333a65..ceb8e1d5a94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c
index b7ab408d53c..a751546ae13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c
index e43ad98d933..a6c4d272968 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c
index 7f4b90b08dd..1a7466bb5b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c
index 34b75d4abc8..cd907f6224c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmulltq_int_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c
index 7e09bf93e0e..dbc4c80b440 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmulltq_int_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c
index b6eb1f5e7f2..0fef6a21207 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmulltq_int_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c
index f4fc9c0c634..91b6fb4595d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_int_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c
index d1bc3a8f990..71c62a12afb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmulltq_int_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c
index 87f3c4e386a..7506adce33e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_int_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c
index c13ef50147e..c2376abe268 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c
index e82321ecb79..788789db120 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c
index 7f093c26080..3935741d041 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c
index d0f6461448b..32ee5b2e4e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c
index 55e19cb204a..cc3105650a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c
index 650c9471c7e..01713fba245 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c
index 944db4c2fab..6d368e2ba68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m_p16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c
index d07311943c2..75b8811fdd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m_p8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c
index 121de8e9c0e..9f08d57eef9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_poly_p16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c
index c7d9548a8ab..59e6e1bb6e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_poly_p8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c
index fb4b849b8b0..f3d3de2d1d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x_p16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c
index 1e79b2987c9..2c7a6294540 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x_p8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 633a203732f52443d314d0519ff3571641866b88
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:33:58 2022

    arm: improve tests for vcaddq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise.
    
    (cherry picked from commit 6764c13b14b036e70da28b0245c1299aecc061a9)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c
index b50a5d54bb2..fb83a1cd8fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot270_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c
index 0a12ff6fdcf..f8341a74e4a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot270_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c
index e78bbd5446c..b4e2ffda280 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c
index 8b53c665463..e7adc1be243 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c
index 61948bb3552..fdde2f56b20 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c
index 0bbe24b3b4a..1cb6afb4e4d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c
index e9cab3df37f..39f063970f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c
index 25c71257920..fd285288487 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c
index ee437eeb41f..053a61197d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c
index 419ba7e98ee..869983a0a0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c
index 832be006af8..67b0d0a4d0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot270_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c
index dbebe22183c..ab28458130e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot270_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c
index 5f7852f69d4..842d6adf96d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot270_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c
index 80b6c0ff3a9..97773d8daa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot270_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c
index 260c5b81e22..17d5c147295 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot270_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c
index ae9c4f436ad..faf01a18824 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot270_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c
index 4b99c638830..f35aaf01a59 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c
index 2532ef7d535..6446d9edc42 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c
index 676efa8cfd7..b92fd2ee8aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c
index 9aa05d5bfdf..b8acc67feb9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c
index 4532296494c..78ec7862574 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c
index 51db9379e9b..ea781622424 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c
index a2e51c13268..a43d806ac3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c
index 6ae7f693664..eb9cf0cffb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c
index e1b21e6c5c3..1e78bd144b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot90_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c
index 118489e923f..9611f8938dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot90_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c
index e47e242f061..58608b4961e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c
index 833aa9c2367..125dbe5405c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c
index 46babedb949..38e0e47b500 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c
index 15774e5a142..455d8388f0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c
index 6f2bb4da3e3..7217dadaac0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c
index b9113fe4f39..d3edbaa478c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c
index b7fe5106414..eb1bf2a4274 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c
index e6c4e9f66fb..3343399b2c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c
index 8279da9ed45..134fba6280f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot90_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c
index 6d59da7757d..b8e81679e9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot90_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c
index b4f5a22c03e..2a37b8e7b83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot90_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c
index e203bd017cd..51e1871b690 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot90_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c
index 0cba5d5bda8..5905062064a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot90_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c
index f4f0476427a..37374637eb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot90_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c
index 476648ad459..4223c4d0f33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c
index ae9a196af7f..9e67c56b5e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c
index 16b5949a2a2..553fc2801fb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c
index d30150e0f1c..1cd7338d162 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c
index fa79ce24eaf..13373d46154 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c
index e18a39ed125..3f8957783e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c
index b9b95fe360e..34cb0363574 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c
index b8b8978c1e6..d383404052d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 455461dfccc0747c4731c4f69d8ae3a353cd9798
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:34:41 2022

    arm: improve tests for vcmlaq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise.
    
    (cherry picked from commit 0ea30b2a83c908323d73309b6f698331607eb2e0)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c
index fa7d0c05e8c..bb8a99790a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c
index 166bf421f14..71ec4b8479c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c
index 0929f5a0a89..3db345d0791 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c
index 1f4ba453cbc..dcbd2dccce5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c
index fc6ba30b36a..f76ae2383a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot180_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot180 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c
index dbe3f26b3b9..c97d0d0d852 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot180_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot180 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c
index 84a3bd81ad9..132cdf9954f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c
index 61f5716f0b7..99e96ebe3a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c
index 1b0bef91f37..fae85105feb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot270_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot270 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c
index 83e15025e44..54a9b662772 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot270_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot270 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c
index 6e033b1d7ab..e34f83165c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c
index 4928341076d..cdba91b8e8c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c
index 16744a4582c..f767b2b6e6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot90_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot90 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c
index f1f19a87ba7..6c9b24f271d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot90_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot90 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c
index 7133ddc7ad5..9141c9e6f90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c
index 6022e3be538..f317d411806 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 6171e0b1701e580800eded08844e6f1d02af55da
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:35:24 2022

    arm: improve tests for vcmulq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise.
    
    (cherry picked from commit c3c828436e7db1787d644153fe07daf356c99f2a)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
index 142c315ecf5..456370e1de1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
index 158d750793d..64db652a1a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
index b38e0d9fb52..b60f5d718f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
index 7bf68735e52..22157d4e58f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
index fc7162aaa9c..f01b0f3421f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot180_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot180 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
index 13a4553b6bd..537385c5209 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot180_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot180 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
index 8767e2beee8..bc8692eb043 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
index 3f951039f35..d2a0b6d3f2c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
index f8e835f158f..37d7b79a75c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
index d0d30c59d44..1e57fba4bd3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
index 225b8910f88..05c444af804 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot270_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
index 1c8b0ebcf7e..b599c9fc171 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot270_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
index 20ccb5e9423..fded8a05089 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
index 7499f4271a6..54d939eb378 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
index d1b52e74d6d..d1e58cb84bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
index 35da5936f66..07c781f5103 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
index 17f96cb0a78..53b1930c045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot90_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
index 739fc9cd1fa..147f1807c29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot90_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
index 8259baa82cc..8c4b0902b09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
index 751a9a6c03d..b3131a5e984 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
index c4aef6cbf30..000610367b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
index 9c54f0870e7..8e31ad563c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
index 7634d61b6ea..b53324738f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
index 21b6acf9733..a73482a09e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit f25c97c8326c211ec65aecfda495599adf3caa72
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:39:16 2022

    arm: improve tests and fix vqabsq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vqabsq_s<mode>): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise.
    
    (cherry picked from commit 672eec5db5e673713540022c5a467ce6be165f53)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 3a1db782203..2730c1d9df2 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -381,7 +381,7 @@
 	 VQABSQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vqabs.s%#<V_sz_elem> %q0, %q1"
+  "vqabs.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c
index e74e04ac92f..7172ac5cddd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqabsq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqabst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c
index f6ca8a6c3d6..297cb196f1a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqabsq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqabst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c
index d89a5aa3fa5..83c69931239 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqabsq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqabst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c
index e67c008cf6e..bf849fe9354 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vqabsq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vqabsq (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c
index 8023ff8d22e..1f88821de23 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vqabsq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vqabsq (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c
index b36d2b762e9..1399f7c1636 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vqabsq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vqabsq (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 9d80744291001fe3e29d2d7430639a3c46265622
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:40:39 2022

    arm: improve tests for vqdmladhq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise.
    
    (cherry picked from commit d26036dd88ab6c792928032ed05cc7e0a3dd345e)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c
index 51cdadc9ece..aa9c78c883b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c
index 7e43fed1503..4694a6f9ec5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c
index adf591041e3..c8dc67fdd12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c
index 2dc453bdd9a..74ebbfa8b97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c
index 06f3204e47e..796de4df283 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c
index 79670b8b153..d585f5fac20 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit e776a8333bab96a997738a8a0a647eae28ba379c
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:41:30 2022

    arm: improve tests for vqdmladhxq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise.
    
    (cherry picked from commit f2a324b29e07b5d9b3b0c299dbb6558a9f3b8574)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c
index c2446e69181..19c5ce5a64f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c
index 12b45517535..e00162addae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c
index 146aa51306b..19767d2cd41 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c
index 5a6f4455c20..c6a2fa80670 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c
index 4eafa6f9476..d38bd691243 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c
index cc6643574f4..322f702d962 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 98c45781be3fed8ed8c8819cf196faa2b5753892
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:42:09 2022

    arm: improve tests for vqrdmladhq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
    
    (cherry picked from commit 6c43db2480f0e50878ba4da4d47c6621513fe91f)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
index fce4f5a35ef..5b0e134a0ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
index e550b6a7995..6fdf3879cc2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
index b07b28e5bcd..ef75f737161 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
index 5bdac923b20..cf7cdb202ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
index aade9bb0ea1..5a022fe3009 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
index bde80fa5279..2cb27df16f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 017b5dbc34282ed221370f32343dff908252d039
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:42:42 2022

    arm: improve tests for vqrdmladhxq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
    
    (cherry picked from commit 22a02a9576d234c517f33972e572541438eb9018)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
index 677efdcd1e4..1f68671b3f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
index 8ee8bbb420b..eaea6e1f482 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
index 7cfa88fee28..0f582a91f3a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
index 2410ef12b38..a26898ebdab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
index 716028cadfd..572486ecf82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
index 8f9bed5fdb7..00e478b9d3e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 48afcf6f720b8a69dd0cab3010d3c423d038d569
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:44:29 2022

    arm: improve tests for vqrdmlashq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
    
    (cherry picked from commit 26c400b1d82482b905f4d804e959b090fe72ab39)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
index 8ff8c34d529..2710f2f0442 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqrdmlashq_n_s16 (a, b, c);
+  return vqrdmlashq_n_s16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqrdmlash.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqrdmlashq (a, b, c);
+  return vqrdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlash.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
index 02583f0627b..5fefc3938c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqrdmlashq_n_s32 (a, b, c);
+  return vqrdmlashq_n_s32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqrdmlash.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqrdmlashq (a, b, c);
+  return vqrdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlash.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
index 0bd5bcac71f..df96fe85213 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqrdmlashq_n_s8 (a, b, c);
+  return vqrdmlashq_n_s8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqrdmlash.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqrdmlashq (a, b, c);
+  return vqrdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlash.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 4971715f884823a3bd18ee57fffb3a9e1d571d26
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:44:48 2022

    arm: improve tests for vqdmlsdhq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise.
    
    (cherry picked from commit 8de09beb71a9bdc24c969ab648c4c5570204ab87)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c
index d1e66864d10..f87287ab8cd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c
index cc80f211ec8..8155aaf843c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c
index 5c9d81a6526..d39badc7707 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c
index eb058fb9789..a4fa1d5024b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c
index 27b93d6b76c..0c6ba426ded 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c
index 1dd2a59ee4b..089c4cdcc39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 997b86eda16b7aa750c8431b3c36f6dd9edeeead
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:45:45 2022

    arm: improve tests for vqdmlsdhxq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise.
    
    (cherry picked from commit 8b9fcce72f7f93b11129a298c54c9c178e510cf0)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c
index 6ab9743054c..1742d47291c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c
index a34618e97fd..1c1b73a2251 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c
index fdbe89ab6b8..0a980a081a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c
index 786decc6238..713ce9732d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c
index c0244c44067..02f0a3cd6b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c
index 12b43c8edd8..c1792879138 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit eae89159b54ce7d276a0bec0372f50fa63a7e388
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:46:25 2022

    arm: improve tests for vqrdmlsdhq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
    
    (cherry picked from commit 79090d68ba7bd59b1cf2585a1478fd5781f577d4)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
index d0054b8ea97..6a5776215ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
index 7d3fe45eb4d..9539e249d6a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
index c33f8ea903b..69e54f53a76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
index 3bd760d38aa..3eb957d6029 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
index e23dc94a9ed..3a3fb506c01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
index 836e04af566..65ac15da9c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit b56b280c8703aa565a6c20f43ac4d0c7aca4d417
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:47:00 2022

    arm: improve tests for vqrdmlsdhxq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
    
    (cherry picked from commit ef0bec9036cef36b26006d9a3d22b879d705e75c)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
index 2fbd351f3b4..3598f50ccba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
index 324a6e63398..1ab22edf9ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
index 287868b1190..01103e99b61 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
index 9d8ea9b2694..522d0ba4a3a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
index aca0b358ea9..5198dfa754e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
index 18f95317b4c..b5baa3dea79 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit a0cbc3d6d96ac7391b6fc4ce5951bf92e66077e1
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:47:54 2022

    arm: improve tests for vqrdmulhq*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
    
    (cherry picked from commit 73a712e9c6620f8b7aede3eb1c2984fb91646201)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
index c4b6b7e22f8..fc3a33073aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
index 6de3eb1cb9a..897ad5bd28c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
index df3dfa87fbf..05ab0609af4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
index 24831e8a5f8..1d9dc07787c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
index 70257c3c0a0..76d7507e35a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
index 7cd39d2a0d4..7fd2119ea63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
index 42fe9cbaa2b..8a90a399858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqrdmulhq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
index 5f014fae9fb..973464b3297 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqrdmulhq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
index 887e294661b..65aab964f4e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqrdmulhq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
index 409fc29c0d0..f3153c86b4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqrdmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
index 18e11b1248c..48b10dbd025 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqrdmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
index 3f1441d5d6b..9f0346fc841 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqrdmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit 856c74b2cbac0f3eae91735af92013496077ef21
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Mon Nov 28 17:49:36 2022

    arm: improve tests and fix vqnegq*
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vqnegq_s<mode>): Fix spacing.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise.
    
    (cherry picked from commit 1563de6f9d3a9607ae2872b87d9718add3cf6e6a)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 2730c1d9df2..e980da68344 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -367,7 +367,7 @@
 	 VQNEGQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vqneg.s%#<V_sz_elem> %q0, %q1"
+  "vqneg.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c
index 4f0145d2ebd..f3799a35b12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqnegq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqnegt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c
index da4f90bad53..bbe64ff4d52 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqnegq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqnegt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c
index ac1250b2fac..71fcdd7cba7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqnegq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqnegt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c
index f9210cd70f4..d5fb4a19854 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vqnegq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vqnegq (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c
index c2ded7fe659..2c8e709f491 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vqnegq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vqnegq (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c
index d1cc83a6cd0..2f7f7619ef6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vqnegq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vqnegq (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit af4cdaa51a3bb93331f4f35ac13536a3c477142d
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Tue Nov 29 16:45:10 2022

    arm: improve tests for vld2q*
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vld2q_f16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vld2q_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld2q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld2q_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld2q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld2q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld2q_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld2q_u8.c: Likewise.
    
    (cherry picked from commit a8704dc9d5f00bff9f52cf626f129ac1c6520d65)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c
index 24e7a2ea4d0..81690b1022e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8x2_t
-foo (float16_t const * addr)
+foo (float16_t const *addr)
 {
   return vld2q_f16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
-/* { dg-final { scan-assembler "vld21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8x2_t
-foo1 (float16_t const * addr)
+foo1 (float16_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c
index 727484caaf6..d2ae31fa9e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4x2_t
-foo (float32_t const * addr)
+foo (float32_t const *addr)
 {
   return vld2q_f32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
-/* { dg-final { scan-assembler "vld21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4x2_t
-foo1 (float32_t const * addr)
+foo1 (float32_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c
index f2864a00478..fb4dc1b4fcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8x2_t
-foo (int16_t const * addr)
+foo (int16_t const *addr)
 {
   return vld2q_s16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
-/* { dg-final { scan-assembler "vld21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8x2_t
-foo1 (int16_t const * addr)
+foo1 (int16_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c
index 9fe2e0459b5..aeb85238fd2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4x2_t
-foo (int32_t const * addr)
+foo (int32_t const *addr)
 {
   return vld2q_s32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
-/* { dg-final { scan-assembler "vld21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4x2_t
-foo1 (int32_t const * addr)
+foo1 (int32_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c
index 736080a94a7..687e5ded48c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16x2_t
-foo (int8_t const * addr)
+foo (int8_t const *addr)
 {
   return vld2q_s8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
-/* { dg-final { scan-assembler "vld21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16x2_t
-foo1 (int8_t const * addr)
+foo1 (int8_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c
index 2d89ebdcf6b..281fe5eaf10 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8x2_t
-foo (uint16_t const * addr)
+foo (uint16_t const *addr)
 {
   return vld2q_u16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
-/* { dg-final { scan-assembler "vld21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8x2_t
-foo1 (uint16_t const * addr)
+foo1 (uint16_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c
index 28d311eca68..524afee72e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4x2_t
-foo (uint32_t const * addr)
+foo (uint32_t const *addr)
 {
   return vld2q_u32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
-/* { dg-final { scan-assembler "vld21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4x2_t
-foo1 (uint32_t const * addr)
+foo1 (uint32_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c
index 790c9743c9a..9eebbd42719 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16x2_t
-foo (uint8_t const * addr)
+foo (uint8_t const *addr)
 {
   return vld2q_u8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
-/* { dg-final { scan-assembler "vld21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16x2_t
-foo1 (uint8_t const * addr)
+foo1 (uint8_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit fc68bca6a77c20931d61c96ef47cf6ee85783331
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Jan 18 17:38:42 2023

    arm: fix missing extern "C" in MVE tests
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Add missing extern
            "C".
            * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
    
    (cherry picked from commit 267f01a493ab8a0bec9325ce3386b946c46f2e98)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
index 20a999da1d2..31f78b30ed8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
index 986cb8d3ba5..77c0521161c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
index 57a4b36f5fe..1cf93d50379 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
index abed33b0e37..98d80e42da9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t a)
   return vhaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
index 5e5204fb3a7..9b7e611c0e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t a)
   return vhaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
index b35221ef81b..4d82970e7ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t a)
   return vhaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
index 310964f3440..2788eb2f8ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
index d8222645c21..67872a77076 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
index 85b2feee346..1ec890591ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
index 2da0aa053e5..bc84618b036 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
index 49b865a123b..6abdfce981f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
index 5ecd3cbf6ec..0c68c68206b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vhaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
index a4e277d4e1f..d5bff94a46e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
index c79b88d6ced..af3e219b3f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
index 61893536231..a4551e207c2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
index 146d226f36f..71facc46ad9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vhaddq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
index b70014fb6a5..d45421c76d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vhaddq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
index 03978dfa28a..5f16fbd9121 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vhaddq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
index c3c787583dd..4e332733459 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
index a1ab196d3d2..5cdfd3921a5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
index 061ae89315e..7a2ed232f29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
index 0ee88520f8f..e24ff1668db 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
index 0a0e512c5fc..e9f13956b96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
index c495641c532..cba0a302e2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vhaddq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
index af4f534d7ff..4d1bab9641e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
index 941d38074a4..8effffaf377 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
index 9ceb4ef3c6f..f55cd8f5528 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
index 037ed2c637d..73575a401c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t a)
   return vhsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
index f51eb10ecbf..f152ef10a9d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t a)
   return vhsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
index 24dd45db152..0a58b1ed355 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t a)
   return vhsubq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
index 0f275d48753..ec8d9aaed0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
index 21aeb9d2a59..e98635a8c11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
index b3ee94341b5..3107bb55844 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
index 690ef2de5ba..783309fdbed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
index cfe12573fa0..99bc278d16f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
index 1926bc34219..ae186512b78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vhsubq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
index fcda4c541a6..260ba9ee509 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
index 55637221f21..be5cc04c2b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
index ecfe188f3fa..b0c28be7872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
index bf3d6c38b85..f31bb3fa632 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint16x8_t a, mve_pred16_t p)
   return vhsubq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
index 4ae75b09950..a35346d9b2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint32x4_t a, mve_pred16_t p)
   return vhsubq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
index edfa4216a31..25c85449081 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -54,4 +58,8 @@ foo2 (uint8x16_t a, mve_pred16_t p)
   return vhsubq_x (a, 1, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
index bd2771b0978..dc3433cb81a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
index 0ea40df3d9e..a1e1faeacb5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
index 90ee94defb0..bbfce818be4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
index d700741169a..86fc9d7cf33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
index f43c9626829..53274267515 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
index a0908ba786b..04d89c6c6bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
   return vhsubq_x (a, b, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
index f201d5fa047..5925d9e968e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
   return vmladavaxq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
index c90647a5064..87d66e654f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
   return vmladavaxq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
index 57af7bc1c78..803a5becc86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
   return vmladavaxq_p (add, m1, m2, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
index 684580d1c36..6a81b4acfcb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t add, int16x8_t m1, int16x8_t m2)
   return vmladavaxq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
index 5d152647b55..b63ca43abba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t add, int32x4_t m1, int32x4_t m2)
   return vmladavaxq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
index 71bcdc9b55e..2430858aa51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t add, int8x16_t m1, int8x16_t m2)
   return vmladavaxq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
index 0fac7abeac0..17b28cfd956 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
index d750b1f2c14..e6bb4e0b51d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
index 5fc796edf75..f39451f6bc0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
index decad65c188..a87163c0446 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t a)
   return vqaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
index b0a6d79093e..a6aa9b5dddc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t a)
   return vqaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
index f9ca9a1f042..4bd47319f5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t a)
   return vqaddq (a, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
index ffa31463372..97e2a6039eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t a, int16x8_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
index c5937a967ff..db9355d56dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t a, int32x4_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
index 9f937512811..2804d668da8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t a, int8x16_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
index aa4be43f244..17e59961c87 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint16x8_t a, uint16x8_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
index daef60eb5ca..ce3a397acd6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint32x4_t a, uint32x4_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
index e28807ec708..faa881f67f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (uint8x16_t a, uint8x16_t b)
   return vqaddq (a, b);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
index 210bacec2fb..909631c549d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
   return vqdmlahq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
index dbb2494b216..fb670befeff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
   return vqdmlahq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
index a7962f82d38..f66740bee0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
   return vqdmlahq (add, m1, m2);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
index 34d407f0142..918de9572e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
   return vqdmlashq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
index 50a665ea7e5..b25b66057bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
   return vqdmlashq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
index 45f34b60382..b796f205e5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -38,4 +42,8 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
   return vqdmlashq_m (m1, m2, add, p);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
index a3f1ae8d6b8..9a2549464c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
   return vqdmlashq (m1, m2, add);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
index cf867e56874..36fc7b066a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
   return vqdmlashq (m1, m2, add);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
index 7e9362cab60..1e7cd44d4f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
   return vqdmlashq (m1, m2, add);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
index 6b148a4b03d..5b1731f7332 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float16x8_t b)
   return vsetq_lane (1.1, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
index e4e7f892e97..34b403d0601 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (float32x4_t b)
   return vsetq_lane (1.1, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
index 950cd016b76..458fd5e6f26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int16_t a, int16x8_t b)
   return vsetq_lane (a, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
index 6b49ccd91e4..44672f6c264 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int32_t a, int32x4_t b)
   return vsetq_lane (a, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
index 95ba4da1f51..62e8ee50929 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int64_t a, int64x2_t b)
   return vsetq_lane (a, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
index 91a5baee55f..3a79ab1759b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -30,4 +34,8 @@ foo1 (int8_t a, int8x16_t b)
   return vsetq_lane (a, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
index 53986a5c1b1..8a42773e01f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint16x8_t b)
   return vsetq_lane (1, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
index 3f17db9623a..43778e6103d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint32x4_t b)
   return vsetq_lane (1, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
index 5ce4c544c25..c75bfa448f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint64x2_t b)
   return vsetq_lane (1, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
index 58e932b85e8..5fb20161259 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
@@ -5,6 +5,10 @@
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
 **foo:
 **	...
@@ -42,4 +46,8 @@ foo2 (uint8x16_t b)
   return vsetq_lane (1, b, 1);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

commit c7c4dfb5989e80ffc8e8439a8d9a9ed654612b90
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Mon Jan 16 12:40:40 2023

    arm: Split up MVE _Generic associations to prevent type clashes [PR107515]
    
    With these previous patches:
    https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606586.html
    https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606587.html
    we enabled the MVE overloaded _Generic associations to handle more
    scalar types, however at PR 107515 we found a new regression that
    wasn't detected in our testing:
    
    With glibc's posix/types.h:
    ```
    typedef signed int __int32_t;
    ...
    typedef __int32_t int32_t;
    ```
    We would get a `error: '_Generic' specifies two compatible types`
    from `__ARM_mve_coerce3` because of `type: param`, when `type` is
    `int` and `int32_t: param` both being the same under the hood.
    
    The same did not happen with Newlib's header sys/_stdint.h:
    ```
    typedef long int __int32_t;
    ...
    typedef __int32_t int32_t ;
    ```
    which worked fine, because it uses `long int`.
    
    The same could feasibly happen in `__ARM_mve_coerce2` between
    `__fp16` and `float16_t`.
    
    The solution here is to break the _Generic down so that the similar
    types don't appear at the same level, as is done in `__ARM_mve_typeid`
    
    gcc/ChangeLog:
            PR target/96795
            PR target/107515
            * config/arm/arm_mve.h (__ARM_mve_coerce2): Split types.
            (__ARM_mve_coerce3): Likewise.
    
    gcc/testsuite/ChangeLog:
            PR target/96795
            PR target/107515
            * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: New test.
            * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: New test.
    
    (cherry picked from commit 8a1360e72d6c6056606aa5edd8c906c50f26de59)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 09167ec118e..70003653db6 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35659,9 +35659,9 @@ extern void *__ARM_undef;
 #define __ARM_mve_coerce1(param, type) \
     _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef)
 #define __ARM_mve_coerce2(param, type) \
-    _Generic(param, type: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)
+    _Generic(param, type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef))
 #define __ARM_mve_coerce3(param, type) \
-    _Generic(param, type: param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef)
+    _Generic(param, type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef))
 
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
new file mode 100644
index 00000000000..7492e9b22bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
@@ -0,0 +1,65 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
+#include "arm_mve.h"
+
+float f1;
+double f2;
+float16_t f3;
+float32_t f4;
+__fp16 f5;
+_Float16 f6;
+
+int i1;
+short i2;
+long i3;
+long long i4;
+int8_t i5;
+int16_t i6;
+int32_t i7;
+int64_t i8;
+
+const int ci1;
+const short ci2;
+const long ci3;
+const long long ci4;
+const int8_t ci5;
+const int16_t ci6;
+const int32_t ci7;
+const int64_t ci8;
+
+float16x8_t floatvec;
+int16x8_t intvec;
+
+void test(void)
+{
+    /* Test a few different supported ways of passing an int value.  The
+    intrinsic vmulq was chosen arbitrarily, but it is representative of
+    all intrinsics that take a non-const scalar value.  */
+    intvec = vmulq(intvec, 2);
+    intvec = vmulq(intvec, (int32_t) 2);
+    intvec = vmulq(intvec, (short) 2);
+    intvec = vmulq(intvec, i1);
+    intvec = vmulq(intvec, i2);
+    intvec = vmulq(intvec, i3);
+    intvec = vmulq(intvec, i4);
+    intvec = vmulq(intvec, i5);
+    intvec = vmulq(intvec, i6);
+    intvec = vmulq(intvec, i7);
+    intvec = vmulq(intvec, i8);
+
+    /* Test a few different supported ways of passing a float value.  */
+    floatvec = vmulq(floatvec, 0.5);
+    floatvec = vmulq(floatvec, 0.5f);
+    floatvec = vmulq(floatvec, (__fp16) 0.5);
+    floatvec = vmulq(floatvec, f1);
+    floatvec = vmulq(floatvec, f2);
+    floatvec = vmulq(floatvec, f3);
+    floatvec = vmulq(floatvec, f4);
+    floatvec = vmulq(floatvec, f5);
+    floatvec = vmulq(floatvec, f6);
+    floatvec = vmulq(floatvec, 0.15f16);
+    floatvec = vmulq(floatvec, (_Float16) 0.15);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
new file mode 100644
index 00000000000..9a921bf40e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
@@ -0,0 +1,45 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
+
+#include "arm_mve.h"
+
+int i1;
+short i2;
+long i3;
+long long i4;
+int8_t i5;
+int16_t i6;
+int32_t i7;
+int64_t i8;
+
+const int ci1;
+const short ci2;
+const long ci3;
+const long long ci4;
+const int8_t ci5;
+const int16_t ci6;
+const int32_t ci7;
+const int64_t ci8;
+
+int16x8_t intvec;
+
+void test(void)
+{
+    /* Test a few different supported ways of passing an int value.  The
+    intrinsic vmulq was chosen arbitrarily, but it is representative of
+    all intrinsics that take a non-const scalar value.  */
+    intvec = vmulq(intvec, 2);
+    intvec = vmulq(intvec, (int32_t) 2);
+    intvec = vmulq(intvec, (short) 2);
+    intvec = vmulq(intvec, i1);
+    intvec = vmulq(intvec, i2);
+    intvec = vmulq(intvec, i3);
+    intvec = vmulq(intvec, i4);
+    intvec = vmulq(intvec, i5);
+    intvec = vmulq(intvec, i6);
+    intvec = vmulq(intvec, i7);
+    intvec = vmulq(intvec, i8);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit 09f0fd468f5fc5b67344c0f2e86376804e52aee3
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Tue Apr 4 14:06:41 2023

    arm: Fix vcreate definition
    
    From the initial merge of the MVE backend, the vcreate
    intrinsic has had the vector lanes mixed up, compared
    to the intended (as per the ACLE) definition. This is
    also a discrepancy with clang:
    https://godbolt.org/z/4n93e5aqj
    
    This patches simply switches the operands around and
    makes the tests more specific on the input registers
    (I do not touch the output Q regs as they vary based
    on softfp/hardfp or the input registers when the input
    is a constant, since, in that case, a single register
    is loaded with a constant and then the same register is
    used twice as "vmov q0[2], q0[0], r2, r2" and the reg
    num might not always be guaranteed).
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vcvtq_n_to_f_<supf><mode>): Swap operands.
            (mve_vcreateq_f<mode>): Swap operands.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Tighten test.
            * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Tighten test.
    
    (cherry picked from commit 3f0ca7a3e4431534bff3b8eb73709cc822e489b0)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index e980da68344..16966bdfc78 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -716,7 +716,7 @@
 	 VCREATEQ_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
+  "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -731,7 +731,7 @@
 	 VCREATEQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
+  "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
index 0458bb1bb7c..8d6764d8938 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 float16x8_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
index af782b5ac53..6ab05ced809 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 float32x4_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
index 8a3e91843f8..290637595a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 int16x8_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
index 5e385dfeee0..4aeead1175e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 int32x4_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
index df901680c2b..9f6df427a8f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 int64x2_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
index e853395af0c..196c147fb65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 int8x16_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
index bf4a137bb43..20b18e2ac15 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 uint16x8_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
index efb58ddff8b..febfd3bd782 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 uint32x4_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
index 91dd885dce1..5a49b346bf4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 uint64x2_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
index d5d001158ed..c0ac5e51225 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
@@ -12,8 +12,8 @@ extern "C" {
 /*
 **foo:
 **	...
-**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
-**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
 **	...
 */
 uint8x16_t
@@ -39,4 +39,4 @@ foo1 ()
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit bb113a56e31159f4fbe26cc06ee25e4972ce74b5
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Tue Jan 24 17:59:23 2023

    arm: Make MVE masked stores read memory operand [PR 108177]
    
    This patch adds the memory operand of MVE masked stores as input operands to
    mimic the 'partial' writes, to prevent erroneous write-after-write
    optimizations as described in the PR.
    
    gcc/ChangeLog:
    
            PR target/108177
            * config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
            mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
            as input operand.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/pr108177-1-run.c: New test.
            * gcc.target/arm/mve/pr108177-1.c: New test.
            * gcc.target/arm/mve/pr108177-10-run.c: New test.
            * gcc.target/arm/mve/pr108177-10.c: New test.
            * gcc.target/arm/mve/pr108177-11-run.c: New test.
            * gcc.target/arm/mve/pr108177-11.c: New test.
            * gcc.target/arm/mve/pr108177-12-run.c: New test.
            * gcc.target/arm/mve/pr108177-12.c: New test.
            * gcc.target/arm/mve/pr108177-13-run.c: New test.
            * gcc.target/arm/mve/pr108177-13.c: New test.
            * gcc.target/arm/mve/pr108177-14-run.c: New test.
            * gcc.target/arm/mve/pr108177-14.c: New test.
            * gcc.target/arm/mve/pr108177-2-run.c: New test.
            * gcc.target/arm/mve/pr108177-2.c: New test.
            * gcc.target/arm/mve/pr108177-3-run.c: New test.
            * gcc.target/arm/mve/pr108177-3.c: New test.
            * gcc.target/arm/mve/pr108177-4-run.c: New test.
            * gcc.target/arm/mve/pr108177-4.c: New test.
            * gcc.target/arm/mve/pr108177-5-run.c: New test.
            * gcc.target/arm/mve/pr108177-5.c: New test.
            * gcc.target/arm/mve/pr108177-6-run.c: New test.
            * gcc.target/arm/mve/pr108177-6.c: New test.
            * gcc.target/arm/mve/pr108177-7-run.c: New test.
            * gcc.target/arm/mve/pr108177-7.c: New test.
            * gcc.target/arm/mve/pr108177-8-run.c: New test.
            * gcc.target/arm/mve/pr108177-8.c: New test.
            * gcc.target/arm/mve/pr108177-9-run.c: New test.
            * gcc.target/arm/mve/pr108177-9.c: New test.
            * gcc.target/arm/mve/pr108177-main.x: New test include.
            * gcc.target/arm/mve/pr108177.x: New test include.
    
    (cherry picked from commit c1093923733a1072a237f112e3239b5ebd88eadd)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 16966bdfc78..b02ecfd8c7f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -7269,15 +7269,13 @@
 }
   [(set_attr "length" "8")])
 
-;;
-;; [vstrbq_p_s vstrbq_p_u]
-;;
 (define_insn "mve_vstrbq_p_<supf><mode>"
   [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRBQ))
-  ]
+	(unspec:<MVE_B_ELEM>
+	 [(match_operand:MVE_2 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRBQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
@@ -8076,10 +8074,11 @@
 ;;
 (define_insn "mve_vstrhq_p_fv8hf"
   [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
-	(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
-		      (match_operand:V8BI 2 "vpr_register_operand" "Up")]
-	 VSTRHQ_F))
-  ]
+	(unspec:V8HI
+	 [(match_operand:V8HF 1 "s_register_operand" "w")
+	  (match_operand:V8BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRHQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8096,8 +8095,10 @@
 ;;
 (define_insn "mve_vstrhq_p_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
+	(unspec:<MVE_H_ELEM>
+	 [(match_operand:MVE_6 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
 	 VSTRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -8275,10 +8276,11 @@
 ;;
 (define_insn "mve_vstrwq_p_fv4sf"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
-		      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRWQ_F))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SF 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8295,10 +8297,11 @@
 ;;
 (define_insn "mve_vstrwq_p_<supf>v4si"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4BI 2 "vpr_register_operand" "Up")]
-	 VSTRWQ))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SI 1 "s_register_operand" "w")
+	  (match_operand:V4BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
new file mode 100644
index 00000000000..ca092df9802
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-1.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
new file mode 100644
index 00000000000..2d42062bc8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint8x16_t
+#define INTRINSIC vstrbq_u8
+#define INTRINSIC_P vstrbq_p_u8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
new file mode 100644
index 00000000000..0a58b8f7fdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-10.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
new file mode 100644
index 00000000000..4db594f588f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrhq_s32
+#define INTRINSIC_P vstrhq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
new file mode 100644
index 00000000000..9f568eacf34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-11.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
new file mode 100644
index 00000000000..329fcb33eeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrwq_u32
+#define INTRINSIC_P vstrwq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
new file mode 100644
index 00000000000..8e946a29795
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-12.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
new file mode 100644
index 00000000000..3f7c5b2a4c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrwq_s32
+#define INTRINSIC_P vstrwq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
new file mode 100644
index 00000000000..2e731ee3824
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-13.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
new file mode 100644
index 00000000000..2f82228d8f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE float16x8_t
+#define INTRINSIC vstrhq_f16
+#define INTRINSIC_P vstrhq_p_f16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
new file mode 100644
index 00000000000..3cebcf5bbcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-14.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
new file mode 100644
index 00000000000..ba6196b7994
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE float32x4_t
+#define INTRINSIC vstrwq_f32
+#define INTRINSIC_P vstrwq_p_f32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
new file mode 100644
index 00000000000..03750c9c7a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-2.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
new file mode 100644
index 00000000000..52c8d87ccc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE int8x16_t
+#define INTRINSIC vstrbq_s8
+#define INTRINSIC_P vstrbq_p_s8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
new file mode 100644
index 00000000000..bab08e042d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-3.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
new file mode 100644
index 00000000000..ac89e7ea883
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrbq_u16
+#define INTRINSIC_P vstrbq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
new file mode 100644
index 00000000000..cff62c75dd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-4.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
new file mode 100644
index 00000000000..dc4f7ddab07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrbq_s16
+#define INTRINSIC_P vstrbq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
new file mode 100644
index 00000000000..7211828ceeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-5.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
new file mode 100644
index 00000000000..d1dfd328d66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrbq_u32
+#define INTRINSIC_P vstrbq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
new file mode 100644
index 00000000000..4e7d108cd81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-6.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
new file mode 100644
index 00000000000..fa70dde9eeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrbq_s32
+#define INTRINSIC_P vstrbq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
new file mode 100644
index 00000000000..94c492ed96b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-7.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
new file mode 100644
index 00000000000..73cd8605171
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrhq_u16
+#define INTRINSIC_P vstrhq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
new file mode 100644
index 00000000000..3c34045f31d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-8.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
new file mode 100644
index 00000000000..187c2b3f4ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrhq_s16
+#define INTRINSIC_P vstrhq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
new file mode 100644
index 00000000000..967cf7f1992
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-9.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
new file mode 100644
index 00000000000..caecd18a881
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrhq_u32
+#define INTRINSIC_P vstrhq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
new file mode 100644
index 00000000000..f5f965fb698
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
@@ -0,0 +1,31 @@
+#include <arm_mve.h>
+extern void abort (void);
+
+__attribute__ ((noipa)) void
+write_expected (uint32x4_t v, void *a)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC (a, _v);
+}
+
+void test (uint32x4_t, void *, mve_pred16_t, mve_pred16_t);
+
+int main(void)
+{
+  uint32x4_t v = {0, 1, 2, 3};
+  uint32_t actual[] = {0, 0, 0, 0};
+  uint32_t expected[] = {0, 0, 0, 0};
+
+  write_expected (v, &(expected[0]));
+
+  mve_pred16_t p1 = 0xff00;
+  mve_pred16_t p2 = 0x00ff;
+
+  test (v, (void *)&actual[0], p1, p2);
+
+  if (__builtin_memcmp (&actual[0], &expected[0], 16) != 0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177.x b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
new file mode 100644
index 00000000000..019ef54eae7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
@@ -0,0 +1,9 @@
+#include "pr108177-main.x"
+
+__attribute__ ((noipa)) void
+test (uint32x4_t v, void *a, mve_pred16_t p1, mve_pred16_t p2)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC_P (a, _v, p1);
+  INTRINSIC_P (a, _v, p2);
+}

commit 60e54b99f597a594a9ad8deaa2af1ed66eb451c7
Author: Murray Steele <murray.steele@arm.com>
Date:   Wed Dec 22 16:55:58 2021

    arm: fix __arm_vld1q_z* and __arm_vst1q_p* intrinsics [PR108442]
    
    The MVE ACLE allows for __ARM_MVE_PRESERVE_USER_NAMESPACE to be defined,
    which removes definitions for intrinsic functions without the __arm_
    prefix. __arm_vld1q_z* and __arm_vst1q_p* are currently implemented via
    calls to vldr* and vstr*, which results in several compile-time errors when
    __ARM_MVE_PRESERVE_USER_NAMESPACE is defined. This patch replaces these
    with calls to their prefixed counterparts, __arm_vldr* and __arm_str*,
    and adds a test covering the definition of __ARM_MVE_PRESERVE_USER_NAMESPACE.
    
    gcc/ChangeLog:
    
            PR target/108442
            * config/arm/arm_mve.h (__arm_vst1q_p_u8): Use prefixed intrinsic
            function.
            (__arm_vst1q_p_s8): Likewise.
            (__arm_vld1q_z_u8): Likewise.
            (__arm_vld1q_z_s8): Likewise.
            (__arm_vst1q_p_u16): Likewise.
            (__arm_vst1q_p_s16): Likewise.
            (__arm_vld1q_z_u16): Likewise.
            (__arm_vld1q_z_s16): Likewise.
            (__arm_vst1q_p_u32): Likewise.
            (__arm_vst1q_p_s32): Likewise.
            (__arm_vld1q_z_u32): Likewise.
            (__arm_vld1q_z_s32): Likewise.
            (__arm_vld1q_z_f16): Likewise.
            (__arm_vst1q_p_f16): Likewise.
            (__arm_vld1q_z_f32): Likewise.
            (__arm_vst1q_p_f32): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/general/preserve_user_namespace_1.c: New test.
    
    (cherry picked from commit f54e31ddefe3ea7146624eabcb75b1c90dc59f1a)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 70003653db6..82ceec2bbfc 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -16171,14 +16171,14 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_u8 (uint8_t * __addr, uint8x16_t __value, mve_pred16_t __p)
 {
-  return vstrbq_p_u8 (__addr, __value, __p);
+  return __arm_vstrbq_p_u8 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_s8 (int8_t * __addr, int8x16_t __value, mve_pred16_t __p)
 {
-  return vstrbq_p_s8 (__addr, __value, __p);
+  return __arm_vstrbq_p_s8 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
@@ -16203,14 +16203,14 @@ __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_u8 (uint8_t const *__base, mve_pred16_t __p)
 {
-  return vldrbq_z_u8 ( __base, __p);
+  return __arm_vldrbq_z_u8 ( __base, __p);
 }
 
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_s8 (int8_t const *__base, mve_pred16_t __p)
 {
-  return vldrbq_z_s8 ( __base, __p);
+  return __arm_vldrbq_z_s8 ( __base, __p);
 }
 
 __extension__ extern __inline int8x16x2_t
@@ -16253,14 +16253,14 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_u16 (uint16_t * __addr, uint16x8_t __value, mve_pred16_t __p)
 {
-  return vstrhq_p_u16 (__addr, __value, __p);
+  return __arm_vstrhq_p_u16 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_s16 (int16_t * __addr, int16x8_t __value, mve_pred16_t __p)
 {
-  return vstrhq_p_s16 (__addr, __value, __p);
+  return __arm_vstrhq_p_s16 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
@@ -16285,14 +16285,14 @@ __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_u16 (uint16_t const *__base, mve_pred16_t __p)
 {
-  return vldrhq_z_u16 ( __base, __p);
+  return __arm_vldrhq_z_u16 ( __base, __p);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_s16 (int16_t const *__base, mve_pred16_t __p)
 {
-  return vldrhq_z_s16 ( __base, __p);
+  return __arm_vldrhq_z_s16 ( __base, __p);
 }
 
 __extension__ extern __inline int16x8x2_t
@@ -16335,14 +16335,14 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_u32 (uint32_t * __addr, uint32x4_t __value, mve_pred16_t __p)
 {
-  return vstrwq_p_u32 (__addr, __value, __p);
+  return __arm_vstrwq_p_u32 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_s32 (int32_t * __addr, int32x4_t __value, mve_pred16_t __p)
 {
-  return vstrwq_p_s32 (__addr, __value, __p);
+  return __arm_vstrwq_p_s32 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
@@ -16367,14 +16367,14 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_u32 (uint32_t const *__base, mve_pred16_t __p)
 {
-  return vldrwq_z_u32 ( __base, __p);
+  return __arm_vldrwq_z_u32 ( __base, __p);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_s32 (int32_t const *__base, mve_pred16_t __p)
 {
-  return vldrwq_z_s32 ( __base, __p);
+  return __arm_vldrwq_z_s32 ( __base, __p);
 }
 
 __extension__ extern __inline int32x4x2_t
@@ -19837,7 +19837,7 @@ __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_f16 (float16_t const *__base, mve_pred16_t __p)
 {
-  return vldrhq_z_f16 (__base, __p);
+  return __arm_vldrhq_z_f16 (__base, __p);
 }
 
 __extension__ extern __inline void
@@ -19853,7 +19853,7 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p)
 {
-  return vstrhq_p_f16 (__addr, __value, __p);
+  return __arm_vstrhq_p_f16 (__addr, __value, __p);
 }
 
 __extension__ extern __inline float32x4x4_t
@@ -19878,7 +19878,7 @@ __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_f32 (float32_t const *__base, mve_pred16_t __p)
 {
-  return vldrwq_z_f32 (__base, __p);
+  return __arm_vldrwq_z_f32 (__base, __p);
 }
 
 __extension__ extern __inline void
@@ -19894,7 +19894,7 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p)
 {
-  return vstrwq_p_f32 (__addr, __value, __p);
+  return __arm_vstrwq_p_f32 (__addr, __value, __p);
 }
 
 __extension__ extern __inline float16x8_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/general/preserve_user_namespace_1.c b/gcc/testsuite/gcc.target/arm/mve/general/preserve_user_namespace_1.c
new file mode 100644
index 00000000000..f107ac44ca9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/general/preserve_user_namespace_1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#define __ARM_MVE_PRESERVE_USER_NAMESPACE
+#include <arm_mve.h>

commit 0b968346dad68953acf964575ff984b8004a6520
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 6 19:57:08 2023

    arm: remove unused variables from test
    
    This is just a minor issue I found with a previous test
    of mine that caused it to fail in C++ mode due to these
    unused const variables being uninitialised. I forgot to
    remove these after removing some test cases that did use
    them. I removed the test cases, because I came to the
    conclusion that the const-ness of the immediate was
    irrelevant to the test itself.
    Removing the variables now makes the test PASS for C++.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Remove unused variables.
            * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Remove unused variables.
    
    (cherry picked from commit 1d509f190393627cffffdf0afffc427b25dd21c2)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
index 7492e9b22bd..a2787a47859 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
@@ -19,15 +19,6 @@ int16_t i6;
 int32_t i7;
 int64_t i8;
 
-const int ci1;
-const short ci2;
-const long ci3;
-const long long ci4;
-const int8_t ci5;
-const int16_t ci6;
-const int32_t ci7;
-const int64_t ci8;
-
 float16x8_t floatvec;
 int16x8_t intvec;
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
index 9a921bf40e8..7b88f462e17 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
@@ -13,15 +13,6 @@ int16_t i6;
 int32_t i7;
 int64_t i8;
 
-const int ci1;
-const short ci2;
-const long ci3;
-const long long ci4;
-const int8_t ci5;
-const int16_t ci6;
-const int32_t ci7;
-const int64_t ci8;
-
 int16x8_t intvec;
 
 void test(void)

commit d04583df6e2ae2cffb7f5df79081bbbc539b7af9
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Tue Feb 28 11:03:18 2023

    arm: Mve testsuite improvements
    
    Hello all,
    
    this patch improves a number of MVE tests in the testsuite for more
    precise and better coverage using check-function-bodies instead of
    scan-assembler checks.  Also all intrusctions prescribed in the ACLE[1]
    are now checked.
    
    Best Regards
    
      Andrea
    
    [1] <https://github.com/ARM-software/acle>
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
index 699e40d0e3b..f0a9243a6d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base)
+foo (float16_t const *base)
 {
   return vld1q_f16 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base)
+foo1 (float16_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
index 86592303362..129d256dd86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base)
+foo (float32_t const *base)
 {
   return vld1q_f32 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base)
+foo1 (float32_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
index f4f04f534db..a95bf6c4260 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base)
+foo (int16_t const *base)
 {
   return vld1q_s16 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base)
+foo1 (int16_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
index e0f66166751..bb24e52d164 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base)
+foo (int32_t const *base)
 {
   return vld1q_s32 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base)
+foo1 (int32_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
index 1b7edead6b1..0d89c2f19cd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vld1q_s8 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base)
+foo1 (int8_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
index 50e1f5cedcb..a31baf75fed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
 {
   return vld1q_u16 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base)
+foo1 (uint16_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
index a13fe824382..7d4f858c784 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base)
+foo (uint32_t const *base)
 {
   return vld1q_u32 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base)
+foo1 (uint32_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
index dfd1deb93f0..455ec5ce105 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vld1q_u8 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base)
+foo1 (uint8_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
index 3c32e408e42..951b795fd59 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, mve_pred16_t p)
+foo (float16_t const *base, mve_pred16_t p)
 {
   return vld1q_z_f16 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, mve_pred16_t p)
+foo1 (float16_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
index 3fc935c889b..4b43f0f4be3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, mve_pred16_t p)
+foo (float32_t const *base, mve_pred16_t p)
 {
   return vld1q_z_f32 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, mve_pred16_t p)
+foo1 (float32_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
index 49cc81092f3..a65c10c5fc1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
 {
   return vld1q_z_s16 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, mve_pred16_t p)
+foo1 (int16_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
index ec317cd70e8..31749046fc6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, mve_pred16_t p)
+foo (int32_t const *base, mve_pred16_t p)
 {
   return vld1q_z_s32 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, mve_pred16_t p)
+foo1 (int32_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
index 538c140e78e..990522faee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vld1q_z_s8 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base, mve_pred16_t p)
+foo1 (int8_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
index e5e588a187e..8a41b42306c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
 {
   return vld1q_z_u16 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, mve_pred16_t p)
+foo1 (uint16_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
index 999beefa7e8..67b200f6028 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, mve_pred16_t p)
+foo (uint32_t const *base, mve_pred16_t p)
 {
   return vld1q_z_u32 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, mve_pred16_t p)
+foo1 (uint32_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
index 172053c7142..c113a0db3e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vld1q_z_u8 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base, mve_pred16_t p)
+foo1 (uint8_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
index db50f27bb60..e554cdab33d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float16x8x4_t
-foo (float16_t const * addr)
+foo (float16_t const *addr)
 {
   return vld4q_f16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
-/* { dg-final { scan-assembler "vld41.16"  }  } */
-/* { dg-final { scan-assembler "vld42.16"  }  } */
-/* { dg-final { scan-assembler "vld43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float16x8x4_t
-foo1 (float16_t const * addr)
+foo1 (float16_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
index de3fe0e79fc..be61054d331 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float32x4x4_t
-foo (float32_t const * addr)
+foo (float32_t const *addr)
 {
   return vld4q_f32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
-/* { dg-final { scan-assembler "vld41.32"  }  } */
-/* { dg-final { scan-assembler "vld42.32"  }  } */
-/* { dg-final { scan-assembler "vld43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float32x4x4_t
-foo1 (float32_t const * addr)
+foo1 (float32_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
index 41a9dd86a4f..f9cbc17da61 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int16x8x4_t
-foo (int16_t const * addr)
+foo (int16_t const *addr)
 {
   return vld4q_s16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
-/* { dg-final { scan-assembler "vld41.16"  }  } */
-/* { dg-final { scan-assembler "vld42.16"  }  } */
-/* { dg-final { scan-assembler "vld43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int16x8x4_t
-foo1 (int16_t const * addr)
+foo1 (int16_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
index 6f29c1b28c0..056e26023a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int32x4x4_t
-foo (int32_t const * addr)
+foo (int32_t const *addr)
 {
   return vld4q_s32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
-/* { dg-final { scan-assembler "vld41.32"  }  } */
-/* { dg-final { scan-assembler "vld42.32"  }  } */
-/* { dg-final { scan-assembler "vld43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int32x4x4_t
-foo1 (int32_t const * addr)
+foo1 (int32_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
index 7701facb55c..2bec51ab4f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int8x16x4_t
-foo (int8_t const * addr)
+foo (int8_t const *addr)
 {
   return vld4q_s8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
-/* { dg-final { scan-assembler "vld41.8"  }  } */
-/* { dg-final { scan-assembler "vld42.8"  }  } */
-/* { dg-final { scan-assembler "vld43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int8x16x4_t
-foo1 (int8_t const * addr)
+foo1 (int8_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
index 5a5e22d36d0..a2c98670174 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint16x8x4_t
-foo (uint16_t const * addr)
+foo (uint16_t const *addr)
 {
   return vld4q_u16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
-/* { dg-final { scan-assembler "vld41.16"  }  } */
-/* { dg-final { scan-assembler "vld42.16"  }  } */
-/* { dg-final { scan-assembler "vld43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint16x8x4_t
-foo1 (uint16_t const * addr)
+foo1 (uint16_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
index e40d9b24fb4..4bbe56db205 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint32x4x4_t
-foo (uint32_t const * addr)
+foo (uint32_t const *addr)
 {
   return vld4q_u32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
-/* { dg-final { scan-assembler "vld41.32"  }  } */
-/* { dg-final { scan-assembler "vld42.32"  }  } */
-/* { dg-final { scan-assembler "vld43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint32x4x4_t
-foo1 (uint32_t const * addr)
+foo1 (uint32_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
index 0d9abc36190..63353dba4b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint8x16x4_t
-foo (uint8_t const * addr)
+foo (uint8_t const *addr)
 {
   return vld4q_u8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
-/* { dg-final { scan-assembler "vld41.8"  }  } */
-/* { dg-final { scan-assembler "vld42.8"  }  } */
-/* { dg-final { scan-assembler "vld43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint8x16x4_t
-foo1 (uint8_t const * addr)
+foo1 (uint8_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
index 0f6c24dde0a..ce4255b8430 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base, uint16x8_t offset)
+foo (int8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset_s16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int8_t const * base, uint16x8_t offset)
+foo1 (int8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
index 4c1415d2c5f..cd5eb6b9e66 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base, uint32x4_t offset)
+foo (int8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int8_t const * base, uint32x4_t offset)
+foo1 (int8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
index 4108bbae3e2..5ef4a895082 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, uint8x16_t offset)
+foo (int8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset_s8 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base, uint8x16_t offset)
+foo1 (int8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
index 5d5b005a8f4..cfec3c66a54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base, uint16x8_t offset)
+foo (uint8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset_u16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint8_t const * base, uint16x8_t offset)
+foo1 (uint8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
index 7c2d92b7c58..f416a03c325 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base, uint32x4_t offset)
+foo (uint8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint8_t const * base, uint32x4_t offset)
+foo1 (uint8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
index 110f9db0296..e8bdd1eabb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, uint8x16_t offset)
+foo (uint8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset_u8 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base, uint8x16_t offset)
+foo1 (uint8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
index f0616b5ab8d..9a134609780 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_s16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
index 5bf291d4ba5..f47e02076b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
index a3798a01b5f..e2b58b47f1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_s8 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
index 578bd15c66e..2a1801fc941 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_u16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
index a58044af176..c415fe26ba8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
index 0e06833961b..90a19680999 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_u8 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
index 4403092b988..c54e04dbdda 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vldrbq_s16 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
index 95ea9364ffc..1623f53d971 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vldrbq_s32 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
index ec2f2176ccf..b1c141ae287 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vldrbq_s8 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
index 2fb297f92ad..203e2e9de83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vldrbq_u16 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
index dc555c1be2d..2005c3a2bbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vldrbq_u32 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
index d07b472a4ff..b4c109eb147 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vldrbq_u8 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
index 8bd08ab5cff..813f6a31a25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_s16 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
index 0309ff4111b..10e1dbf6ad9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_s32 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
index aed3c910063..de361d4c9a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_s8 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
index adcb0cfa2ae..ba4401045e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_u16 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
index 6b7bce60d62..adc88a59a71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_u32 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
index 54c61e74454..b13d9fb426f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_u8 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
index 6499f930c40..3539c1e40ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (uint64x2_t addr)
 {
-  return vldrdq_gather_base_s64 (addr, 8);
+  return vldrdq_gather_base_s64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
index 9a11638a261..2245df61a4e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t addr)
 {
-  return vldrdq_gather_base_u64 (addr, 8);
+  return vldrdq_gather_base_u64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
index a9b1f81b62d..e3fd7f16a31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (uint64x2_t * addr)
+foo (uint64x2_t *addr)
 {
-  return vldrdq_gather_base_wb_s64 (addr, 8);
+  return vldrdq_gather_base_wb_s64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
index e32a06695ae..161cf00b65e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64x2_t * addr)
+foo (uint64x2_t *addr)
 {
-  return vldrdq_gather_base_wb_u64 (addr, 8);
+  return vldrdq_gather_base_wb_u64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
index bb06cf88e32..0716baa635a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
 #include "arm_mve.h"
 
-int64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
+int64x2_t
+foo (uint64x2_t *addr, mve_pred16_t p)
 {
-    return vldrdq_gather_base_wb_z_s64 (addr, 1016, p);
+  return vldrdq_gather_base_wb_z_s64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
index 558115d49ef..242c7c06e27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
 #include "arm_mve.h"
 
-uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
+uint64x2_t
+foo (uint64x2_t *addr, mve_pred16_t p)
 {
-    return vldrdq_gather_base_wb_z_u64 (addr, 8, p);
+  return vldrdq_gather_base_wb_z_u64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
index d7455b49206..d451f4e693f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (uint64x2_t addr, mve_pred16_t p)
 {
-  return vldrdq_gather_base_z_s64 (addr, 8, p);
+  return vldrdq_gather_base_z_s64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
index 07f72d422b4..508db3ca538 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t addr, mve_pred16_t p)
 {
-  return vldrdq_gather_base_z_u64 (addr, 8, p);
+  return vldrdq_gather_base_z_u64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
index 1d2d904efc4..9431491f3fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset)
+foo (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset_s64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset)
+foo1 (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
index 49a3b134d2f..11c0872f5a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset)
+foo (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset_u64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset)
+foo1 (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
index 1ff5f2acd1b..f474cbef788 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z_s64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
index 63b2254d171..19136d7f451 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z_u64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
index 4feb9c06fcd..ad11d8fa5cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset)
+foo (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset_s64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset)
+foo1 (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
index 999735039c8..a466494974b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset)
+foo (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset_u64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset)
+foo1 (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
index 77303a47a08..3555105d09e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z_s64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
index 0273b242031..f7cfbfcddb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z_u64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
index 05bef418d82..87c746f4ad7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base)
+foo (float16_t const *base)
 {
   return vldrhq_f16 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
index 525e54c72f5..287276e41f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset)
+foo (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset_f16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset)
+foo1 (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
index 47ef03445b4..e2493a62b3a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset)
+foo (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset_s16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset)
+foo1 (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
index 39379aaedd3..5d1e348cc86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset)
+foo (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset)
+foo1 (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
index fa345e24b48..6d5f6f877dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset)
+foo (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset_u16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset)
+foo1 (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
index b888660dc37..c39afbe6119 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset)
+foo (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset)
+foo1 (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
index 7ee84232f04..53c673e3644 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_f16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
index 9b354fad50d..1e68a77824e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_s16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
index 0e252291944..06c208f31c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
index 763e33d90bb..f50f026b00e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_u16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
index 36baa252aa4..eff32dc6718 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
index 843904a7041..f8468be41fa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset)
+foo (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset_f16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset)
+foo1 (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
index 6d013c835b5..ac2491ea143 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset)
+foo (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset_s16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset)
+foo1 (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
index 5ec8e8c1dc8..6919b3a3cc2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset)
+foo (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset)
+foo1 (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
index fa5f3d04548..7e8fdf3799d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset)
+foo (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset_u16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset)
+foo1 (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
index 227b18d7864..de2d22d985d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset)
+foo (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset)
+foo1 (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
index cae37837c7e..a55ada003ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_f16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
index 1aff290a6b0..ee57d77e3db 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_s16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
index 92ee073adf9..9f8963f56bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
index 792510d3639..90be7020ac2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_u16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
index 8ae845418e8..0ff6d021b51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
index 7c977b6a699..107ce22856b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base)
+foo (int16_t const *base)
 {
   return vldrhq_s16 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
index 229b52163fa..5cc864c38e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base)
+foo (int16_t const *base)
 {
   return vldrhq_s32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.s32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
index 07f6d9e3944..12f807da03b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
 {
   return vldrhq_u16 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
index cd24f01831f..5d4f34f9789 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
 {
   return vldrhq_u32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.u32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
index dd0fc9c7b73..582061bbab3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, mve_pred16_t p)
+foo (float16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_f16 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
index 36d3458d95c..dc32460ccdd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_s16 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
index 9c67b479be7..15dd77cb36c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_s32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.s32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
index 26354b5971a..91ab2caf1c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_u16 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
index 948fe5ee5b4..1682ec1987a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_u32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.u32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
index 143079aa23f..9cf47332b38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base)
+foo (float32_t const *base)
 {
   return vldrwq_f32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
index 5e0faaad8dd..c3f052efbc6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t addr)
 {
-  return vldrwq_gather_base_f32 (addr, 4);
+  return vldrwq_gather_base_f32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
index 8ca44199e3e..f2dbcfb9f6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (uint32x4_t addr)
 {
-  return vldrwq_gather_base_s32 (addr, 4);
+  return vldrwq_gather_base_s32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
index 3c3e90f1c0a..0926689805f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t addr)
 {
-  return vldrwq_gather_base_u32 (addr, 4);
+  return vldrwq_gather_base_u32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
index 8e2994f75d7..f9cd0a3ffe0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
 {
-  return vldrwq_gather_base_wb_f32 (addr, 8);
+  return vldrwq_gather_base_wb_f32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
index e5054738b75..b8f16969a31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
 {
-  return vldrwq_gather_base_wb_s32 (addr, 8);
+  return vldrwq_gather_base_wb_s32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
index 7f39414143b..387d0115f46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
 {
-  return vldrwq_gather_base_wb_u32 (addr, 8);
+  return vldrwq_gather_base_wb_u32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
index 1e57ca40739..bea7ecdee83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
@@ -1,18 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_wb_z_f32 (addr, 8, p);
+  return vldrwq_gather_base_wb_z_f32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
index f8d77fdfd5b..4469ac14a0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
@@ -1,18 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_wb_z_s32 (addr, 8, p);
+  return vldrwq_gather_base_wb_z_s32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
index 8a0e109c70c..9d4d81b3afe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
@@ -1,18 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_wb_z_u32 (addr, 8, p);
+  return vldrwq_gather_base_wb_z_u32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
index 81aac523728..905000a31a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_z_f32 (addr, 4, p);
+  return vldrwq_gather_base_z_f32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
index fec49bbde06..3ee6a219b80 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (uint32x4_t addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_z_s32 (addr, 4, p);
+  return vldrwq_gather_base_z_s32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
index b64a11d6620..488adf58b78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_z_u32 (addr, 4, p);
+  return vldrwq_gather_base_z_u32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
index 6a4ea041137..a513452a12d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset)
+foo (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset_f32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset)
+foo1 (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
index ee15fa4a0b0..57ad6583153 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset)
+foo (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset)
+foo1 (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
index d344779058f..30fc36c6f97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset)
+foo (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset)
+foo1 (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
index 93253119418..1f84edcdb8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z_f32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
index 4537427bef3..3fe5a986cc3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
index e59c4c996bf..087e5d0ce1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
index 1ba2cb0ccde..bed16f5fa72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset)
+foo (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset_f32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset)
+foo1 (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
index 39d976bb676..e6c589020f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset)
+foo (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset)
+foo1 (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
index 971f482dfff..8e287da0dbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset)
+foo (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset)
+foo1 (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
index e4110cd50aa..f69d67fd2aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z_f32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
index 71dd8a757ce..3aff6de03b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
index f95d6f0f708..ed8873d0c53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
index 860dd324d25..87c3ac9f9d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base)
+foo (int32_t const *base)
 {
   return vldrwq_s32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
index 513ed49fb6e..5b560c534a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base)
+foo (uint32_t const *base)
 {
   return vldrwq_u32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
index 3e0a6a60bcf..14a61fcfbd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, mve_pred16_t p)
+foo (float32_t const *base, mve_pred16_t p)
 {
   return vldrwq_z_f32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
index 82b914885b5..5c90707becc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, mve_pred16_t p)
+foo (int32_t const *base, mve_pred16_t p)
 {
   return vldrwq_z_s32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
index 6a66e167881..16b50335fe7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, mve_pred16_t p)
+foo (uint32_t const *base, mve_pred16_t p)
 {
   return vldrwq_z_u32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
index 64650e26bcb..5180667658e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8x2_t value)
+foo (float16_t *addr, float16x8x2_t value)
 {
-  vst2q_f16 (addr, value);
+  return vst2q_f16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
-/* { dg-final { scan-assembler "vst21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8x2_t value)
+foo1 (float16_t *addr, float16x8x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
index 8840afb867d..3e6f5b0ed75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4x2_t value)
+foo (float32_t *addr, float32x4x2_t value)
 {
-  vst2q_f32 (addr, value);
+  return vst2q_f32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
-/* { dg-final { scan-assembler "vst21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4x2_t value)
+foo1 (float32_t *addr, float32x4x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
index 15182c5eee0..1c939317779 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8x2_t value)
+foo (int16_t *addr, int16x8x2_t value)
 {
-  vst2q_s16 (addr, value);
+  return vst2q_s16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
-/* { dg-final { scan-assembler "vst21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8x2_t value)
+foo1 (int16_t *addr, int16x8x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
index 11c92463ae4..28c8e078942 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4x2_t value)
+foo (int32_t *addr, int32x4x2_t value)
 {
-  vst2q_s32 (addr, value);
+  return vst2q_s32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
-/* { dg-final { scan-assembler "vst21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4x2_t value)
+foo1 (int32_t *addr, int32x4x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
index 90257ae5dae..e882c01bd63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16x2_t value)
+foo (int8_t *addr, int8x16x2_t value)
 {
-  vst2q_s8 (addr, value);
+  return vst2q_s8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
-/* { dg-final { scan-assembler "vst21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16x2_t value)
+foo1 (int8_t *addr, int8x16x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
index a8a7c49757a..0cfbd6b9902 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8x2_t value)
+foo (uint16_t *addr, uint16x8x2_t value)
 {
-  vst2q_u16 (addr, value);
+  return vst2q_u16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
-/* { dg-final { scan-assembler "vst21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8x2_t value)
+foo1 (uint16_t *addr, uint16x8x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
index b5d78180995..ea46a5969d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4x2_t value)
+foo (uint32_t *addr, uint32x4x2_t value)
 {
-  vst2q_u32 (addr, value);
+  return vst2q_u32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
-/* { dg-final { scan-assembler "vst21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4x2_t value)
+foo1 (uint32_t *addr, uint32x4x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
index 4e7d6fea7ed..895c2ccf425 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16x2_t value)
+foo (uint8_t *addr, uint8x16x2_t value)
 {
-  vst2q_u8 (addr, value);
+  return vst2q_u8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
-/* { dg-final { scan-assembler "vst21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16x2_t value)
+foo1 (uint8_t *addr, uint8x16x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
index 0da66894e2c..94066089f58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (float16_t * addr, float16x8x4_t value)
+foo (float16_t *addr, float16x8x4_t value)
 {
-  vst4q_f16 (addr, value);
+  return vst4q_f16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8x4_t value)
+foo1 (float16_t *addr, float16x8x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
-
-void
-foo2 (float16_t * addr, float16x8x4_t value)
-{
-  vst4q_f16 (addr, value);
-  addr += 32;
-  vst4q_f16 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
index c1614bd10fc..0150ba7ca56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (float32_t * addr, float32x4x4_t value)
+foo (float32_t *addr, float32x4x4_t value)
 {
-  vst4q_f32 (addr, value);
+  return vst4q_f32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4x4_t value)
+foo1 (float32_t *addr, float32x4x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
-
-void
-foo2 (float32_t * addr, float32x4x4_t value)
-{
-  vst4q_f32 (addr, value);
-  addr += 16;
-  vst4q_f32 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
index e1250449bee..8c9df15b3c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (int16_t * addr, int16x8x4_t value)
+foo (int16_t *addr, int16x8x4_t value)
 {
-  vst4q_s16 (addr, value);
+  return vst4q_s16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8x4_t value)
+foo1 (int16_t *addr, int16x8x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
-
-void
-foo2 (int16_t * addr, int16x8x4_t value)
-{
-  vst4q_s16 (addr, value);
-  addr += 32;
-  vst4q_s16 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
index e6e1272744e..1a1a9797360 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (int32_t * addr, int32x4x4_t value)
+foo (int32_t *addr, int32x4x4_t value)
 {
-  vst4q_s32 (addr, value);
+  return vst4q_s32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4x4_t value)
+foo1 (int32_t *addr, int32x4x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
-
-void
-foo2 (int32_t * addr, int32x4x4_t value)
-{
-  vst4q_s32 (addr, value);
-  addr += 16;
-  vst4q_s32 (addr, value); 
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
index 16eb488ff99..d23032a73bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (int8_t * addr, int8x16x4_t value)
+foo (int8_t *addr, int8x16x4_t value)
 {
-  vst4q_s8 (addr, value);
+  return vst4q_s8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16x4_t value)
+foo1 (int8_t *addr, int8x16x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
-
-void
-foo2 (int8_t * addr, int8x16x4_t value)
-{
-  vst4q_s8 (addr, value);
-  addr += 16*4;
-  vst4q_s8 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
index afd60306d0d..76cc4311e1b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8x4_t value)
+foo (uint16_t *addr, uint16x8x4_t value)
 {
-  vst4q_u16 (addr, value);
+  return vst4q_u16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8x4_t value)
+foo1 (uint16_t *addr, uint16x8x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
-
-void
-foo2 (uint16_t * addr, uint16x8x4_t value)
-{
-  vst4q_u16 (addr, value);
-  addr += 32;
-  vst4q_u16 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
index 755dd689dff..e5f62858eee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4x4_t value)
+foo (uint32_t *addr, uint32x4x4_t value)
 {
-  vst4q_u32 (addr, value);
+  return vst4q_u32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4x4_t value)
+foo1 (uint32_t *addr, uint32x4x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
-
-void
-foo2 (uint32_t * addr, uint32x4x4_t value)
-{
-  vst4q_u32 (addr, value);
-  addr += 16;
-  vst4q_u32 (addr, value); 
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
index 0b28451df55..923cd0d3b10 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16x4_t value)
+foo (uint8_t *addr, uint8x16x4_t value)
 {
-  vst4q_u8 (addr, value);
+  return vst4q_u8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16x4_t value)
+foo1 (uint8_t *addr, uint8x16x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
-
-void
-foo2 (uint8_t * addr, uint8x16x4_t value)
-{
-  vst4q_u8 (addr, value);
-  addr += 16*4;
-  vst4q_u8 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
index ad74d8aa2e9..19804443e01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int8_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p_s16 (addr, value, p);
+  return vstrbq_p_s16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int8_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
index 46fd4549ffb..26be212770b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int8_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p_s32 (addr, value, p);
+  return vstrbq_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int8_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
index 8e70b9eb098..a0d08772a50 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p_s8 (addr, value, p);
+  return vstrbq_p_s8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
index 180f9033edd..bc02c59887a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint8_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p_u16 (addr, value, p);
+  return vstrbq_p_u16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
index 1b944fc9ffc..1215d5f0978 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint8_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p_u32 (addr, value, p);
+  return vstrbq_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
index 7e73cbff84e..a88234e411d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p_u8 (addr, value, p);
+  return vstrbq_p_u8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
index 4d12bc2cd19..1e88d3aa600 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int16x8_t value)
+foo (int8_t *base, int16x8_t value)
 {
-  vstrbq_s16 (addr, value);
+  return vstrbq_s16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int16x8_t value)
+foo1 (int8_t *base, int16x8_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
index 750413f35ae..12764bf3041 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int32x4_t value)
+foo (int8_t *base, int32x4_t value)
 {
-  vstrbq_s32 (addr, value);
+  return vstrbq_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int32x4_t value)
+foo1 (int8_t *base, int32x4_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
index 7ffb2c51976..05a9e5c42ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16_t value)
+foo (int8_t *base, int8x16_t value)
 {
-  vstrbq_s8 (addr, value);
+  return vstrbq_s8 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value)
+foo1 (int8_t *base, int8x16_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
index f59fa349cc0..052c3f85b75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_s16 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_s16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
index 737c1008976..57410e46a8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_s32 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
index 8b2d06807b4..c3cdefdf078 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_s8 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_s8 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
index 0adccaac39c..0868cc2248b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_u16 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_u16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
index 308119294df..9d769941569 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_u32 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
index 28b2ca4b83a..4586535d600 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_u8 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_u8 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
index e6cf1828b33..179b96f4973 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint16x8_t offset, int16x8_t value)
+foo (int8_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrbq_scatter_offset_s16 (base, offset, value);
+  return vstrbq_scatter_offset_s16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int8_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
index 052e02a7cf9..e7b7767c9f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint32x4_t offset, int32x4_t value)
+foo (int8_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrbq_scatter_offset_s32 (base, offset, value);
+  return vstrbq_scatter_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int8_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
index 523f318e73c..f47bdd1a630 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint8x16_t offset, int8x16_t value)
+foo (int8_t *base, uint8x16_t offset, int8x16_t value)
 {
-  vstrbq_scatter_offset_s8 (base, offset, value);
+  return vstrbq_scatter_offset_s8 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value)
+foo1 (int8_t *base, uint8x16_t offset, int8x16_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
index 49d4d31ad21..90e8cf351f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint8_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrbq_scatter_offset_u16 (base, offset, value);
+  return vstrbq_scatter_offset_u16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
index 0012852298c..e5449aa0942 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint8_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrbq_scatter_offset_u32 (base, offset, value);
+  return vstrbq_scatter_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
index e54422a1afe..06c8c45e877 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t offset, uint8x16_t value)
 {
-  vstrbq_scatter_offset_u8 (base, offset, value);
+  return vstrbq_scatter_offset_u8 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value)
+foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
index 9fa9d18c6a1..0b350e2491b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint16x8_t value)
+foo (uint8_t *base, uint16x8_t value)
 {
-  vstrbq_u16 (addr, value);
+  return vstrbq_u16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint16x8_t value)
+foo1 (uint8_t *base, uint16x8_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
index e535aa275ef..2f809356420 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint32x4_t value)
+foo (uint8_t *base, uint32x4_t value)
 {
-  vstrbq_u32 (addr, value);
+  return vstrbq_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint32x4_t value)
+foo1 (uint8_t *base, uint32x4_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
index 93771aabcbd..deeea98dda5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t value)
 {
-  vstrbq_u8 (addr, value);
+  return vstrbq_u8 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value)
+foo1 (uint8_t *base, uint8x16_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
index 74e2617c380..a41217b24f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8_t value)
+foo (float16_t *base, float16x8_t value)
 {
-  vstrhq_f16 (addr, value);
+  return vstrhq_f16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value)
+foo1 (float16_t *base, float16x8_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
index 227da4f10aa..8398a60023d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p_f16 (addr, value, p);
+  return vstrhq_p_f16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
index f3ba71f0ce1..ee1026801be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p_s16 (addr, value, p);
+  return vstrhq_p_s16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
index dab646706ce..b8490209644 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p_s32 (addr, value, p);
+  return vstrhq_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
index e575c70cc44..59fb73cef19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p_u16 (addr, value, p);
+  return vstrhq_p_u16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
index e863e284c3c..ed66db7f8ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p_u32 (addr, value, p);
+  return vstrhq_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
index 5e47fb4e1a6..972d733c5bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8_t value)
+foo (int16_t *base, int16x8_t value)
 {
-  vstrhq_s16 (addr, value);
+  return vstrhq_s16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value)
+foo1 (int16_t *base, int16x8_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
index 73e01c9acfb..f260c61c3a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int32x4_t value)
+foo (int16_t *base, int32x4_t value)
 {
-  vstrhq_s32 (addr, value);
+  return vstrhq_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int32x4_t value)
+foo1 (int16_t *base, int32x4_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
index d29bd08ad0a..794d75e76ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_offset_f16 (base, offset, value);
+  return vstrhq_scatter_offset_f16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
index 79d9827b378..1fd5a0773dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_f16 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_f16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
index 1b401d4c5b7..34c44a90541 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_s16 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_s16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
index afb325b9789..2a84b28a3f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_s32 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
index 73bee831282..f1c875657ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_u16 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_u16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
index bae7c2d14c2..913fd8d5591 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_u32 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
index bf3c03a85c6..b322d0fa02e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_offset_s16 (base, offset, value);
+  return vstrhq_scatter_offset_s16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
index 0591ab55c07..49fcc3a382b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_offset_s32 (base, offset, value);
+  return vstrhq_scatter_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
index 0a2fa1f410e..b5de540a74c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_offset_u16 (base, offset, value);
+  return vstrhq_scatter_offset_u16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
index 809a44dee16..7808f25d4a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_offset_u32 (base, offset, value);
+  return vstrhq_scatter_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
index 1dcb1f7692d..6d57a22fe41 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_shifted_offset_f16 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_f16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
index c46eec95adf..2e77dd492a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
index 7e9a549e8c2..1c83a13ffdf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
index 502b4b00e2a..6d786de4379 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
index 151145ce174..fd73168ddbb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
index 14efd952593..689195ce603 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
index e5142ed85f7..0edacd938f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_shifted_offset_s16 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_s16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
index 431808f9008..ebda2faec92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_shifted_offset_s32 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
index f93e5d51913..abe8bbf8045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_shifted_offset_u16 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_u16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
index fc250706fa8..a01b04bd940 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_shifted_offset_u32 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
index f7b3ef1012b..85f5790ff49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t value)
 {
-  vstrhq_u16 (addr, value);
+  return vstrhq_u16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
index 8e01fd10032..d0958e22222 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t value)
 {
-  vstrhq_u32 (addr, value);
+  return vstrhq_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit 732102a21b75c972129c9589b491451e0b0289b5
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Thu Mar 23 15:36:37 2023

    arm: Fix vstrwq* backend + testsuite
    
    Hi all,
    
    this patch fixes the vstrwq* MVE instrinsics failing to emit the
    correct sequence of instruction due to a missing predicate. Also the
    immediate range is fixed to be multiples of 2 up between [-252, 252].
    
    Best Regards
    
      Andrea
    
    gcc/ChangeLog:
    
            * config/arm/constraints.md (mve_vldrd_immediate): Move it to
            predicates.md.
            (Ri): Move constraint definition from predicates.md.
            (Rl): Define new constraint.
            * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Add
            missing constraint.
            (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
            for op 1, use mve_vstrw_immediate predicate and Rl constraint for
            op 2. Fix asm output spacing.
            (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing constraint.
            * config/arm/predicates.md (Ri) Move constraint to constraints.md
            (mve_vldrd_immediate): Move it from
            constraints.md.
            (mve_vstrw_immediate): New predicate.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.

diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index db316d81dcc..10e7c9b9c32 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -102,10 +102,6 @@
        (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
 				       || (ival == 4) || (ival == 8))")))
 
-;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
-(define_predicate "mve_vldrd_immediate"
-  (match_test "satisfies_constraint_Ri (op)"))
-
 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  "The VFP registers @code{s0}-@code{s31}.")
 
@@ -566,6 +562,22 @@
  (match_code "symbol_ref")
 )
 
+;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
+(define_constraint "Ri"
+  "@internal In Thumb-2 state a constant is multiple of 8 and in range
+   of -/+ 1016 for MVE"
+  (and (match_code "const_int")
+       (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
+		    && ((ival % 8) == 0)")))
+
+;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
+(define_constraint "Rl"
+  "@internal In Thumb-2 state a constant is multiple of 2 and in range
+   of -/+ 252 for MVE"
+  (and (match_code "const_int")
+       (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252)
+		    && ((ival % 2) == 0)")))
+
 (define_memory_constraint "Uz"
  "@internal
   A memory access that is accessible as an LDC/STC operand"
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index b02ecfd8c7f..7ac7e2e0710 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -9352,7 +9352,7 @@
 		[(match_operand:V4SI 1 "s_register_operand" "0")
 		 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
 		 (match_operand:V4SI 3 "s_register_operand" "w")
-		 (match_operand:V4BI 4 "vpr_register_operand")]
+		 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
 	VSTRWSBWBQ))
    (set (match_operand:V4SI 0 "s_register_operand" "=w")
 	(unspec:V4SI [(match_dup 1) (match_dup 2)]
@@ -9401,9 +9401,9 @@
  [(set (mem:BLK (scratch))
        (unspec:BLK
 		[(match_operand:V4SI 1 "s_register_operand" "0")
-		 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
+		 (match_operand:SI 2 "mve_vstrw_immediate" "Rl")
 		 (match_operand:V4SF 3 "s_register_operand" "w")
-		 (match_operand:V4BI 4 "vpr_register_operand")]
+		 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
 	VSTRWQSBWB_F))
    (set (match_operand:V4SI 0 "s_register_operand" "=w")
 	(unspec:V4SI [(match_dup 1) (match_dup 2)]
@@ -9415,7 +9415,7 @@
    ops[0] = operands[1];
    ops[1] = operands[2];
    ops[2] = operands[3];
-   output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
+   output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops);
    return "";
 }
   [(set_attr "length" "8")])
@@ -9454,7 +9454,7 @@
 		[(match_operand:V2DI 1 "s_register_operand" "0")
 		 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
 		 (match_operand:V2DI 3 "s_register_operand" "w")
-		 (match_operand:HI 4 "vpr_register_operand")]
+		 (match_operand:HI 4 "vpr_register_operand" "Up")]
 	 VSTRDSBWBQ))
    (set (match_operand:V2DI 0 "s_register_operand" "=w")
 	(unspec:V2DI [(match_dup 1) (match_dup 2)]
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 67f2fdb4f8f..b6eb12632d4 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -73,13 +73,13 @@
 (define_predicate "mve_imm_selective_upto_8"
   (match_test "satisfies_constraint_Rg (op)"))
 
-;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
-(define_constraint "Ri"
-  "@internal In Thumb-2 state a constant is multiple of 8 and in range
-   of -/+ 1016 for MVE"
-  (and (match_code "const_int")
-       (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
-		    && ((ival % 8) == 0)")))
+;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
+(define_predicate "mve_vldrd_immediate"
+  (match_test "satisfies_constraint_Ri (op)"))
+
+;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
+(define_predicate "mve_vstrw_immediate"
+  (match_test "satisfies_constraint_Rl (op)"))
 
 ; Predicate for stack protector guard's address in
 ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
index 8aa04fcbdee..e92ecb0f6bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value)
+foo (float32_t *base, float32x4_t value)
 {
-  vstrwq_f32 (addr, value);
+  return vstrwq_f32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value)
+foo1 (float32_t *base, float32x4_t value)
 {
-  vstrwq (addr, value);
+  return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
index 411de6414f7..f1992a67736 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p_f32 (addr, value, p);
+  return vstrwq_p_f32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p (addr, value, p);
+  return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
index 3b042814d27..a00aeabb9fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p_s32 (addr, value, p);
+  return vstrwq_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p (addr, value, p);
+  return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
index b9e92204c88..05fded8aac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p_u32 (addr, value, p);
+  return vstrwq_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p (addr, value, p);
+  return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
index c7b3d91a972..b2a184f3c66 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value)
+foo (int32_t *base, int32x4_t value)
 {
-  vstrwq_s32 (addr, value);
+  return vstrwq_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value)
+foo1 (int32_t *base, int32x4_t value)
 {
-  vstrwq (addr, value);
+  return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
index f8b56917295..c80e8d9cdc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, float32x4_t value)
 {
-  vstrwq_scatter_base_f32 (addr, 8, value);
+  return vstrwq_scatter_base_f32 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, float32x4_t value)
 {
-  vstrwq_scatter_base (addr, 8, value);
+  return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
index 4a75e6503e1..237843c0661 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p_f32 (addr, 8, value, p);
+  return vstrwq_scatter_base_p_f32 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p (addr, 8, value, p);
+  return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
index 5ac4f300a7d..5f4f4a09664 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p_s32 (addr, 8, value, p);
+  return vstrwq_scatter_base_p_s32 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p (addr, 8, value, p);
+  return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
index e564f26b9c7..8c5cf63f861 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p_u32 (addr, 8, value, p);
+  return vstrwq_scatter_base_p_u32 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p (addr, 8, value, p);
+  return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
index 5bba36db5cb..5208cf4f808 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, int32x4_t value)
 {
-  vstrwq_scatter_base_s32 (addr, 8, value);
+  return vstrwq_scatter_base_s32 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, int32x4_t value)
 {
-  vstrwq_scatter_base (addr, 8, value);
+  return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
index 1dcbb5a739c..e728db2b9f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, uint32x4_t value)
 {
-  vstrwq_scatter_base_u32 (addr, 8, value);
+  return vstrwq_scatter_base_u32 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, uint32x4_t value)
 {
-  vstrwq_scatter_base (addr, 8, value);
+  return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
index b2cc6e555ae..e481191aa57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, float32x4_t value)
+foo (uint32x4_t *addr, float32x4_t value)
 {
-  vstrwq_scatter_base_wb_f32 (addr, 8, value);
+  return vstrwq_scatter_base_wb_f32 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, float32x4_t value)
+foo1 (uint32x4_t *addr, float32x4_t value)
 {
-  vstrwq_scatter_base_wb (addr, 8, value);
+  return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
index 4befd49d7b9..8d217d46230 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
index dfb1827c4f0..afc47adcd7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
index 4eb78c600be..65191c2f1ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
index 618dbaf5aa6..b6a9f6cd1f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, int32x4_t value)
+foo (uint32x4_t *addr, int32x4_t value)
 {
-  vstrwq_scatter_base_wb_s32 (addr, 8, value);
+  return vstrwq_scatter_base_wb_s32 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, int32x4_t value)
+foo1 (uint32x4_t *addr, int32x4_t value)
 {
-  vstrwq_scatter_base_wb (addr, 8, value);
+  return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
index 912a4590cf5..81a278f4e2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, uint32x4_t value)
+foo (uint32x4_t *addr, uint32x4_t value)
 {
-  vstrwq_scatter_base_wb_u32 (addr, 8, value);
+  return vstrwq_scatter_base_wb_u32 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, uint32x4_t value)
+foo1 (uint32x4_t *addr, uint32x4_t value)
 {
-  vstrwq_scatter_base_wb (addr, 8, value);
+  return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
index c14d3ce607b..b81df68aa21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_offset_f32 (base, offset, value);
+  return vstrwq_scatter_offset_f32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_offset (base, offset, value);
+  return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
index 115be56ec00..8aee42f76a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p_f32 (base, offset, value, p);
+  return vstrwq_scatter_offset_p_f32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p (base, offset, value, p);
+  return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
index 48652af3cff..9c74ae7a8d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p_s32 (base, offset, value, p);
+  return vstrwq_scatter_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p (base, offset, value, p);
+  return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
index dcd42ec453f..015a202b548 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p_u32 (base, offset, value, p);
+  return vstrwq_scatter_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p (base, offset, value, p);
+  return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
index 04672e5a4aa..df373111b78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_offset_s32 (base, offset, value);
+  return vstrwq_scatter_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_offset (base, offset, value);
+  return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
index e3d312550c6..a74696ca273 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_offset_u32 (base, offset, value);
+  return vstrwq_scatter_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_offset (base, offset, value);
+  return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
index b20c4c7ed3a..1c9b29a57b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_shifted_offset_f32 (base, offset, value);
+  return vstrwq_scatter_shifted_offset_f32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_shifted_offset (base, offset, value);
+  return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
index 1682f702dc6..08e1572854e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
index eef6ea6e196..2b8f8a7d61f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
index b11e7e04dc4..3e4e87bf79a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
index 8ac25c47554..7f25490a69a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_shifted_offset_s32 (base, offset, value);
+  return vstrwq_scatter_shifted_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_shifted_offset (base, offset, value);
+  return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
index 1ce0ddacc7a..a96220c4f6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_shifted_offset_u32 (base, offset, value);
+  return vstrwq_scatter_shifted_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_shifted_offset (base, offset, value);
+  return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
index 4aec9935b84..df554af79a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t value)
 {
-  vstrwq_u32 (addr, value);
+  return vstrwq_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t value)
 {
-  vstrwq (addr, value);
+  return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit 958a3c54645f2a47a188d17e2c43b5e56ba88430
Author: Andrea Corallo <andrea.corallo@arm.com>
Date:   Wed Apr 19 18:08:57 2023

    arm: Mve backend + testsuite fixes 2
    
    Hi all,
    
    this patch improves a number of MVE tests in the testsuite for more
    precise and better coverage using check-function-bodies instead of
    scan-assembler checks.  Also all intrusctions prescribed in the
    ACLE[1] are now checked.
    
    Also a number of simple fixes are done in the backend to fix
    capitalization and spacing.
    
    Best Regards
    
      Andrea
    
    [1] <https://github.com/ARM-software/acle>
    
    gcc/ChangeLog:
    
            * config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrev64q_f<mode>)
            (mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf)
            (mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_<supf><mode>)
            (mve_vrev64q_<supf><mode>, mve_vcvtq_from_f_<supf><mode>)
            (mve_vmovltq_<supf><mode>, mve_vmovlbq_<supf><mode>)
            (mve_vcvtpq_<supf><mode>, mve_vcvtnq_<supf><mode>)
            (mve_vcvtmq_<supf><mode>, mve_vcvtaq_<supf><mode>)
            (mve_vmvnq_n_<supf><mode>, mve_vrev16q_<supf>v16qi)
            (mve_vctp<mode1>qhi, mve_vbrsrq_n_f<mode>)
            (mve_vbrsrq_n_<supf><mode>, mve_vandq_f<mode>, mve_vbicq_f<mode>)
            (mve_vbicq_n_<supf><mode>, mve_vctp<mode1>q_mhi)
            (mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf)
            (mve_veorq_f<mode>, mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
            (mve_vmlsldavxq_s<mode>, mve_vornq_f<mode>, mve_vorrq_f<mode>)
            (mve_vrmlaldavhxq_sv4si, mve_vbicq_m_n_<supf><mode>)
            (mve_vcvtq_m_to_f_<supf><mode>, mve_vshlcq_<supf><mode>)
            (mve_vmvnq_m_<supf><mode>, mve_vpselq_<supf><mode>)
            (mve_vcvtbq_m_f16_f32v8hf, mve_vcvtbq_m_f32_f16v4sf)
            (mve_vcvttq_m_f16_f32v8hf, mve_vcvttq_m_f32_f16v4sf)
            (mve_vmlaldavq_p_<supf><mode>, mve_vmlsldavaq_s<mode>)
            (mve_vmlsldavaxq_s<mode>, mve_vmlsldavq_p_s<mode>)
            (mve_vmlsldavxq_p_s<mode>, mve_vmvnq_m_n_<supf><mode>)
            (mve_vorrq_m_n_<supf><mode>, mve_vpselq_f<mode>)
            (mve_vrev32q_m_fv8hf, mve_vrev32q_m_<supf><mode>)
            (mve_vrev64q_m_f<mode>, mve_vrmlaldavhaxq_sv4si)
            (mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhaxq_sv4si)
            (mve_vrmlsldavhq_p_sv4si, mve_vrmlsldavhxq_p_sv4si)
            (mve_vrev16q_m_<supf>v16qi, mve_vrmlaldavhq_p_<supf>v4si)
            (mve_vrmlsldavhaq_sv4si, mve_vandq_m_<supf><mode>)
            (mve_vbicq_m_<supf><mode>, mve_veorq_m_<supf><mode>)
            (mve_vornq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
            (mve_vandq_m_f<mode>, mve_vbicq_m_f<mode>, mve_veorq_m_f<mode>)
            (mve_vornq_m_f<mode>, mve_vorrq_m_f<mode>)
            (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn)
            (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn)
            (mve_vstrdq_scatter_base_wb_p_<supf>v2di) : Fix spacing and
            capitalization in the emitted asm.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/asrl.c: Use
            check-function-bodies instead of scan-assembler checks.  Use
            extern "C" for C++ testing.
            * gcc.target/arm/mve/intrinsics/lsll.c: Likewise.
            * gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise.
            * gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise.
            * gcc.target/arm/mve/intrinsics/sqshl.c: Likewise.
            * gcc.target/arm/mve/intrinsics/sqshll.c: Likewise.
            * gcc.target/arm/mve/intrinsics/srshr.c: Likewise.
            * gcc.target/arm/mve/intrinsics/srshrl.c: Likewise.
            * gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise.
            * gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise.
            * gcc.target/arm/mve/intrinsics/uqshl.c: Likewise.
            * gcc.target/arm/mve/intrinsics/uqshll.c: Likewise.
            * gcc.target/arm/mve/intrinsics/urshr.c: Likewise.
            * gcc.target/arm/mve/intrinsics/urshrl.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp16q.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise.

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 7ac7e2e0710..1d5721df3e8 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -134,7 +134,7 @@
 	 VRNDQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
+  "vpst\;vrintzt.f%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -232,7 +232,7 @@
 	 VREV64Q_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "vrev64.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -286,7 +286,7 @@
 	 VREV32Q_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev32.16 %q0, %q1"
+  "vrev32.16\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 ;;
@@ -299,7 +299,7 @@
 	 VCVTTQ_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtt.f32.f16 %q0, %q1"
+  "vcvtt.f32.f16\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -313,7 +313,7 @@
 	 VCVTBQ_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtb.f32.f16 %q0, %q1"
+  "vcvtb.f32.f16\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -327,7 +327,7 @@
 	 VCVTQ_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>       %q0, %q1"
+  "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -341,7 +341,7 @@
 	 VREV64Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "vrev64.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -355,7 +355,7 @@
 	 VCVTQ_FROM_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>       %q0, %q1"
+  "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 ;; [vqnegq_s])
@@ -517,7 +517,7 @@
 	 VMOVLTQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmovlt.<supf>%#<V_sz_elem>   %q0, %q1"
+  "vmovlt.<supf>%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -531,7 +531,7 @@
 	 VMOVLBQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmovlb.<supf>%#<V_sz_elem>   %q0, %q1"
+  "vmovlb.<supf>%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -545,7 +545,7 @@
 	 VCVTPQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -559,7 +559,7 @@
 	 VCVTNQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -573,7 +573,7 @@
 	 VCVTMQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -587,7 +587,7 @@
 	 VCVTAQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -601,7 +601,7 @@
 	 VMVNQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vmvn.i%#<V_sz_elem>  %q0, %1"
+  "vmvn.i%#<V_sz_elem>\t%q0, %1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -615,7 +615,7 @@
 	 VREV16Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev16.8 %q0, %q1"
+  "vrev16.8\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -643,7 +643,7 @@
 	VCTPQ))
   ]
   "TARGET_HAVE_MVE"
-  "vctp.<mode1> %1"
+  "vctp.<mode1>\t%1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -687,7 +687,7 @@
 	 VBRSRQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vbrsr.<V_sz_elem>  %q0, %q1, %2"
+  "vbrsr.<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -969,7 +969,7 @@
 	 VBRSRQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vbrsr.%#<V_sz_elem>	%q0, %q1, %2"
+  "vbrsr.%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1857,7 +1857,7 @@
 		   (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vand %q0, %q1, %q2"
+  "vand\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1871,7 +1871,7 @@
 			      (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vbic %q0, %q1, %q2"
+  "vbic\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1886,7 +1886,7 @@
 	 VBICQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vbic.i%#<V_sz_elem>	%q0, %2"
+  "vbic.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1960,7 +1960,7 @@
 	 VCTPQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vctpt.<mode1> %1"
+  "vpst\;vctpt.<mode1>\t%1"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -1975,7 +1975,7 @@
 	 VCVTBQ_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtb.f16.f32 %q0, %q2"
+  "vcvtb.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1990,7 +1990,7 @@
 	 VCVTTQ_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtt.f16.f32 %q0, %q2"
+  "vcvtt.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2004,7 +2004,7 @@
 		   (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2152,7 +2152,7 @@
 	 VMLALDAVXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vmlaldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2167,7 +2167,7 @@
 	 VMLSLDAVQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vmlsldav.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2182,7 +2182,7 @@
 	 VMLSLDAVXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vmlsldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2255,7 +2255,7 @@
 		   (match_operand:MVE_0 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vorn %q0, %q1, %q2"
+  "vorn\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2269,7 +2269,7 @@
 		   (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vorr %q0, %q1, %q2"
+  "vorr\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2419,7 +2419,7 @@
 	 VRMLALDAVHXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
+  "vrmlaldavhx.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2554,7 +2554,7 @@
 	 VBICQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vbict.i%#<V_sz_elem>	%q0, %2"
+  "vpst\;vbict.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -2599,7 +2599,7 @@
 	 VCVTQ_M_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>	 %q0, %q2"
+  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -2707,7 +2707,7 @@
 		   (match_dup 4)]
 	VSHLCQ))]
  "TARGET_HAVE_MVE"
- "vshlc %q0, %1, %4")
+ "vshlc\t%q0, %1, %4")
 
 ;;
 ;; [vabsq_m_s])
@@ -3265,7 +3265,7 @@
 	 VMVNQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmvnt %q0, %q2"
+  "vpst\;vmvnt\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3297,7 +3297,7 @@
 	 VPSELQ))
   ]
   "TARGET_HAVE_MVE"
-  "vpsel %q0, %q1, %q2"
+  "vpsel\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -3922,7 +3922,7 @@
 	 VCVTBQ_M_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtbt.f16.f32 %q0, %q2"
+  "vpst\;vcvtbt.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3938,7 +3938,7 @@
 	 VCVTBQ_M_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtbt.f32.f16 %q0, %q2"
+  "vpst\;vcvtbt.f32.f16\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3954,7 +3954,7 @@
 	 VCVTTQ_M_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvttt.f16.f32 %q0, %q2"
+  "vpst\;vcvttt.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3970,7 +3970,7 @@
 	 VCVTTQ_M_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvttt.f32.f16 %q0, %q2"
+  "vpst\;vcvttt.f32.f16\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4190,7 +4190,7 @@
 	 VMLALDAVQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vpst\;vmlaldavt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4221,7 +4221,7 @@
 	 VMLSLDAVAQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlsldava.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4237,7 +4237,7 @@
 	 VMLSLDAVAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlsldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4253,7 +4253,7 @@
 	 VMLSLDAVQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vpst\;vmlsldavt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4269,7 +4269,7 @@
 	 VMLSLDAVXQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vpst\;vmlsldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -4346,7 +4346,7 @@
 	 VMVNQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmvnt.i%#<V_sz_elem>	%q0, %2"
+  "vpst\;vmvnt.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -4377,7 +4377,7 @@
 	 VORRQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vorrt.i%#<V_sz_elem>	%q0, %2"
+  "vpst\;vorrt.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -4392,7 +4392,7 @@
 	 VPSELQ_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpsel %q0, %q1, %q2"
+  "vpsel\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4568,7 +4568,7 @@
 	 VREV32Q_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev32t.16 %q0, %q2"
+  "vpst\;vrev32t.16\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4584,7 +4584,7 @@
 	 VREV32Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev32t.%#<V_sz_elem>	%q0, %q2"
+  "vpst\;vrev32t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4600,7 +4600,7 @@
 	 VREV64Q_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev64t.%#<V_sz_elem>	%q0, %q2"
+  "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4616,7 +4616,7 @@
 	 VRMLALDAVHAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
+  "vrmlaldavhax.s32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4632,7 +4632,7 @@
 	 VRMLALDAVHXQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlaldavhxt.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4648,7 +4648,7 @@
 	 VRMLSLDAVHAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
+  "vrmlsldavhax.s32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4664,7 +4664,7 @@
 	 VRMLSLDAVHQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlsldavht.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4680,7 +4680,7 @@
 	 VRMLSLDAVHXQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlsldavhxt.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4905,7 +4905,7 @@
 	 VREV16Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev16t.8 %q0, %q2"
+  "vpst\;vrev16t.8\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4937,7 +4937,7 @@
 	 VRMLALDAVHQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlaldavht.<supf>32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4953,7 +4953,7 @@
 	 VRMLSLDAVHAQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
+  "vrmlsldavha.s32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -5122,7 +5122,7 @@
 	 VANDQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vandt %q0, %q2, %q3"
+  "vpst\;vandt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5139,7 +5139,7 @@
 	 VBICQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vbict %q0, %q2, %q3"
+  "vpst\;vbict\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5207,7 +5207,7 @@
 	 VEORQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;veort %q0, %q2, %q3"
+  "vpst\;veort\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5462,7 +5462,7 @@
 	 VORNQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vornt %q0, %q2, %q3"
+  "vpst\;vornt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5479,7 +5479,7 @@
 	 VORRQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vorrt %q0, %q2, %q3"
+  "vpst\;vorrt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -6651,7 +6651,7 @@
 	 VANDQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vandt %q0, %q2, %q3"
+  "vpst\;vandt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -6668,7 +6668,7 @@
 	 VBICQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vbict %q0, %q2, %q3"
+  "vpst\;vbict\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -6872,7 +6872,7 @@
 	 VEORQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;veort %q0, %q2, %q3"
+  "vpst\;veort\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -7025,7 +7025,7 @@
 	 VORNQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vornt %q0, %q2, %q3"
+  "vpst\;vornt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -7042,7 +7042,7 @@
 	 VORRQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vorrt %q0, %q2, %q3"
+  "vpst\;vorrt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -8485,7 +8485,7 @@
 	   (match_operand:HI 3 "vpr_register_operand" "Up")]
 	  VSTRDSSOQ))]
   "TARGET_HAVE_MVE"
-  "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]"
+  "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]"
   [(set_attr "length" "8")])
 
 ;;
@@ -8514,7 +8514,7 @@
 	   (match_operand:V2DI 2 "s_register_operand" "w")]
 	  VSTRDSSOQ))]
   "TARGET_HAVE_MVE"
-  "vstrd.64\t%q2, [%0, %q1, UXTW #3]"
+  "vstrd.64\t%q2, [%0, %q1, uxtw #3]"
   [(set_attr "length" "4")])
 
 ;;
@@ -9466,7 +9466,7 @@
    ops[0] = operands[1];
    ops[1] = operands[2];
    ops[2] = operands[3];
-   output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops);
+   output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops);
    return "";
 }
   [(set_attr "length" "8")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
index a2d5160e518..1aa576afae3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	asrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64_t
-asrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
 {
-  return asrl (longval3, x);
+  return asrl (value, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
index 9c1b62fb9f2..5542ac8c316 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	lsll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint64_t
-lsll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
 {
-  return lsll (longval3, x);
+  return lsll (value, shift);
+}
+
+/*
+**foo1:
+**	...
+**	lsll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+  return lsll (1, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
index 1f0a228e4b4..ea8c7a0ce4a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqrshr	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32_t
-sqrshr_reg (int32_t longval3, int32_t x)
+foo (int32_t value, int32_t shift)
 {
-  return sqrshr (longval3, x);
+  return sqrshr (value, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
index 2f1612cde77..affa12c526d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqrshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64_t
-sqrshrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
 {
-  return sqrshrl_sat48 (longval3, x);
+  return sqrshrl_sat48 (value, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
index 8cb8c74b268..e8c9c441163 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqshl	(?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-sqshl_imm (int32_t longval3)
+foo (int32_t value)
 {
-  return sqshl (longval3, 25);
+  return sqshl (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
index 016ef2a336e..03dc91f3758 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-sqshll_imm(int64_t value)
+foo (int64_t value)
 {
-  return sqshll (value, 21);
+  return sqshll (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 264f0bf09ce..94e3f42fd33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	srshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
 int32_t
-srshr_imm (int32_t longval3)
+foo (int32_t value)
 {
-  return srshr (longval3, 25);
+  return srshr (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index ab12d0da635..65f28ccbfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	srshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
 int64_t
-srshrl_imm(int64_t value)
+foo (int64_t value)
 {
-  return srshrl (value, 21);
+  return srshrl (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
index 0064aa19fbc..4b6fd041210 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqrshl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32_t
-uqrshl_reg (uint32_t longval3, int32_t x)
+foo (uint32_t value, int32_t shift)
 {
-  return uqrshl (longval3, x);
+  return uqrshl (value, shift);
+}
+
+/*
+**foo1:
+**	...
+**	uqrshl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32_t
+foo1 (int32_t shift)
+{
+  return uqrshl (1, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
index 24cd2324413..eaf36911eb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqrshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint64_t
-uqrshll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
 {
-  return uqrshll_sat48 (longval3, x);
+  return uqrshll_sat48 (value, shift);
+}
+
+/*
+**foo1:
+**	...
+**	uqrshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+  return uqrshll_sat48 (1, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index 9e6ff649805..b23c9d97ba6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqshl	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
 uint32_t
-uqshl_imm (uint32_t longval3)
+foo (uint32_t value)
 {
-  return uqshl (longval3, 21);
+  return uqshl (value, 1);
+}
+
+/*
+**foo1:
+**	...
+**	uqshl	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
+uint32_t
+foo1 ()
+{
+  return uqshl (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 52560721d6f..6a3d08eea75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
 uint64_t
-uqshll_imm(uint64_t value)
+foo (uint64_t value)
 {
-  return uqshll (value, 21);
+  return uqshll (value, 1);
+}
+
+/*
+**foo1:
+**	...
+**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
+uint64_t
+foo1 ()
+{
+  return uqshll (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index ec5d84bb009..23afcb8da4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint64_t
-urshr_imm (uint32_t longval3)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	urshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
+uint32_t
+foo (uint32_t value)
+{
+  return urshr (value, 1);
+}
+
+/*
+**foo1:
+**	...
+**	urshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
+uint32_t
+foo1 ()
 {
-  return urshr (longval3, 21);
+  return urshr (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index ea29412ab7a..8014371f47f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
 uint64_t
-urshrl_imm(uint64_t value)
+foo (uint64_t value)
 {
-  return urshrl (value, 21);
+  return urshrl (value, 1);
+}
+
+/*
+**foo1:
+**	...
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	...
+*/
+uint64_t
+foo1 ()
+{
+  return urshrl (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index 1bfc101d5e8..b262bf94d39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -1,23 +1,61 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m_s32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index f72fe34c33b..d349caed36a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -1,23 +1,61 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m_u32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index ff13841c581..5166993a355 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
   return vadciq_s32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
   return vadciq (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index e3560362225..080bd61d238 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
   return vadciq_u32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
   return vadciq (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 668c4fdc82c..5c2702a3142 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -1,23 +1,81 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m_s32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 368c7c5c5f2..a3c01710627 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -1,23 +1,81 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m_u32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index 9c8777c45ee..efe4f8c778b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -1,21 +1,73 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vadcq_s32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vadcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index 78f48da5107..af778be6917 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -1,21 +1,73 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vadcq_u32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vadcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
index 2303b598a28..cb1820347bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vandq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
index 905f2b410c0..1034bcbaa62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vandq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
index d061dbc390b..d6752a6fdc4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
index 77b2813dfad..fb8410d0b71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
index 2840a33b433..5797ffa9a16 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
index 2e8ec7e14de..d2ede670e40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
index 36226f6d9ac..76ed60c64a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
index 49f0502f607..b3f7833e546 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
index 194c7800a05..7d761c86622 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
index 9b27c44ee82..8fd17e4f258 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
index 86aa64fec96..9f3e9b0c078 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vandq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
index 907fe89ced8..ab0e9627fb9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vandq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
index 783ad042c87..980ba6b5f7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vandq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
index ae483869f11..fdd18e92476 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vandq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
index 532926d894a..01df1828788 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vandq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
index 4018308f66d..a4f0cec4483 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vandq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
index 6aa98910c7b..99c586d5604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
index fd74ee6eee7..eda9d618409 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
index d8821d59be7..f0159ee7668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
index 980b01436b6..09277b2d56b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
index 93dead71416..f1232168a7d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
index aa99c69bd84..836385f44f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
index 1178837d78a..06b5010738b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
index d46e2b235b9..37f4fc51f9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
index c15f1f91d07..38a1a4adafa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vbicq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
index c8659d460a0..224b535992b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vbicq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
index 39a12a9fba3..e197a2aa1e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
index 091027c4b19..b441e205a64 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
index 3d0d09859c1..4e2be3e4516 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-  return vbicq_m_n_s16 (a, 16, p);
+  return vbicq_m_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
-  return vbicq_m_n (a, 16, p);
+  return vbicq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
index 47a9459580b..d8beab58024 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
index 7c0c691fd46..34b62aa557f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vbicq_m_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vbicq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
index e97b17aa27d..60681e3f045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
index 31a9e986b8d..c30658cf34c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
index 9e7a2940b42..6a861cb80e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
index b5e3253384c..c19caf53658 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
index 54370ab9548..443fcac6605 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
index cfcae7c74a9..31b1e22ef7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
index cd9856f629e..6bddc5c2d30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
index 6258727d82f..8726b2c57a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vbicq_n_s16 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i16" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
index be641abf556..015af580ed0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vbicq_n_s32 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i32" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
index 0b26ffda0dc..1ad03b9d17f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
   return vbicq_n_u16 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i16" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
index 47820bd184a..f3fe58fdf37 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
   return vbicq_n_u32 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i32" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
index 4ffacdd9733..6fd2a9e5c0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vbicq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
index 13fbff40746..37859e0dc6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vbicq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
index b9fba943a83..23db9afbcf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vbicq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
index 5d94a6396c4..9ed4e533e52 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vbicq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
index 893dc3deefc..abaf2a9cf7b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vbicq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
index bd5e9bc0197..4a47bb9d0e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vbicq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
index 975d60c713e..aa4812568d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
index e779224b5d5..db295df1cd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
index be554c4b2fb..2b7a3594dd7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
index e49aabf11d6..bf3b755f9ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
index c36cd1e6dc5..30df0904539 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
index 3b611591deb..eaa50a84fd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
index fce2fab3dd6..aea2592d9cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
index 672b3fb1e39..4ffee473ea6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
index 8f8d1bffd73..5985b7fed01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
index 336c8194cd7..1fff5a8bf95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
index f597d8ccb9d..a5221f8d864 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
index 76f0463af1e..99106e81a30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
index 30c6519236c..6bd4c8f4455 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
index 7052b8b5ff5..03ad4896029 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
index e19e02fbbd8..e65077001ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
index ce658432fd9..61ca255e431 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
index 9b8dea6e7e8..6dc4c657cbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, int32_t b)
 {
   return vbrsrq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
index cd335197c3b..810cd1b86ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, int32_t b)
 {
   return vbrsrq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
index efb17dd5250..109ccd72f0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vbrsrq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
index fda78e6aa4b..78b2db49c87 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vbrsrq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
index cd75a2b88fa..dfd485240ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vbrsrq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
index ef7708e33f8..59e1fcc0fd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vbrsrq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
index b33c533aeda..2d7792dd1cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vbrsrq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
index 91156bd4325..5f4398ddbe1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vbrsrq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
index 0710b59b1ab..d9d404ccf82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
index 67ab8cf80c9..8b176fe701c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
index ac0c13c0b4d..77f4f1852a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
index 98c87f17588..fc4a1c9c7e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
index 8159f5da999..10322ac328a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
index dbad2940616..72d8a9e23b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
index 04c812a2747..535af3600c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
index b3836936750..5f8f8c928fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
index 0339fbcafc6..89d8e2b9109 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -56,4 +56,4 @@ foo2 (float16x8_t a)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
index 2659f061cd9..1575966073d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp16q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.16"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp16q (a);
+  return vctp16q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
index d901c9ece0d..a14fbe97f86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp16q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.16"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp16q_m (a, p);
+  return vctp16q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
index f54ecc33e4a..c53b6190019 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp32q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.32"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp32q (a);
+  return vctp32q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
index 3d2f101fb0c..6fa790d7039 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp32q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.32"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp32q_m (a, p);
+  return vctp32q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
index 8502ad3b600..dba63bae1a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp64q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.64"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp64q (a);
+  return vctp64q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
index 6f3d1c21d01..1faf8a0063c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp64q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.64"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp64q_m (a, p);
+  return vctp64q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
index 91283f82db1..56267fd861d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp8q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.8"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp8q (a);
+  return vctp8q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
index 2c640ba6801..937c33cbb83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp8q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.8"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp8q_m (a, p);
+  return vctp8q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
index ad8b7d9eb06..fcf4cf817ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
index 5649e342d1a..8aa640de6ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
index b73c3418758..8fdd3c1b1b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
index 56c04f9f782..246941e7523 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
index e2d70e8901f..c45ba6ccfbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtaq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvta.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
index d6fd45ae01e..baa20cc5f9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtaq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvta.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
index 8f3b12d9101..de4ea927385 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtaq_u16_f16 (a);
+  return vcvtaq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvta.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
index 45e2916e288..93bf292980e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtaq_u32_f32 (a);
+  return vcvtaq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvta.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
index 26ff128217e..b046b7ad94d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
index 3a79e3aecd4..77a740867be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
index 1f26e7f52d4..b8a10822bdb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
index 987e524d789..51184231b7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
index f45e07de375..76b76a2f66e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtb.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b)
 {
   return vcvtbq_f16_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcvtb.f16.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
index 39471a0a43b..347d4129b99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtb.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a)
 {
   return vcvtbq_f32_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtb.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
index 6c8d9192417..0545d1e8e27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtbt.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcvtbq_m_f16_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f16.f32"  }  } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vcvtbq_m (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
index 91775436e67..1b220ddfa19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtbt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtbq_m_f32_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16"  }  } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
-  return vcvtbq_m (inactive, a, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
index 0dcdb19d1e4..2a3559d2522 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtbt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtbq_x_f32_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
index 75ff107ab15..b8f6ed855d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
index b364533e08d..61445594524 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
index 249ef0e92b1..3e57ba58d0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
index 52ff77ca4c5..8b8a1565332 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
index 70f43ddc220..4eafb5783b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtmq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtm.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
index c2f62cf0717..bd3bfc1b4bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtmq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtm.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
index 62e4acd73b5..a1917eaf11a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtmq_u16_f16 (a);
+  return vcvtmq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtm.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
index f7f59df1be9..c9f62479e85 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtmq_u32_f32 (a);
+  return vcvtmq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtm.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
index 22597fb9cb1..211c2d0df83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
index 17a583c2641..7ca2cb6eb15 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
index b6e296f29ea..df212089bf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
index 5f9909b5adb..8b5818fd029 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
index a7c3b66a2eb..67fa9cb720d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
index 38913a9e26c..26c0b09f7b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
index 42d9e5ea79c..ee2a64747a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
index 321fa35ceb3..cc61951abf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
index d66c058834e..39c00f6ed04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtnq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtn.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
index 3dec6661411..c371598db24 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtnq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtn.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
index 07637e84bf7..17ae06a57be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtnq_u16_f16 (a);
+  return vcvtnq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtn.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
index b6d5eb90493..4777b1b205a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
   return vcvtnq_u32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtn.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
index f552d633231..a9c91831881 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
index c3aa2e3daed..2ffb1d98736 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
index 9d9d12f9f2c..ce2ceb108b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
index e7df48de88d..c2c48ef1558 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
index c613fc8883d..f09c78b77c2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
index 7f4c7f600e5..7a3d7763406 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
index 192891021f0..f82103ca831 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
index 61858f7844a..7c848aa5157 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
index 8615e50bbaa..87258346b53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtpq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtp.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
index fed7a4b83f7..e4a7d0baaf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtpq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtp.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
index 37d1411067f..94edfcb0244 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtpq_u16_f16 (a);
+  return vcvtpq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtp.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
index fcea4c51885..b84501ca72c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtpq_u32_f32 (a);
+  return vcvtpq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtp.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
index 5d550772bfc..2b51cc56867 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
index 31823ab9528..6c4d6655300 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
index 0d1808c0fe8..2e663c8a472 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
index d73df212942..2d32425fdbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
index 560127b7c9f..9f1647c1ac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a)
 {
   return vcvtq_f16_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.s16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (int16x8_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
index f571c535778..6704626bd1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a)
 {
   return vcvtq_f16_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.u16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (uint16x8_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
index 898c74bfba4..898126468d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a)
 {
   return vcvtq_f32_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.s32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (int32x4_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
index a44add5d178..9e9aa1d703e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a)
 {
   return vcvtq_f32_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.u32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (uint32x4_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
index 45e9b045af6..b01a9a148c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_f16_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
index b50f57234c3..805e26e72fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_f16_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
index 4c1af180b58..7faa130fa3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_f32_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
index 49acef80489..589d4efa61b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_f32_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
index d5ba7a690a6..3e23f1d88d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_f16_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
index e53d7fa6ef1..f6f309cba25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_f16_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
index 58519c04ff4..e6ff2fd6f44 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_f32_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
index 782d1f9e259..7368f127aab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_m_n_f32_u32 (inactive, a, 16, p);
+  return vcvtq_m_n_f32_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_m_n (inactive, a, 16, p);
+  return vcvtq_m_n (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
index cd3f373aa77..edfb01203dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_s16_f16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
index d1ff5072223..8084160e7e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_s32_f32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
index 4bf12e8b64e..1d217387ac6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_u16_f16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
index 4d0b1bf7a7f..868a1bcc1b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_u32_f32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
index 606e43614ea..a998cdcb11a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
index 2204e7929ec..fdaeac453a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
index 1f814251c4f..f168d371615 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
index 13cd6f28884..83e5ae38106 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
index 565012e4e93..5c017221889 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a)
 {
   return vcvtq_n_f16_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (int16x8_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
index 95acc29683f..1080a5a0309 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a)
 {
   return vcvtq_n_f16_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (uint16x8_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
index 5285099bc2a..020138b0084 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a)
 {
   return vcvtq_n_f32_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (int32x4_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
index ad6335116bc..3f1c3c8c9e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a)
 {
   return vcvtq_n_f32_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (uint32x4_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
index ed3dd1a87d6..d16c114e00b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtq_n_s16_f16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
index e7f63f8cdd2..9256cb48a26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtq_n_s32_f32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
index ca2fdca9b49..1038af8f890 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
   return vcvtq_n_u16_f16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
index 2919ea5b364..5c06365b320 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
   return vcvtq_n_u32_f32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
index 8269bf949bf..ecec3727529 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
index 2af96d25917..9be17c0696c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
index afac0f4d414..3c33f2ce5b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtq_u16_f16 (a);
+  return vcvtq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvt.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
index 7380f73301a..8e70df955b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtq_u32_f32 (a);
+  return vcvtq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvt.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
index c6b9c1005f5..73b368fdd4f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_f16_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
index d3ef02c1931..13d7fed2f5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_f16_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
index fa73ad69ce5..d14099c87a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_f32_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
index 99ca3881553..800d8aa8e8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_f32_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
index 718c83e74df..f91021d5735 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_f16_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
index 510c29c383a..f4c444b5540 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_f16_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
index 34f7cc1e061..7c11f1f0c34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_f32_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
index b5b20efc1b8..96a1d2c8876 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_x_n_f32_u32 (a, 16, p);
+  return vcvtq_x_n_f32_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_x_n (a, 16, p);
+  return vcvtq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
index 3c3343ae4e1..7c0f551d66f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_s16_f16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
index 17ef866af39..c22eeb75a17 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_s32_f32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
index 62e6f1638d5..7f07b0fac53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_u16_f16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
index 306e32016ff..7531db7d575 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_u32_f32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
index 56867da3bb0..fd90d67b46c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
index 4449bd68c54..e6cbbeaca2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
index 580bb775c59..29d1d9d5c56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
index 3722de632e5..0181850d857 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
index 599e30e3d26..3c9a6844e01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtt.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b)
 {
   return vcvttq_f16_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcvtt.f16.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
index a4a7997d2dd..9d389382ae9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a)
 {
   return vcvttq_f32_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtt.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
index 065974d7e76..2eeb670a5a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvttt.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcvttq_m_f16_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f16.f32"  }  } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vcvttq_m (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
index 1eb69e4fee9..ba309114dae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvttt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvttq_m_f32_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16"  }  } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
-  return vcvttq_m (inactive, a, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
index 921caba0e1b..29688a939dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvttt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvttq_x_f32_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
index 90cd663c7f3..0c27a1c5664 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return veorq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
index e9ad87a9796..cbf67e335ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return veorq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
index a39d680e0cd..5d9831f8d34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
index a5dbfc4725e..ea992de1fbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
index 9ab271ac987..f2b8b91aa13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
index 45d5074e32b..c9573f732aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
index 5b8ac0a286e..86cb8ed31c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
index e436a9e6536..7b2b1ea1596 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
index 631abb515fd..3d3b2bbb4e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
index ba65042f986..7d2baba6e8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
index b49e35c887f..8275da1d7fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return veorq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
index 9b6414b8458..ea111b4256d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return veorq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
index 4a18bf5a165..f40dddcbb6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return veorq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
index 90d5a5a6021..f16ddc14e09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return veorq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
index b6103d68638..33213c53aa7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return veorq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
index 86fccc1bef0..aba155b1023 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return veorq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
index eb9e44cb777..8eac5ee6ae0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
index 3503250e5c3..3e71870daf0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
index 837210bb609..fd032647117 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
index 93796e333ab..ec67ddc761b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
index ed88d43834d..35a1dfdab8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
index e6e82d8076d..7aad6d6f5c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
index 17393d80233..315241581f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
index 027968dab2d..615b1e645b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
index 8c926bdf1c3..18a184a0e98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmaq_f16 (a, b, c);
+  return vfmaq_f16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
index c2fff9a43ea..5d67439b11e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmaq_f32 (a, b, c);
+  return vfmaq_f32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
index e8453e0cb41..e094cba8acb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_f16 (a, b, c, p);
+  return vfmaq_m_f16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
index 9d1844eba5a..3003eff236a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_f32 (a, b, c, p);
+  return vfmaq_m_f32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
index 888016e8164..4603f038467 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_n_f16 (a, b, c, p);
+  return vfmaq_m_n_f16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1, mve_pred16_t p)
+{
+  return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
index f9afc8845b0..ad0ff907810 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_n_f32 (a, b, c, p);
+  return vfmaq_m_n_f32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1, mve_pred16_t p)
+{
+  return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
index 208c46f5960..8e8738bc10a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t add, float16x8_t m1, float16_t m2)
 {
-  return vfmaq_n_f16 (a, b, c);
+  return vfmaq_n_f16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1)
+{
+  return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
index 664533239b7..4781e089ffb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t add, float32x4_t m1, float32_t m2)
 {
-  return vfmaq_n_f32 (a, b, c);
+  return vfmaq_n_f32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1)
+{
+  return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
index 7f427bd6140..3f57b80874e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
@@ -62,4 +62,4 @@ foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
index 99a106982fa..728633f5c9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
@@ -62,4 +62,4 @@ foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
index ce9bf48d657..def309387fa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfmas.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t m1, float16x8_t m2, float16_t add)
 {
-  return vfmasq_n_f16 (a, b, c);
+  return vfmasq_n_f16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vfmas.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfmas.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t m1, float16x8_t m2, float16_t add)
 {
-  return vfmasq (a, b, c);
+  return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+**	...
+**	vfmas.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t m1, float16x8_t m2)
+{
+  return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfmas.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
index 46c5a320644..c761bdcb109 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfmas.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t m1, float32x4_t m2, float32_t add)
 {
-  return vfmasq_n_f32 (a, b, c);
+  return vfmasq_n_f32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vfmas.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfmas.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t m1, float32x4_t m2, float32_t add)
 {
-  return vfmasq (a, b, c);
+  return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+**	...
+**	vfmas.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t m1, float32x4_t m2)
+{
+  return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfmas.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
index 32475013fd4..607668ebc47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfms.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmsq_f16 (a, b, c);
+  return vfmsq_f16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfms.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfms.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmsq (a, b, c);
+  return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfms.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
index fbdabd188d5..ac18e9e3d9c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfms.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmsq_f32 (a, b, c);
+  return vfmsq_f32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfms.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfms.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmsq (a, b, c);
+  return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfms.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
index ccbbfc1606c..f530e0b0614 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmsq_m_f16 (a, b, c, p);
+  return vfmsq_m_f16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmsq_m (a, b, c, p);
+  return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
index 219492a2ad9..6faca5a2e84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmsq_m_f32 (a, b, c, p);
+  return vfmsq_m_f32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmsq_m (a, b, c, p);
+  return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
index f4a1311980a..7e39b75a7bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
index 4697eb25458..57096076913 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
index ff547e83588..d47a99e29a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
index 75346b2e349..01324c003c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot270_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
index 0d458f100af..344d1ebf4a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot270_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
index 5106bb7d45b..0ee4cfb4095 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot270_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
index 73f4784cd35..c3e70ad9e2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
index 69c7cb7b0e6..6f14d2af44d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
index df4aff74bff..32bfb6cf3bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
index 5461fc26741..a7a870e78df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
index 20d2711aadb..1e6ef8f9aaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
index 55475753512..147d647d27f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
index 539f9b00bd2..76747d669bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot90_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
index 841c5294253..8b9b8ad7aa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot90_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
index d2992c2f280..5e9b004f7cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot90_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
index 0d677f7f149..d3416d65658 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
index a54af77440f..b0255e5141c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
index 5205cd37deb..10f5f31f26e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
index 2a7a79e62ea..f05d04b1f3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_s16 (a, b, p);
+  return vmladavq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
index 6b118144075..397bb9fb4ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_s32 (a, b, p);
+  return vmladavq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
index b3a4e11fa24..25c11d200ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_s8 (a, b, p);
+  return vmladavq_p_s8 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
index 0ff2ffdc5f2..064d2c22a23 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_u16 (a, b, p);
+  return vmladavq_p_u16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
index c5d213d4c0b..f5f3de9f0e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_u32 (a, b, p);
+  return vmladavq_p_u32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
index 6fcc530c17c..243e61715e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_u8 (a, b, p);
+  return vmladavq_p_u8 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo1 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
index a140be6204d..b0ff042fc43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavq_s16 (a, b);
+  return vmladavq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
index 1413e480551..a2ef4b37e4d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavq_s32 (a, b);
+  return vmladavq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
index d43dbb9fefc..e3e6e2982d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavq_s8 (a, b);
+  return vmladavq_s8 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
index e1c44d7b4ce..d021bc0e30d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavq_u16 (a, b);
+  return vmladavq_u16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
index 5e9bb56bae0..0848ca25b9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavq_u32 (a, b);
+  return vmladavq_u32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
index f4223538170..2a735fbb654 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint8x16_t a, uint8x16_t b)
+foo (uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavq_u8 (a, b);
+  return vmladavq_u8 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint8x16_t a, uint8x16_t b)
+foo1 (uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
index 7ee875eae6b..dc94ecada57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p_s16 (a, b, p);
+  return vmladavxq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p (a, b, p);
+  return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
index d4f92ba9cf2..15a2abd7d13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p_s32 (a, b, p);
+  return vmladavxq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p (a, b, p);
+  return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
index d5f14c51ae8..e56874151a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p_s8 (a, b, p);
+  return vmladavxq_p_s8 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p (a, b, p);
+  return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavxt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
index deac58d768e..e7e3b571efb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavxq_s16 (a, b);
+  return vmladavxq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavxq (a, b);
+  return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavx.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
index 56516d74173..c3841f59d57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavxq_s32 (a, b);
+  return vmladavxq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavxq (a, b);
+  return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavx.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
index 3b1e8cd67cd..59cdc346ee5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavxq_s8 (a, b);
+  return vmladavxq_s8 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavxq (a, b);
+  return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavx.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
index 246b40fbe2c..fbdbb5c16a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_s16 (a, b, c, p);
+  return vmlaldavaq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
index 6563af20061..9c59d0306a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_s32 (a, b, c, p);
+  return vmlaldavaq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
index 632e29f972d..b714b677339 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_u16 (a, b, c, p);
+  return vmlaldavaq_p_u16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+  return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
index d2fcd5d14ed..29419a06458 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_u32 (a, b, c, p);
+  return vmlaldavaq_p_u32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+  return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
index 1cb9b6ebc41..d1f049923c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c)
+foo (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaq_s16 (a, b, c);
+  return vmlaldavaq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
index 56e59f5929d..dfce7d8f625 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c)
+foo (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaq_s32 (a, b, c);
+  return vmlaldavaq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
index 7c95abc271c..7e42054a4f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavaq_u16 (a, b, c);
+  return vmlaldavaq_u16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmlaldava.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+  return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
index 239f5e32d8b..20ba6d377bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavaq_u32 (a, b, c);
+  return vmlaldavaq_u32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmlaldava.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+  return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
index 11e32c76d5a..7c2f07f3495 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
@@ -46,4 +46,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
index 937fab4166c..6214235487b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
@@ -46,4 +46,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
index 4f10ec7d098..b5922b8c281 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
index 1d78a7cd269..124125e2f29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
index 008efd95a35..de9cc0ed9c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_s16 (a, b, p);
+  return vmlaldavq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
index e824e6b7ce0..a2b1c59291b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_s32 (a, b, p);
+  return vmlaldavq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
index 1fea6d5c117..6034b9b5454 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_u16 (a, b, p);
+  return vmlaldavq_p_u16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
index 99300fcb6ec..a85d7de4dad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_u32 (a, b, p);
+  return vmlaldavq_p_u32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
index 1cdb44920e1..b18e8eb149e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavq_s16 (a, b);
+  return vmlaldavq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
index 123ca0f4eeb..b0fe1c5132c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavq_s32 (a, b);
+  return vmlaldavq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
index c9c40eeac0a..d1fcf715cb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavq_u16 (a, b);
+  return vmlaldavq_u16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
index 4d1754697bf..76726e8255b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavq_u32 (a, b);
+  return vmlaldavq_u32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
index d41c2e16114..3b8392bcf7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p_s16 (a, b, p);
+  return vmlaldavxq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p (a, b, p);
+  return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
index 8ad7b219a0f..578b7b68095 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p_s32 (a, b, p);
+  return vmlaldavxq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p (a, b, p);
+  return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
index ebe999393e8..7061bd2c13d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavxq_s16 (a, b);
+  return vmlaldavxq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavxq (a, b);
+  return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavx.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
index 0417eb867de..957dc174a36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavxq_s32 (a, b);
+  return vmlaldavxq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavxq (a, b);
+  return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavx.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
index d48b020d595..f68fe8e49a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_s16 (a, b, c, p);
+  return vmlaq_m_n_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
index 315c1afc2c7..d3c49553596 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_s32 (a, b, c, p);
+  return vmlaq_m_n_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
index a452f5de5e6..44dc3b57cdd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_s8 (a, b, c, p);
+  return vmlaq_m_n_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
index 6ecdc689a61..cbb92fb39b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_u16 (a, b, c, p);
+  return vmlaq_m_n_u16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1, mve_pred16_t p)
+{
+  return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
index 2c584a635e7..569ea91af36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_u32 (a, b, c, p);
+  return vmlaq_m_n_u32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1, mve_pred16_t p)
+{
+  return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
index b75b3c95916..592ad3e072a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_u8 (a, b, c, p);
+  return vmlaq_m_n_u8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1, mve_pred16_t p)
+{
+  return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
index 29543c8f60d..d1fa73de1c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vmlaq_n_s16 (a, b, c);
+  return vmlaq_n_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
index d74bacaffd7..c349c0c8d7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vmlaq_n_s32 (a, b, c);
+  return vmlaq_n_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
index 38dd01a6580..c1cd39e5715 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vmlaq_n_s8 (a, b, c);
+  return vmlaq_n_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
index 55a5d0601d5..5eb201c05e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2)
 {
-  return vmlaq_n_u16 (a, b, c);
+  return vmlaq_n_u16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmla.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1)
+{
+  return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
index e160275a29b..d4820ea65d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2)
 {
-  return vmlaq_n_u32 (a, b, c);
+  return vmlaq_n_u32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmla.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1)
+{
+  return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
index 5f0edef53d4..7f83f092b07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2)
 {
-  return vmlaq_n_u8 (a, b, c);
+  return vmlaq_n_u8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmla.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1)
+{
+  return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
index 3b250c1bf79..e8d1b5fd3d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s16"  }  } */
-/* { dg-final { scan-assembler "vmlsdavat.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
index 077c5980e66..effbf24d997 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s32"  }  } */
-/* { dg-final { scan-assembler "vmlsdavat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
index 2e53f5530b1..de04f9fd089 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p_s8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s8"  }  } */
-/* { dg-final { scan-assembler "vmlsdavat.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
index e127be940b4..f66f652f6fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
index 20f879c6b69..79ba85ddb02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
index 3cbed73f660..3e0f9dc2649 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaq_s8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
index 37aee878b97..61e88ce8fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s16"  }  } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
index 6a15d3cf97b..cbc2c71423e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s32"  }  } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
index d090e625e1b..2b30e8a9c12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p_s8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s8"  }  } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
index 0ef5302ef80..90fd85a170e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaxq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
index 71a5e1a987f..06fe27faf49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
index 7df6b9f7f32..70a44b49d8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaxq_s8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
index f71dda19c57..09db9a3a90a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
index 255235ba372..8eb9d24263a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
index 2fc892db2eb..166fedea45c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavq_p_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
index 7376b07865b..b97252f7225 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsdavq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsdavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
index a37042eab30..5473cfe22fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsdavq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsdavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
index b44b98bc7e4..487097118fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmlsdavq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmlsdavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
index aa4ac4e4f01..d1ff9a0fa1c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
index 0de81290d99..09c19c1f161 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
index 68588f6951a..1f364a3e846 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
index 8f49d6a6106..1c0675fb44b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsdavxq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsdavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
index 830cd4ca8b1..5986e130ec0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsdavxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsdavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
index 74feb60b005..4f8aa44b57a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmlsdavxq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmlsdavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
index 78d29b058a3..8d0a03c0213 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
index fca0ef1d3dc..fae2ad5c713 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
index aecfcee4571..bfe4010df68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
index 7344a50f02b..b023b1b67ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
index 5278bd842cc..1ffa8c28ea9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
index 07efdf96f10..aa5001705c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
index 6a51d9f3d93..7772b3da069 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaxq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
index 275776388d2..eba923f15d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
index 6eedf07efd6..79ed4c94b64 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
index b36ea49612c..44982f89edf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
index f05841798c9..dbdf1deae04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsldavq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsldavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
index 45bee16ab79..458f14c446f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsldavq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsldavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
index 821f4eae90a..9481550f526 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
index 77e84d07486..cc20e554932 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
index dcd88f8db73..7a4d9365ed6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsldavxq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsldavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
index d59550ba69e..b241569d75c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsldavxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsldavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
index b7ce6ce9c2a..69c2f91b50e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
index d15df32831d..2b3cfacb5f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
index dcd9dc43692..39398b2cde9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
index dbdeb263086..30ca18ad103 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
index a6b5cbb1527..8ce0da68113 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vmovlbq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vmovlbq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
index 4ead765bb6e..36fbce37bf8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vmovlbq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vmovlbq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
index fec88bb7f79..b90728e9956 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
-    return vmovlbq_u16 (a);
+  return vmovlbq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
-    return vmovlbq (a);
+  return vmovlbq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlb.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
index af6d804696a..5299f581329 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
-    return vmovlbq_u8 (a);
+  return vmovlbq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
-    return vmovlbq (a);
+  return vmovlbq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlb.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
index 393fc5523a7..63d2ddb9015 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
index 3773be0b621..b573f572012 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
index b668eeb6fcf..f039019f5b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
index 6019e2d09d7..7fb32ece22d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
index 47897a3913f..72ca8c8bb9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
index c87b263db51..7e3b4f40bc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
index cfe7cd7a5d3..4320df794ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
index a9119fbb940..c9a75a590b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
index a7fd325e330..f431cda53ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vmovltq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vmovltq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
index c392e56b60b..d65f8066454 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vmovltq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vmovltq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
index 7634af6f45a..5469671041b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
-    return vmovltq_u16 (a);
+  return vmovltq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
-    return vmovltq (a);
+  return vmovltq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
index 2c0d1a7c69d..a14c71cdfbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
-    return vmovltq_u8 (a);
+  return vmovltq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
-    return vmovltq (a);
+  return vmovltq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
index ae6c8999835..f8e24c4e0d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
index 1172643218a..b97de081858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
index 64442dcf935..851264e45ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
index 33e571890c0..82219b670db 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
index fdb392cbf81..3bd9b82cbb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
index 9f32f49d24e..bc2f95c7d8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
index ebc1599af54..1624237c67a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
index 502068713e9..1a2f1e8441e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
index a49943fd25a..d5286f11259 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vmovnbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
index 6dbce232399..b6b44837b8c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vmovnbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
index f3df71a43eb..1203ac5c7f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vmovnbq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
index e0369ed5fa2..de5bb111783 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vmovnbq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
index f305ab30dc8..594f72c08f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
index 59820c610e6..b3e3e0442c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
index 079b162148e..a3e33db311e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
index 7c09b2e4f9f..b5629493c72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
index 229cd5809d9..d7e369d266e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vmovntq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
index 01921cbd66e..6d87cc21aaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vmovntq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
index 30e75b2169d..f85e45a666a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vmovntq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
index 9ed963dda70..05c4af3d614 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vmovntq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
index 1b6e683700c..9d4804a0057 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_s16 (inactive, 2, p);
+  return vmvnq_m_n_s16 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 2, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
index dcfd69fb7f1..607cdfca33e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_s32 (inactive, 2, p);
+  return vmvnq_m_n_s32 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 2, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
index bd86fa806b8..7b0b5a9ef83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_u16 (inactive, 4, p);
+  return vmvnq_m_n_u16 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 4, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
index 2ac6ef192d7..2217420081e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_u32 (inactive, 4, p);
+  return vmvnq_m_n_u32 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 4, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
index 5284b8fe054..e27d8111b54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
index da16a5d45d6..8a264a1e76f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
index 206759247c5..c4374d0ffd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
index 9940cec4bfe..3d5d56eadfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
index 25179f13f95..fd1961e0673 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
index 7237db35b33..037d1f4ce39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
index 336c6aa63c4..975639334d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo ()
 {
   return vmvnq_n_s16 (1);
 }
 
-/* { dg-final { scan-assembler "vmvn.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
index 354c39c8f7b..0e09343e6c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo ()
 {
-  return vmvnq_n_s32 (2);
+  return vmvnq_n_s32 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
index 178b003091b..84e158ade93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo ()
 {
-    return vmvnq_n_u16 (1);
+  return vmvnq_n_u16 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
index 4819066bdbd..168b77a400a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo ()
 {
-    return vmvnq_n_u32 (2);
+  return vmvnq_n_u32 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
index 840d834ea9e..30ddcd9118e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vmvnq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vmvnq (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
index cf73bc088c7..48d66753c0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vmvnq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vmvnq (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
index 6d239391cbb..199bb0f81c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vmvnq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vmvnq (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
index db348328513..c2d724f5375 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vmvnq_u16 (a);
+  return vmvnq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vmvnq (a);
+  return vmvnq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
index c007a959078..8bafe68f21c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-    return vmvnq_u32 (a);
+  return vmvnq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-    return vmvnq (a);
+  return vmvnq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
index 2288a283d60..684e5bc94f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vmvnq_u8 (a);
+  return vmvnq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vmvnq (a);
+  return vmvnq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
index b00ccc3e672..a4d575e4aba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_s16 (2, p);
+  return vmvnq_x_n_s16 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
index ea65104b4b3..9ca5c90d80e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_s32 (2, p);
+  return vmvnq_x_n_s32 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
index 2fa4e40ad5d..9fbf2b978ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_u16 (4, p);
+  return vmvnq_x_n_u16 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
index b39e681c116..883e9af1609 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_u32 (4, p);
+  return vmvnq_x_n_u32 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
index d4b87a795fc..6bd04f7dd38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
index 0bcdba0c1d6..6af90408e9c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
index ffa7306ace6..8c6f118c36f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
index 29b5ad950ea..2e9902f3858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
index b3d5f73cd92..53b2ebdd457 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
index f085aa83662..ad7a5a9398c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
index 7cf00d94084..36543ee6bff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vornq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
index d187bde1dc2..c3d73059c31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vornq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
index 081872bada1..7a5cabf4396 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
index fe92dae6ec6..8fb90212c88 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
index 56a2b64bc29..31123f853f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
index c2e4b1267b8..e5d6d63955b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
index 6607808e96e..73bde2bcfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
index 1905ed193ac..2872c0a7045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
index 6d6620c3e07..90e8df24b99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
index 23e8d046c73..eedbf3a1ae1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
index 0f73ea28e0d..ac92a93f19c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vornq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
index 7d9835fc1b8..38be3483872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vornq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
index f2ba62292f5..3d5e47fa1e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vornq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
index baa3fd80813..e69212d59b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vornq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
index 481db437b77..c89622c830f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vornq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
index 575a7365487..61ce5ad294a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vornq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
index d776bff2416..2bc10776f6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
index 939e8fafb83..7b733cf6a6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
index 77569b42cc8..beba497bbf9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
index 29cfd020c30..60e6125ed6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
index fd10ff8e719..f62c9b2a111 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
index 473f22abd52..2ac693ca30f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
index 010ac07454d..1981c8ca408 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
index 126a6d236b3..171dc0f58b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
index 1481c43ae5f..3d222d5679b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vorrq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
index 257edd99b7b..140817ee919 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vorrq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
index 641c8f0f3bd..dbfac724131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
index b537a7c74c3..e13a1df44e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
index 757482a3a95..b591bd6fc11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-  return vorrq_m_n_s16 (a, 253, p);
+  return vorrq_m_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
-  return vorrq_m_n (a, 253, p);
+  return vorrq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
index 967e49e7a26..ce4dd3ee7bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
index 01022c32a88..9e7788484ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vorrq_m_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vorrq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
index 809237d1cf6..613c0e2f889 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
index 2714810d591..d475f1e939f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
index c960b18631a..e171e93e4eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
index d1d4bc721b0..17043b26c2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
index 01190ea4812..19a752ec3b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
index 502ceab2fe4..7f3985d1508 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
index 44cf1413ca6..5a04ebdf1de 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
index 63a369f9996..b95418d9668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vorrq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vorr.i16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
index cf7bbc8c46d..30248216012 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vorrq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vorr.i32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
index 2d599e52f8d..1f131501aec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
   return vorrq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vorr.i16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
index 5a873d0d1a3..5bfdb0b2e14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-  return vorrq_n_u32 (a, 44);
+  return vorrq_n_u32 (a, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vorr.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
index 2a56912ab31..658df6f422f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vorrq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
index e80b991c95a..a0a24b7fd45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vorrq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
index 3456477c07c..645c6144f46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vorrq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
index bb7699c1e3b..cb618a1f793 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vorrq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
index e01f5413dc3..937102ff962 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vorrq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
index c7ad98805c4..07121b5b1c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vorrq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
index 2e678febb78..b34d102f470 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
index 12acfb49773..d41a94e7a02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
index 75fe4541845..3e1d3e97d26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
index 37d17f046af..0982b3d2081 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
index 3558db3b7b0..0a46246e124 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
index 7c9a2559c87..ef83d9de2ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
index 13ff34d582a..b6abfd5b314 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
index 781b2b59699..b724ed0562b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
index a84f84446c0..2b894d1d938 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
@@ -1,21 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpnot(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (mve_pred16_t a)
 {
   return vpnot (a);
 }
 
-/* { dg-final { scan-assembler "vpnot"  }  } */
-
-mve_pred16_t
-foo1 (mve_pred16_t a)
-{
-  return vpnot (a);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpnot"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
index ff121b585ed..50127b4537d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vpselq_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
index 35c84761f08..0733413f1ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vpselq_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
index 0e0c14ed49d..06ef70c4073 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vpselq_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
index 0e746de6e07..87b4b2242eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vpselq_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
index f4bbb77e268..dedb812c11b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t a, int64x2_t b, mve_pred16_t p)
 {
   return vpselq_s64 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t a, int64x2_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
index 65cd415c789..5050fc03556 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vpselq_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
index 742ca17ac8e..055f3c00381 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vpselq_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
index 9d2e01c31d4..11333822b19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vpselq_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
index 58c4169bc0a..c08e6c54d95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
 {
   return vpselq_u64 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
index 5f73ba44ea8..804aed384c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vpselq_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
index bf5520ed1ff..dd6c0300c32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
index f07612a47d5..eb340ebe520 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
index 79f082fefab..673f453e7af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
index 5d242dc497f..84f7f9bf897 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
index 18df48f5084..ed17eb81884 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqmovnbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
index 37f9e817805..065ce9b246c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqmovnbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
index 130dcb06944..29df4636e3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqmovnbq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
index 8bf735294e5..422c33560d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqmovnbq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
index bc624bcd877..b50964bd4f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
index 429f25cdb0f..5d4947abb9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
index a453a9fc36a..8cfd62831eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
index 3f9ae8a5ee4..b9d3b7e75ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
index 5de956cbac4..8838a242fd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqmovntq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
index 30db31c47ee..1d8b0dc17ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqmovntq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
index 312ce4f865f..10badd5feb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqmovntq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
index 20623384858..80460393001 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqmovntq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
index 8e46de63b84..d295b3f9155 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovunbq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovunbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
index d0ec95192f9..84b94db682f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovunbq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovunbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
index 9b3b80d024f..070bb90bf12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqmovunbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqmovunbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
index 9cc43d987de..659e703a558 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqmovunbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqmovunbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
index a81fb8863af..fb3b36c451e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovuntq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovuntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
index e76ca2b5f48..f6fce6d4473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovuntq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovuntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
index 324d2e56f3c..3230f25998b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqmovuntq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqmovuntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
index 80fee05b642..5333897a34a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqmovuntq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqmovuntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
index 5b0e134a0ff..1140c25c4a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
index 6fdf3879cc2..b3e6dac19a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
index ef75f737161..5ae74e1dd2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
index cf7cdb202ce..f515c3926da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
index 5a022fe3009..4693d01eeb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
index 2cb27df16f6..cea58e4f80a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
index 1f68671b3f9..3b8ea613f1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
index eaea6e1f482..6ef932672bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
index 0f582a91f3a..5b9dc5cadac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
index a26898ebdab..745c70b84f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
index 572486ecf82..94e976f724c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
index 00e478b9d3e..f8c9f487068 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
index 304f86c6e51..f8400ac63d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
index 265fecaf806..fa1131de6b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
index d1687f79311..a7ce97cc2f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
index 4595d55711e..175a2f74416 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
index 22d9ce56a35..56d5423bd3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
index 36a23ad2078..992be758837 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
index 2995682f252..d713c224b30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
index 7e637e6900f..8af4928f833 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
index d81472d933a..9f30b7d0e13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
index 2710f2f0442..83caaab8926 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
index 5fefc3938c5..337f33c51c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
index df96fe85213..df005ee9b03 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
index 6a5776215ca..52c7f16df12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
index 9539e249d6a..574809dde9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
index 69e54f53a76..9b509687ed9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
index 3eb957d6029..19fdc151550 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
index 3a3fb506c01..d50bd8500bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
index 65ac15da9c7..c3f6b3e462b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
index 3598f50ccba..35fc3bde975 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
index 1ab22edf9ca..7b5ee71194c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
index 01103e99b61..0ceb9c55aa3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
index 522d0ba4a3a..b94e4cca8b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
index 5198dfa754e..0f508d9bca1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
index b5baa3dea79..92607fe0265 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
index fc3a33073aa..ae38058cc62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
index 897ad5bd28c..e923495f4b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
index 05ab0609af4..a6ce3b2ca01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
index 1d9dc07787c..a8a749d07cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
index 76d7507e35a..ad6130dfbdc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
index 7fd2119ea63..da29228e5f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
index 8a90a399858..342ef427bc9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
index 973464b3297..7ae72b75689 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
index 65aab964f4e..8acb72a2245 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
index f3153c86b4c..5e93d7758c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
index 48b10dbd025..d2812c0aa05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
index 9f0346fc841..5c188a6d91f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
index 8d5abfd7588..d9baa378fac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
index 734f67ae251..ce4140a6fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
index 3c6724f285b..ce576b01d65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
index 3e39599df8a..e861a7b1f6a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
index 41f5945daf9..d4cb581c623 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
index 9aad2599476..f170f225d95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
index 80045c5b583..7c5449fb168 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
index 9b4cf1663cd..53a421cf830 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
index 55e0dd57023..52ad4372916 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
index cd5605444a1..e7ca4786363 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
index 02c94d0a51f..3785bbea0dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
index e6058dfc4c5..c736abeceab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
index 46fd917d2d9..231ce85f1a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vqrshlq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
index 373de10b89c..05589eb86cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqrshlq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
index d05d2fc722f..182e7cf260a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vqrshlq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
index 8a74d61e75d..1b5214623c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vqrshlq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
index ccb0db7bb32..50d09bac3a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vqrshlq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
index c3319ea29d2..846d90a2470 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vqrshlq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
index c5645cee518..2a4a0feb5e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqrshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
index b773ccf9245..94665928299 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqrshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
index 1a61cb6de10..2836a6e4dc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqrshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
index 8de05a290b7..2ea554253c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vqrshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
index 0ceee291bab..fef01d926b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vqrshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
index 7779871c097..6ceafa0f473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vqrshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
index 16a4827e50d..76c38e07faa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
index bb054bcf5a1..3af0ad96493 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
index 45119720ed5..f81dd96efde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
index a3a7a7eac3e..ad52c378a07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
index d1b2ea58dd5..3f82f86029e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqrshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
index da5db1b8951..02f303052a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqrshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
index 360999e3785..cda56ce3c48 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
index f276f24a1dd..5202e6249a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
index fb21072bfa0..39c0eff56f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
index 77c4cb7e0b0..5fb6983237c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
index 1749f4866a4..91ec5795566 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
index e243319e256..986437e49ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
index c7cdc394c35..5dfed5dcbaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqrshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
index 68dfccccc66..7df82962342 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqrshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
index bc0572a454b..e76d98ee3f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
index 20bfdbf515a..bc0e39baeae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
index ea12f346b0e..299dd80a887 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
index d127e5381bf..5c87efe4be9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
index 88cb39970d4..3bbf72d4def 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqrshrunbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqrshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
index 46f96127b1b..4dfd8f60e72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqrshrunbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqrshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
index 5ff25eb2d32..48c17e5e5b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshruntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
index 4876414e308..46912882ff1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshruntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
index 0f6258b3524..9dc8d3b8f5a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqrshruntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqrshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
index d307f38ec6c..8071367fa2f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqrshruntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqrshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
index a33856f17a5..6eb7443d45e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
index bcfe4fc2874..d10829c90c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
index fba2f0fe859..49886009d74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
index 1383f6a9ab4..7eb330e6c18 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
index 7cff29f5a28..86ecdc6d563 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
index cbadcbeb77e..f3886e7bae6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
index a3057fec343..e89298c570b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
index 6973b49a476..35e2552728a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
index 282d4b45c59..366b45699a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
index 111d7fa23d9..86774962f0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
index 96de168dd23..92a61fe4a2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
index 24e388824cc..bace3656143 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
index ebae8beecb4..2df2ee5c836 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
index 80e4d860fb9..e0b2de339f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
index e8f88113003..b65df1998fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
index 692ff54981d..bced90d13b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
index 1ece80681a7..409ef8524cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
index 7302669fe26..ce9a426ccc9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
index b827993198d..859da655409 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vqshlq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
index dbc22df551e..1d61e880890 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vqshlq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
index e4e1d193c55..737c1bd3764 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vqshlq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
index 8227890fc4b..9ddb83e4287 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
   return vqshlq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
index b91dc3b91d3..642060f2225 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
   return vqshlq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
index ab4903ae407..bd8b9341007 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
   return vqshlq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
index 4413d447b71..285f398b35a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vqshlq_r_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
index 6df14afb48d..af594003c06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqshlq_r_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
index c1b93793c8f..ef39f0c3924 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vqshlq_r_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
index 20fa0263de4..e6cc0007a2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vqshlq_r_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
index 7d56784b3d5..b30ecdf4052 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vqshlq_r_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
index 199249bf604..69b0a8d0b90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vqshlq_r_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
index 2b01d3e3d31..e7877019200 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
index b9b66223ae9..a7787cabb62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
index 8096205cf28..73af1790b47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
index 61b6c18bd8a..26119eff397 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vqshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
index 06b50442d30..01b66d5dfbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vqshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
index 0cc6a1dac4b..d4727de5de9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vqshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
index 885874d13fb..ada03b165c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vqshluq_m_n_s16 (inactive, a, 7, p);
+  return vqshluq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vqshluq_m (inactive, a, 7, p);
+  return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
index bb2a3294727..6ae38f1ca84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vqshluq_m_n_s32 (inactive, a, 7, p);
+  return vqshluq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vqshluq_m (inactive, a, 7, p);
+  return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
index 7f9a42f8027..8d536a7b0f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vqshluq_m_n_s8 (inactive, a, 7, p);
+  return vqshluq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vqshluq_m (inactive, a, 7, p);
+  return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
index 481a4465834..33ba80cbf97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshlu.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (int16x8_t a)
 {
-  return vqshluq_n_s16 (a, 7);
+  return vqshluq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshlu.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshlu.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (int16x8_t a)
 {
-  return vqshluq (a, 7);
+  return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshlu.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
index 68298963824..0d5a35f1ed3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshlu.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (int32x4_t a)
 {
-  return vqshluq_n_s32 (a, 7);
+  return vqshluq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshlu.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshlu.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (int32x4_t a)
 {
-  return vqshluq (a, 7);
+  return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshlu.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
index 5d52c340667..1e2d9e044b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshlu.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (int8x16_t a)
 {
-  return vqshluq_n_s8 (a, 7);
+  return vqshluq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshlu.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshlu.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (int8x16_t a)
 {
-  return vqshluq (a, 7);
+  return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshlu.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
index 9ea58e95d37..0266640a3ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m_n_s16 (a, b, 7, p);
+  return vqshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m (a, b, 7, p);
+  return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
index b44f41b3699..59be6de392b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m_n_s32 (a, b, 11, p);
+  return vqshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m (a, b, 11, p);
+  return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
index f761d14ecec..f227a285ea9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
index 3073a5b223c..9711c2f9019 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
index 24133b57660..e7e9f974bd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
index 34c11e156c3..b5e2b8af577 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
-  return vqshrnbq_n_s32 (a, b, 2);
+  return vqshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
-  return vqshrnbq (a, b, 2);
+  return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshrnb.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
index 23a7596e0ab..708cf3e8d74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
index 4cb7ceaf66b..07fbbaada67 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
-  return vqshrnbq_n_u32 (a, b, 15);
+  return vqshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
-  return vqshrnbq (a, b, 15);
+  return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshrnb.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
index d2ff2d359e0..c25619df048 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
index 50dde4047d4..1b1d435e282 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
index 07949569581..f151a277cd1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
index 17f0205c880..c336001c945 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
index 9e8d5e88619..15b010d2c84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
index 0661cefa783..974e4a060ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
index cda26142559..3172a330f6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
index f242353f6b4..e9e31d63e98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
index 73c480646e7..b7fe0e51e82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrunbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
index f8887b1cecb..fb78dd44c5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrunbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
index 2c64d7d0873..3c286e77a40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqshrunbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
index 17cb0aa5da1..e22fb2b2b36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqshrunbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
index 4b9758df7ec..22ca346d98b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshruntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
index 18b9f117fb2..2f6adf26e5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshruntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
index f6247751c44..96a377e13b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqshruntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
index 076fd29c69f..2e2eb93a0d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqshruntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
index a64b6649938..f69649b58af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
index 350629cf234..a7843d07933 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
index e5fa4c486bb..f1fb5ad2a05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
index 734ac2da8f7..7e7d2c07267 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
@@ -62,4 +62,4 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
index f54aec8dd00..13e54be06c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
@@ -62,4 +62,4 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
index c96a8398bad..ae6baaba661 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
@@ -62,4 +62,4 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
index bd6a05e858d..fd52022fc26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
index baa9e9f192c..4225ec29c06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
index 746001d0efa..27496305ee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
index ed504fe3817..d840e51d350 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
@@ -46,4 +46,4 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
index 508b54ff41f..242903f9dc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
@@ -46,4 +46,4 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
index 5cfb2c58940..e5a6b7aa0e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
@@ -46,4 +46,4 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
index a4407cc802f..7a286add743 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
index 80634f0a797..2532b216a34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
index 172609a94e7..9e0a233baa0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
index 0a95d0ab3ce..20d3267e583 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
@@ -50,4 +50,4 @@ foo2 (uint16x8_t a)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
index 9964ea66ee8..4805e4cd969 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
@@ -50,4 +50,4 @@ foo2 (uint32x4_t a)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
index b28a93ffd00..db475615bbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
@@ -50,4 +50,4 @@ foo2 (uint8x16_t a)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
index 1c5edd730ad..76def1b340d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
index a7b6c07fb4b..989ad501659 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
index 92676fdca4f..4cf804b4c99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
index 0b816c6b765..4d937a35269 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
@@ -38,4 +38,4 @@ foo1 (uint16x8_t a, uint16x8_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
index 565508db865..5ee2c2d9cc2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
@@ -38,4 +38,4 @@ foo1 (uint32x4_t a, uint32x4_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
index cca60ff7247..14cfb55644c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
@@ -38,4 +38,4 @@ foo1 (uint8x16_t a, uint8x16_t b)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
index 7b06f0b3644..b366057dfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
index 8cf374d97c1..7baad3ba72f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
index 52688402437..23fcd61a464 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vrev16q_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vrev16q (a);
 }
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
index 56c05c523f3..e08b4b6cda2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vrev16q_u8 (a);
+  return vrev16q_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vrev16q (a);
+  return vrev16q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
index 700a6774e2e..6496bf89931 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
index 3b424061f0e..e03f6f177ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
index 946fd8ddf5b..6e4c5691760 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrev32q_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrev32q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
index 623b48a92c4..3b25f0314c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
index 4040707d02c..36f671924b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
index ad15e9d2bca..13960569138 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
index 8cd61e6bb1f..7683397030b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
index 44600e2d1e7..72fc03bff2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
index 503616e2a29..cd02518fd9d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vrev32q_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vrev32q (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
index aa98f965713..3a156b7014f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vrev32q_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vrev32q (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
index 6a441ed0edb..299f015bb04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vrev32q_u16 (a);
+  return vrev32q_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vrev32q (a);
+  return vrev32q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
index 787f236411d..fb65d0a3821 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vrev32q_u8 (a);
+  return vrev32q_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vrev32q (a);
+  return vrev32q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
index f7dc8fb14ec..d1c22aa72f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
index 81ec83dec4b..0f0c19b1483 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
index 8d3bac1e82c..2457dde2a58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
index 36ba71752a8..b1b1237344e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
index 9d15c9df43c..21d39274577 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
index 7ec0962a95e..a2dc8957467 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrev64q_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
index 01c342496da..78add56a4da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrev64q_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
index ef47bab0314..0fb44077ec4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
index 6df0ba62eff..ff62ea7d021 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
index 9f9bbe0e666..b30ce76c68f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
index 132628b5a80..b44d363a712 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
index eb6e560ac3c..4804b8acaf3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
index 4534a64ee84..12c26144cd2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
index 3f1ab24527c..ff90d92fff3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
index 4adb70963dd..267c3b6bee2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
index a886b0b0c6a..b6083f9d69c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vrev64q_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vrev64q (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
index b0ba64b186b..81fc7d1bdd0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vrev64q_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vrev64q (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
index 12f9f1ac389..3fced739681 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vrev64q_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vrev64q (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
index ee3813428c9..b25fccc6c2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vrev64q_u16 (a);
+  return vrev64q_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vrev64q (a);
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
index c4a551dcc15..9d203b1f6bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-    return vrev64q_u32 (a);
+  return vrev64q_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-    return vrev64q (a);
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
index 578d538f019..9acd52439e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vrev64q_u8 (a);
+  return vrev64q_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vrev64q (a);
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
index 467da7fe9ef..9c949028d8b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
index 1a3cd17ebd6..445834a55f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
index b9932eddf38..66daa3d9131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
index 4eb3d4d09b1..2c5a5ee1a0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
index 5c22c387586..a24f17d5797 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
index bbf42931d92..4c11e79254b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
index 1b595c3ad2f..14f676e0cff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
index abff81e40b9..542dcaa782c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
index 01d72efc34b..0deef794352 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
index dfe8d7334a8..e584987fb3e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
index 9eceda2b115..40e3472bbf0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
index ec11b660a4e..bd53871cc58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
index 25c6208ec06..30037083a01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
index 7b25bf8faa8..3208ac1589b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
index 36f36f77233..bafb1dc5795 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vrhaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
index 813cf91649e..bbee81fffd6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrhaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
index 5ce1109d676..3fad58d4e0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vrhaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
index 9d9bf18ec70..91273571ec8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vrhaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
index e465197505b..79a21051b0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vrhaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
index cbede385f20..4bdd23419a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vrhaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
index 8507b436dc8..363dedd3304 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
index 756c52f8f1e..f1df6749f33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
index 9b580782098..107cf2daa58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
index ec534c8262e..5837437d33c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
index c79f406439e..0d8d118987e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
index c4c16f8a753..37711710ee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
index 2134e3fc0dd..c18ff82f8f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
@@ -46,4 +46,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
index 4ebd337e8ee..ba0a9587e3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
@@ -62,4 +62,4 @@ foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
index 2efde824eb3..b2ced4b41c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
@@ -38,4 +38,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
index 745655f31d0..96f1ab72e92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
@@ -50,4 +50,4 @@ foo2 (uint32x4_t b, uint32x4_t c)
 }
 #endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
index 0e29e886ce1..a0164ed2bb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
index 063c94d8c5b..4e71fd72e35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
index 1d7a5e3d690..b8f346f9740 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
index 539b04254cd..d6c6d503a9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
index 566b85d1721..22c1164b6a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
index 352cd58c8e8..6517ee8cd60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavh.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vrmlaldavhq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavh.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vrmlaldavhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
index d99ebffbea0..ebe1012f53f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
index 64f02971eb3..56a2071d61c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
index 83d5a8ce251..aad2f009ba3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
index a8a320c6a43..f30870181b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavha.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavha.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
index aa20ba1a7eb..2a3f441e429 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
index 78932840dfe..06afa309bfa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
index 1e2127a17be..9f1f82a7c62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
index 2a7844fa370..ff867d5c208 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
index ecbc9737d8f..2a127c76df8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
index 0cea55724aa..41539059d7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
index 6adaf3f6431..e5c70a0a323 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
index a90a67971c8..6b373e1739a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
index d0dd99aa4c3..961ba71ccb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
index 50d05c1de11..3a782c295e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
index a7da7330266..818fb631ff7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
index 42b0b9f0f2f..3d1eb365c63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
index ac77b9f13ba..34c3f182628 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vrmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
index a7bbd19c393..fe4d11c5acd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
index b0d1a856794..4b5a2e656ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vrmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
index b43cb07b1bf..478d5885edd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vrmulhq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
index f37eeb606f2..e3dc75d10aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vrmulhq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
index ab5d7597a43..108357b6d35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vrmulhq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
index 3ef89bd686b..00f728bdaf2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
index 2a4b9d0d147..49a739d9a95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
index d3ef8713dba..7d97cbc5f8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
index 5ce4d01a235..31622dce8df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
index 4a965976c2d..f6d2582bac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
index 015530c08b2..15e947618f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
index ba8426fdff3..17b11972e84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrinta.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndaq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrinta.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrinta.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
index a8c9c28422f..dc3689a66d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrinta.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndaq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrinta.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrinta.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
index 3617d796351..ffbdf3dad94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
index fdb9ddb3551..d20f8050c45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
index f398e86b689..141f612ddcb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
index f5f21808528..277d2a7b668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
index 911a2b1cb29..a51878645da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintm.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndmq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintm.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintm.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
index 496a2e55d55..4b79490cc21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintm.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndmq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintm.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintm.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
index 86f58e2eb88..e6eb2a1015d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
index 247595df56a..99f3f206823 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
index accc79579ec..cdef684f381 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
index 0e4200dc2f5..94da7738d16 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
index 23299c2a06f..b1b31bebb11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintn.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndnq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintn.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintn.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
index ce445f2249f..e2fec8a87e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintn.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndnq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintn.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintn.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
index c41e38070bf..04d828bde24 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
index 09b9b95d67d..b32eacd9b20 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
index beeb23cf364..093aaa04d57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
index d09e55d53b3..8428800d503 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
index 25dcbd5f3bf..3145faf9f70 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintp.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndpq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintp.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintp.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
index 5ab6f7ae9c3..2754af48612 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintp.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndpq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintp.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintp.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
index 2cf8220c789..e62883c1edb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
index 7ed26e8d926..b8370b85373 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
index 233a6e843e8..57465385173 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
index f689ce6510b..86a94c0dfe5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
index 6fe3b2eae48..4b2ee2c3da2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintz.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintz.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintz.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
index a27b5c99b3a..301e9e4c25e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintz.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintz.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintz.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
index 3a9edafc772..d7ba6d4f11f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
index 0ae4b92d235..6bfe1d49941 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
index eb6c3c37876..13ba05011e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
index 8b4c8c1e289..162d199420d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
index e6f2028de30..9df65c5473d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintx.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndxq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintx.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintx.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
index 32e6c90e60e..92bc6df1361 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintx.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndxq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintx.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintx.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
index 0e6a6119f08..9d92566b08d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
index 3b09769814b..7a216050fb1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
index c160800023f..537506cd5be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
index 48b76161032..e19ba0c0a3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
index 9e7f22ccad9..e30cfe16fdf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
index 6b6a98c3da4..acb89bd462a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
index e54893d2abc..4d0c6048971 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
index ecb41a2c444..1b768a13061 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
index f09db27adee..6350e3c4cca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vrshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
index 2bc4170b07f..8ae96d8a2b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vrshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
index 990871f5b9e..2918cb05e43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vrshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
index 875fed28fe7..c615d8083d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vrshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
index 72206c36fda..639f25ed719 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
index e964af2e8b5..07a53e364f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
index ad98b7677f0..f00d62bcb7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
index adee8b28b88..bb809acfe6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
index 4c2f133b605..926a897d50e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vrshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
index 26508ba7961..7e931355751 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vrshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
index eea3d4974db..61636d301f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vrshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
index 49afdf0c61e..b82dad525f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vrshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
index ee48f8c2733..b1a2f813320 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_s16 (inactive, a, 16, p);
+  return vrshrq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 16, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
index 4330dcfaaa6..fb229273b86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_s32 (inactive, a, 32, p);
+  return vrshrq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 32, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
index 4b35c597a13..b9136b8dd69 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_s8 (inactive, a, 8, p);
+  return vrshrq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 8, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
index 2e83c60ad95..9dbc3fed62a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_u16 (inactive, a, 16, p);
+  return vrshrq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 16, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
index 5d2a9d8f4f4..0e0cb10b476 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_u32 (inactive, a, 32, p);
+  return vrshrq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 32, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
index f5b43708689..010a7915c56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_u8 (inactive, a, 8, p);
+  return vrshrq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 8, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
index 2cd934774ce..ff3d552bd78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
-  return vrshrq_n_s16 (a, 16);
+  return vrshrq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
-  return vrshrq (a, 16);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
index 3cc21f2b277..db161f7d009 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
-  return vrshrq_n_s32 (a, 32);
+  return vrshrq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
-  return vrshrq (a, 32);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
index 251d5324f5c..86a0294f8a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
-  return vrshrq_n_s8 (a, 8);
+  return vrshrq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
-  return vrshrq (a, 8);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
index 6934597f844..897247fce6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-  return vrshrq_n_u16 (a, 16);
+  return vrshrq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-  return vrshrq (a, 16);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
index 52b287b8f3b..e8f7f1c33e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-  return vrshrq_n_u32 (a, 32);
+  return vrshrq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-  return vrshrq (a, 32);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
index ac595a9ac95..a22521b14ae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-  return vrshrq_n_u8 (a, 8);
+  return vrshrq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-  return vrshrq (a, 8);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
index 14b5c1884f4..37f364cfc39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_s16 (a, 16, p);
+  return vrshrq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 16, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
index 846ddb96782..0da2fd75056 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_s32 (a, 32, p);
+  return vrshrq_x_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 32, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
index 06f75e56db6..90c814b20c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_s8 (a, 8, p);
+  return vrshrq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 8, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
index bc946497cfc..135b9e7e90f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_u16 (a, 16, p);
+  return vrshrq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 16, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
index 55002cd196d..dd656f49aa7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_u32 (a, 32, p);
+  return vrshrq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 32, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
index e3130657711..e41abc450a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_u8 (a, 8, p);
+  return vrshrq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 8, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 21f4219faa3..66a5c4c9da3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -1,23 +1,61 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m_s32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  } } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index ef9eed92d33..9306f152cde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -1,23 +1,61 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m_u32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 2181a3a2879..0b5040f0b2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
   return vsbciq_s32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
-  return vsbciq_s32 (a, b, carry_out);
+  return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df0487f3b88..df211a64daa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
   return vsbciq_u32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
-  return vsbciq_u32 (a, b, carry_out);
+  return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 73be46a8459..ed9e48ce7bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -1,23 +1,81 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m_s32 (inactive, a, b, carry, p);
+  return vsbcq_m_s32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m (inactive, a, b, carry, p);
+  return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 80cf70584e5..442a52ed5f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -1,22 +1,81 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m_u32 (inactive, a, b, carry, p);
+  return vsbcq_m_u32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m (inactive, a, b, carry, p);
+  return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index 23e42575bd7..fa88ec5dcd8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -1,21 +1,73 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vsbcq_s32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vsbcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index d3aa66f6134..c3ae208ff82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -1,21 +1,73 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vsbcq_u32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vsbcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
index c4c77f2559c..c603a89117f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (int16x8_t a, uint32_t *b, mve_pred16_t p)
 {
-  return vshlcq_m_s16 (a, b, 32, p);
+  return vshlcq_m_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int16x8_t a, uint32_t *b, mve_pred16_t p)
 {
-  return vshlcq_m (a, b, 32, p);
+  return vshlcq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
index 20cfd09c82d..46e75033ae6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (int32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
index 33dde10e4a8..868de5df80b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (int8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_s8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
index 2bf69f0c465..a1e1c3f9bc4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (uint16x8_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint16x8_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
index e6650302ea7..bcb0bebd969 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (uint32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
index 95857f09371..98936447451 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (uint8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
index ecd4fce5de3..e6c5069af21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, uint32_t * b)
+foo (int16x8_t a, uint32_t *b)
 {
   return vshlcq_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, uint32_t * b)
+foo1 (int16x8_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
index 2956b93138e..2c17845fd7e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, uint32_t * b)
+foo (int32x4_t a, uint32_t *b)
 {
   return vshlcq_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, uint32_t * b)
+foo1 (int32x4_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
index cc22b1b1bd9..ab55f3a29ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, uint32_t * b)
+foo (int8x16_t a, uint32_t *b)
 {
   return vshlcq_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, uint32_t * b)
+foo1 (int8x16_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
index bbf6c531573..e1862be0249 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint32_t * b)
+foo (uint16x8_t a, uint32_t *b)
 {
   return vshlcq_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b)
+foo1 (uint16x8_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
index c42d9c10afe..dc1030fbedf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32_t * b)
+foo (uint32x4_t a, uint32_t *b)
 {
   return vshlcq_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b)
+foo1 (uint32x4_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
index f24b22797c2..cb24651a294 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint32_t * b)
+foo (uint8x16_t a, uint32_t *b)
 {
   return vshlcq_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b)
+foo1 (uint8x16_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
index 6d6c4b2d737..1ee641d8d68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
index 5d7b9623f1a..93a06cb2676 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
index 3697775ea0f..67039260cd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
index 39a10e21b0b..f02293bb874 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
index 7d3a4d811cb..906f7fb75d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vshllbq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
index 63b406978c1..f63ff4b7556 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vshllbq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
index 9306d244645..883d2979f32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
   return vshllbq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
index 0b24160216e..bbdec7ba321 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
   return vshllbq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
index 689fc749b00..239c536f4a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_s16 (a, 1, p);
+  return vshllbq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
index 82f684d1cd5..9371b523c3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_s8 (a, 1, p);
+  return vshllbq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
index 5c51a4e4011..72f9aed343e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_u16 (a, 1, p);
+  return vshllbq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
index 5a713befb27..bd209428300 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_u8 (a, 1, p);
+  return vshllbq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
index 8153a570a9a..80035011527 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
index 3f47337c9b6..19e2f3c7469 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
index f5af1b31087..46af8731146 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
index 92154d25387..ed7814c39dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
index ced2aa64217..b2987300406 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vshlltq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
index 9fc0cd7ced9..c5b84aa5e2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vshlltq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
index 47b948e2468..358a5b4a3e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
   return vshlltq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
index eac7422a1f1..223649215a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
   return vshlltq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
index 0e9e789c1e0..12d55e49aed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_s16 (a, 1, p);
+  return vshlltq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
index 67966bed12c..dfad54a5eae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_s8 (a, 1, p);
+  return vshlltq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
index dedc795797e..e9077d26918 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_u16 (a, 1, p);
+  return vshlltq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
index a93c69d8d98..1d4d2795fa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_u8 (a, 1, p);
+  return vshlltq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
index 6c0342da0cc..754d412c81d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
index 0e472801de5..5805f90a105 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
index 0f9efacc749..b69b52cf099 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
index 0c4d9e9b7b5..152844bf318 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
index cf247f879aa..9acfd9b8c6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
index 64bda13216d..d2e7fe59f3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
index abd747e9008..ce72e8c408b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
index 001a8d170fc..219c7d2ca73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
index 890dd359e65..22fdee6bd6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
index 91574c5db26..25eca63907d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
index f6ec8797a83..9d24eda6e60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
index 37f0f488801..2421e0b72ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
index 759379c9fc5..c28996ad2cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
index 4878f0b0e4f..ca4801df9ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
index f4ed7f5aaeb..782eedbc774 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
index 99ae7ed9a53..941a6cc3578 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
index 7094ba2ccd7..75e10801ae7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
index e7c481a3b8c..dbabcd55900 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
index e24bb9acd75..83dee27238a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vshlq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
index f537879249f..6b390c8b333 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
-  return vshlq_n_s32 (a, 16);
+  return vshlq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
-  return vshlq_n (a, 16);
+  return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
index ba6ddf3f8a1..e4fd7121bff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vshlq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
index 730c7af40c6..6c37303a9fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-  return vshlq_n_u16 (a, 11);
+  return vshlq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-  return vshlq_n (a, 11);
+  return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
index 36caf5a9032..408f756408f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
   return vshlq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
index a5ba9805d9b..5ecdddccadf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
   return vshlq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
index b6d3e858d7c..f9a8257729e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vshlq_r_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
index e04e2a7bcf3..f4f8e363059 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vshlq_r_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
index d5e54c0a79a..c14d012a1e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vshlq_r_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
index 813bea0575d..71634680deb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vshlq_r_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
index 84a61e47ca7..0d47f85bc82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vshlq_r_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
index 01f9a7d8f19..2d64908eeca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vshlq_r_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
index 5d3e1e5fdf9..6158fafcdb5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
index cecd050888f..b0b18470dea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
index d44610f4f5b..70b2d806131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
index 210fa905d3d..3ab782fa734 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
index 8fc59620016..f104235caee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
index 8332d501640..1a93abfefb1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
index 4bdbc848bb7..5ac725187e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_s16 (a, 1, p);
+  return vshlq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
index 7648d2e2c66..e5e3ab03f01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_s32 (a, 1, p);
+  return vshlq_x_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
index 4b303e92e81..7618d83b85b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_s8 (a, 1, p);
+  return vshlq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
index a2b6ac2d4c0..b4f937ae8f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_u16 (a, 1, p);
+  return vshlq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
index 59aa9dbe182..e42270ba293 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_u32 (a, 1, p);
+  return vshlq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
index 64069bb1728..7e01f8b2ab5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_u8 (a, 1, p);
+  return vshlq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
index 61a643d64bd..a6eeff654e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-    return vshlq_x_s16 (a, b, p);
+  return vshlq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
index 71424456f7d..cc3c434708a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-    return vshlq_x_s32 (a, b, p);
+  return vshlq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
index 0d4825a03ad..430a3ab43ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-    return vshlq_x_s8 (a, b, p);
+  return vshlq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
index 7ce18722444..9f5d0903588 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-    return vshlq_x_u16 (a, b, p);
+  return vshlq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
index fe02cc694a2..32d729f6954 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-    return vshlq_x_u32 (a, b, p);
+  return vshlq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
index 9611b268ca5..45e72c9dffa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-    return vshlq_x_u8 (a, b, p);
+  return vshlq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
index d069cb0db44..ab37f2605e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_s16 (a, b, 8, p);
+  return vshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 8, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
index 50a450f5b52..9fd9f8a7804 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_s32 (a, b, 16, p);
+  return vshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 16, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
index e5762145e64..e9408eeb1bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_u16 (a, b, 8, p);
+  return vshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 8, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
index 88da8e6f341..69699fd15ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_u32 (a, b, 16, p);
+  return vshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 16, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
index 7fcd9e479dc..0320d690627 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
-  return vshrnbq_n_s16 (a, b, 8);
+  return vshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
-  return vshrnbq (a, b, 8);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
index 38d4fdfc05f..aa7b107f7f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
-  return vshrnbq_n_s32 (a, b, 16);
+  return vshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
-  return vshrnbq (a, b, 16);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
index ff341a9f202..4f896469eb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
-  return vshrnbq_n_u16 (a, b, 8);
+  return vshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
-  return vshrnbq (a, b, 8);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
index b891c036d36..d3d22978542 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
-  return vshrnbq_n_u32 (a, b, 16);
+  return vshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
-  return vshrnbq (a, b, 16);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
index 30535470961..77f39ac10c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_s16 (a, b, 8, p);
+  return vshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 8, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
index 2d52f5b6bb1..462d5f446f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_s32 (a, b, 16, p);
+  return vshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 16, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
index ed774e0b31a..0328cc3ef93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_u16 (a, b, 8, p);
+  return vshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 8, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
index e592e96a5f9..d4882dc2d6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_u32 (a, b, 16, p);
+  return vshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 16, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
index ddd9d5c0507..c9016ac124f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
-  return vshrntq_n_s16 (a, b, 8);
+  return vshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
-  return vshrntq (a, b, 8);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
index e35dbf07fac..6150f28d872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
-  return vshrntq_n_s32 (a, b, 16);
+  return vshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
-  return vshrntq (a, b, 16);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
index 58a6eea561a..75be307feaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
-  return vshrntq_n_u16 (a, b, 8);
+  return vshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
-  return vshrntq (a, b, 8);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
index ec0c10007ff..9b9e534e3d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
-  return vshrntq_n_u32 (a, b, 16);
+  return vshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
-  return vshrntq (a, b, 16);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
index 00f236c6d74..ed1833b8673 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_s16 (inactive, a, 16, p);
+  return vshrq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 16, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
index 1d1be501e16..880cd9e3545 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_s32 (inactive, a, 32, p);
+  return vshrq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 32, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
index 7410ba9c8e9..53fc84857b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_s8 (inactive, a, 8, p);
+  return vshrq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 8, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
index 4b0dd59eefa..c3e311454b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_u16 (inactive, a, 16, p);
+  return vshrq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 16, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
index 47ccc1b7499..6c0471f0120 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_u32 (inactive, a, 32, p);
+  return vshrq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 32, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
index 44f96027a04..5621608a2eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_u8 (inactive, a, 8, p);
+  return vshrq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 8, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
index 051fa4a14a1..59a589b21a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
-  return vshrq_n_s16 (a, 16);
+  return vshrq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
-  return vshrq (a, 16);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
index 65a0b2e6224..1666b6657f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
-  return vshrq_n_s32 (a, 32);
+  return vshrq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
-  return vshrq (a, 32);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
index c5adcc1a465..1ce29185bcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
-  return vshrq_n_s8 (a, 8);
+  return vshrq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
-  return vshrq (a, 8);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
index 1b68fafea8a..c2dbe6e5041 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-  return vshrq_n_u16 (a, 16);
+  return vshrq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-  return vshrq (a, 16);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
index 8b798b793c0..15d231c217f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-  return vshrq_n_u32 (a, 32);
+  return vshrq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-  return vshrq (a, 32);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
index 14cdf5917e2..19924e0fcdb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-  return vshrq_n_u8 (a, 8);
+  return vshrq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-  return vshrq (a, 8);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
index 4652693d75c..fc26fd8fd3b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_s16 (a, 16, p);
+  return vshrq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
index 43fa28a1f8d..bc9ae54faad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_s32 (a, 32, p);
+  return vshrq_x_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
index 042bf488284..391ced24079 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_s8 (a, 8, p);
+  return vshrq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
index d627565fe84..eddb977fa83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_u16 (a, 16, p);
+  return vshrq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
index 0f26e7b9efc..6867668d1ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_u8 (a, 8, p);
+  return vshrq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
index 49d342e7c17..23b346b1cab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_s16 (a, b, 15, p);
+  return vsliq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 15, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
index f0f7619dd0a..d640e1f8df4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_s32 (a, b, 31, p);
+  return vsliq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 31, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
index 12d295e70f6..14b1afa1d01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_s8 (a, b, 7, p);
+  return vsliq_m_n_s8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 7, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
index 78cdbdf3950..521abbf4694 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_u16 (a, b, 15, p);
+  return vsliq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 15, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
index 62e9cfd9f31..951204a31a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_u32 (a, b, 31, p);
+  return vsliq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 31, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
index f86fea32a90..8b893a8c4d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_u8 (a, b, 7, p);
+  return vsliq_m_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 7, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
index 2c5f82bb317..a6c86764eab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
-  return vsliq_n_s16 (a, b, 15);
+  return vsliq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
-  return vsliq (a, b, 15);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
index 0738fd61203..301cdd463b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
-  return vsliq_n_s32 (a, b, 31);
+  return vsliq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
-  return vsliq (a, b, 31);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
index 25f2f761c3c..2a26f7f444b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
-  return vsliq_n_s8 (a, b, 7);
+  return vsliq_n_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
-  return vsliq (a, b, 7);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
index 25bbcd8f3fa..b71572a232e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
-  return vsliq_n_u16 (a, b, 15);
+  return vsliq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
-  return vsliq (a, b, 15);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
index 970e069cabf..ecafb61b487 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
-  return vsliq_n_u32 (a, b, 31);
+  return vsliq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
-  return vsliq (a, b, 31);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
index c24e354a957..e20ec7e030e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
-  return vsliq_n_u8 (a, b, 7);
+  return vsliq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
-  return vsliq (a, b, 7);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
index 799232a8dc1..086f5f86fc1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_s16 (a, b, 4, p);
+  return vsriq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
index 7e019782c88..90267f67e54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_s32 (a, b, 2, p);
+  return vsriq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 2, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
index 8fa3e757f6d..6c7552905b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_s8 (a, b, 4, p);
+  return vsriq_m_n_s8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
index 5e2c4a3deb3..624732b0c91 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_u16 (a, b, 4, p);
+  return vsriq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
index 368115e27b2..48abe8b9c0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_u32 (a, b, 4, p);
+  return vsriq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
index 54db7d78836..b1f9ecd0c9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_u8 (a, b, 4, p);
+  return vsriq_m_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
index 75f57ae76a7..2f8bde64ff5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
-  return vsriq_n_s16 (a, b, 4);
+  return vsriq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
index 46d9ead1e9a..a95e6dae8f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
-  return vsriq_n_s32 (a, b, 4);
+  return vsriq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
index 3dcc5a34f90..7726a7ed934 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
-  return vsriq_n_s8 (a, b, 4);
+  return vsriq_n_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
index ff6c4f0c277..4d8d5930b49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
-  return vsriq_n_u16 (a, b, 4);
+  return vsriq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
index f6b79b26235..83a6b13ef40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
-  return vsriq_n_u32 (a, b, 4);
+  return vsriq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
index 4c56b3ab00d..0bd9ac5ddfd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
-  return vsriq_n_u8 (a, b, 4);
+  return vsriq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
index 312b7464f17..1fa02f00f53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (float16_t * addr, float16x8_t value)
-{
-  vst1q_f16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value)
+foo (float16_t *base, float16x8_t value)
 {
-  vst1q (addr, value);
+  return vst1q_f16 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrh.16" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (float16_t a, float16x8_t x)
+foo1 (float16_t *base, float16x8_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
index a6ae1cef2d4..67cc3ae3b47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value)
+foo (float32_t *base, float32x4_t value)
 {
-  vst1q_f32 (addr, value);
+  return vst1q_f32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value)
+foo1 (float32_t *base, float32x4_t value)
 {
-  vst1q (addr, value);
+  return vst1q (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
index f6db22d481a..06b2bd3910d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vst1q_p_f16 (addr, value, p);
+  return vst1q_p_f16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
index 17e7f9c5dfd..e492a705ea0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vst1q_p_f32 (addr, value, p);
+  return vst1q_p_f32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
index b142fc3b021..7b76d1d7687 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vst1q_p_s16 (addr, value, p);
+  return vst1q_p_s16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
index 6334462e230..4ad32a68a96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vst1q_p_s32 (addr, value, p);
+  return vst1q_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
index 1f3f0343820..2425b9cec00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vst1q_p_s8 (addr, value, p);
+  return vst1q_p_s8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
index 331cd34cdce..c0065ef6ff5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vst1q_p_u16 (addr, value, p);
+  return vst1q_p_u16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
index 27836c32451..c41c4184b9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vst1q_p_u32 (addr, value, p);
+  return vst1q_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
index bfbc542dc35..1cd3a781357 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vst1q_p_u8 (addr, value, p);
+  return vst1q_p_u8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
index cd14e2c408f..052959b2083 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (int16_t * addr, int16x8_t value)
-{
-  vst1q_s16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value)
+foo (int16_t *base, int16x8_t value)
 {
-  vst1q (addr, value);
+  return vst1q_s16 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrh.16" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (int16_t a, int16x8_t x)
+foo1 (int16_t *base, int16x8_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
index e07e8a30f9d..444ad07f4ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value)
+foo (int32_t *base, int32x4_t value)
 {
-  vst1q_s32 (addr, value);
+  return vst1q_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value)
+foo1 (int32_t *base, int32x4_t value)
 {
-  vst1q (addr, value);
+  return vst1q (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
index 0004c80963e..684ff0aca5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (int8_t * addr, int8x16_t value)
-{
-  vst1q_s8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value)
+foo (int8_t *base, int8x16_t value)
 {
-  vst1q (addr, value);
+  return vst1q_s8 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrb.8" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (int8_t a, int8x16_t x)
+foo1 (int8_t *base, int8x16_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
index 248e7ce82b0..1fea2de1e76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (uint16_t * addr, uint16x8_t value)
-{
-  vst1q_u16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t value)
 {
-  vst1q (addr, value);
+  return vst1q_u16 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrh.16" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (uint16_t a, uint16x8_t x)
+foo1 (uint16_t *base, uint16x8_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
index d1fdf8897b5..64c43c59d47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t value)
 {
-  vst1q_u32 (addr, value);
+  return vst1q_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t value)
 {
-  vst1q (addr, value);
+  return vst1q (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
index f8b48a69903..5517611bba6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (uint8_t * addr, uint8x16_t value)
-{
-  vst1q_u8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t value)
 {
-  vst1q (addr, value);
+  return vst1q_u8 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrb.8" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (uint8_t a, uint8x16_t x)
+foo1 (uint8_t *base, uint8x16_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
index c694e2b6ad3..25a889dd1f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p_s64 (addr, 8, value, p);
+  return vstrdq_scatter_base_p_s64 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p (addr, 8, value, p);
+  return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
index 6e8507c81d9..f0731f69a09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p_u64 (addr, 8, value, p);
+  return vstrdq_scatter_base_p_u64 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p (addr, 8, value, p);
+  return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
index b9aac8036d4..31cdec9ba0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, int64x2_t value)
+foo (uint64x2_t addr, int64x2_t value)
 {
-  vstrdq_scatter_base_s64 (addr, 1016, value);
+  return vstrdq_scatter_base_s64 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t addr, int64x2_t value)
 {
-  vstrdq_scatter_base (addr, 1016, value);
+  return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
index 888d4e0c031..8f0195c9e8f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, uint64x2_t value)
+foo (uint64x2_t addr, uint64x2_t value)
 {
-  vstrdq_scatter_base_u64 (addr, 8, value);
+  return vstrdq_scatter_base_u64 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t addr, uint64x2_t value)
 {
-  vstrdq_scatter_base (addr, 8, value);
+  return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
index 319188b706f..8f19ede4e1a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p_s64 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
index 940b5421c84..41958c961f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p_u64 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
index 33926d5c9e2..fc06db1c202 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, int64x2_t value)
+foo (uint64x2_t *addr, int64x2_t value)
 {
-  vstrdq_scatter_base_wb_s64 (addr, 8, value);
+  return vstrdq_scatter_base_wb_s64 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t *addr, int64x2_t value)
 {
-  vstrdq_scatter_base_wb (addr, 8, value);
+  return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
index b7ffcf9b5dd..c6529e617e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo (uint64x2_t *addr, uint64x2_t value)
 {
-  vstrdq_scatter_base_wb_u64 (addr, 8, value);
+  return vstrdq_scatter_base_wb_u64 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t *addr, uint64x2_t value)
 {
-  vstrdq_scatter_base_wb (addr, 8, value);
+  return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
index 7ebf858f816..754fb59df4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p_s64 (base, offset, value, p);
+  return vstrdq_scatter_offset_p_s64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p (base, offset, value, p);
+  return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
index 4829bada1a9..046f29a6621 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p_u64 (base, offset, value, p);
+  return vstrdq_scatter_offset_p_u64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p (base, offset, value, p);
+  return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
index fb7317bc4d7..73e25cdf0ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_offset_s64 (base, offset, value);
+  return vstrdq_scatter_offset_s64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_offset (base, offset, value);
+  return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
index e8b3a0210b4..d49adde0b94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_offset_u64 (base, offset, value);
+  return vstrdq_scatter_offset_u64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_offset (base, offset, value);
+  return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
index 9ca83e0f3fd..8acfba1f55e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
index 1c33df18e84..630c627d604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
index 8af348ddbe2..ec73bca4869 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_shifted_offset_s64 (base, offset, value);
+  return vstrdq_scatter_shifted_offset_s64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_shifted_offset (base, offset, value);
+  return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
index bc153a07192..9bdf8003961 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_shifted_offset_u64 (base, offset, value);
+  return vstrdq_scatter_shifted_offset_u64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_shifted_offset (base, offset, value);
+  return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit f51bc071a57fb07b33f0c200011ef319d1be397d
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 27 16:51:14 2023

    arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
    
    Hi all,
    
    We noticed that calls to the vadcq and vsbcq intrinsics, both of
    which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
    the FPSCR, would produce the following code:
    
    ```
    < r2 is the *carry input >
    vmrs    r3, FPSCR_nzcvqc
    bic     r3, r3, #536870912
    orr     r3, r3, r2, lsl #29
    vmsr    FPSCR_nzcvqc, r3
    ```
    
    when the MVE ACLE instead gives a different instruction sequence of:
    ```
    < Rt is the *carry input >
    VMRS Rs,FPSCR_nzcvqc
    BFI Rs,Rt,#29,#1
    VMSR FPSCR_nzcvqc,Rs
    ```
    
    the bic + orr pair is slower and it's also wrong, because, if the
    *carry input is greater than 1, then we risk overwriting the top two
    bits of the FPSCR register (the N and Z flags).
    
    This turned out to be a problem in the header file and the solution was
    to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
    that we only care about the lowest bit and can optimise to a BFI.
    
    Ok for trunk?
    
    Thanks,
    Stam Markianos-Wright
    
    gcc/ChangeLog:
    
            * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
            (__arm_vadcq_u32): Likewise.
            (__arm_vadcq_m_s32): Likewise.
            (__arm_vadcq_m_u32): Likewise.
            (__arm_vsbcq_s32): Likewise.
            (__arm_vsbcq_u32): Likewise.
            (__arm_vsbcq_m_s32): Likewise.
            (__arm_vsbcq_m_u32): Likewise.
            * config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New.
    
    (cherry picked from commit f1417d051be094ffbce228e11951f3e12e8fca1c)

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 82ceec2bbfc..6bf1794d2ff 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res =  __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res =  __builtin_mve_vsbcq_uv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 1d5721df3e8..860d734b9a1 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -9775,7 +9775,7 @@
 
 (define_insn "get_fpscr_nzcvqc"
  [(set (match_operand:SI 0 "register_operand" "=r")
-   (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))]
+   (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))]
  "TARGET_HAVE_MVE"
  "vmrs\\t%0, FPSCR_nzcvqc"
   [(set_attr "type" "mve_move")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
new file mode 100644
index 00000000000..a8c6cce67c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include <arm_mve.h>
+
+volatile int32x4_t c1;
+volatile uint32x4_t c2;
+int *carry;
+
+int
+main ()
+{
+  int32x4_t a1 = vcreateq_s32 (0, 0);
+  int32x4_t b1 = vcreateq_s32 (0, 0);
+  int32x4_t inactive1 = vcreateq_s32 (0, 0);
+
+  uint32x4_t a2 = vcreateq_u32 (0, 0);
+  uint32x4_t b2 = vcreateq_u32 (0, 0);
+  uint32x4_t inactive2 = vcreateq_u32 (0, 0);
+
+  mve_pred16_t p = 0xFFFF;
+  (*carry) = 0xFFFFFFFF;
+
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vadcq (a1, b1, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vadcq (a2, b2, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vsbcq (a1, b1, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vsbcq (a2, b2, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vadcq_m (inactive1, a1, b1, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vadcq_m (inactive2, a2, b2, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vsbcq_m (inactive1, a1, b1, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vsbcq_m (inactive2, a2, b2, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+
+  return 0;
+}

commit 15fbceddeef868b9fa7ebdf3b20aac9ac0afb9a2
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 27 16:51:37 2023

    arm: Add vorrq_n overloading into vorrq _Generic
    
    We found this as part of the wider testsuite updates.
    
    The applicable tests are authored by Andrea earlier in this patch series
    
    Ok for trunk?
    
    gcc/ChangeLog:
    
            * config/arm/arm_mve.h (__arm_vorrq): Add _n variant.

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 6bf1794d2ff..39b3446617d 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35852,6 +35852,10 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
 
@@ -38637,7 +38641,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
 
 #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \

commit eaae2bf98ddb7d4cea34dd44c6ecfdbf23b3065b
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 27 16:52:05 2023

    arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m
    
    We found this as part of the wider testsuite updates.
    
    The applicable tests are authored by Andrea earlier in this patch series
    
    Ok for trunk?
    
    gcc/ChangeLog:
    
            * config/arm/arm_mve.h (__arm_vbicq): Change coerce on
            scalar constant.
            (__arm_vmvnq_m): Likewise.

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 39b3446617d..0b35bd0eedd 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35906,10 +35906,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38825,10 +38825,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -40962,10 +40962,10 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));})
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int) , p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int) , p2));})
 
 #define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \

commit 5d013704c80b6211e6af60beae6cda4bd271ddbe
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 27 16:52:56 2023

    arm: Fix MVE header pointer overloads this time (and a bit more tidying)
    
    Hi all,
    
    Previously we had fixed the overloading of scalar arguments to intrinsics
    with the introduction of a new `__ARM_mve_coerce3` _ Generic association.
    This allowed users to give types other than int32_t, e.g. int, short, long,
    etc., which previously would emit a nonsensical error message from the
    _Generic.
    
    Here I adjust that handling slightly and I am also doing the same thing, but
    for pointer types:
    (un)signed char* can be now used instead of (u)int8_t*
    (un)signed short* can be now used instead of (u)int16_t*
    (un)signed int* and long* can be now used instead of (u)int32_t*
    (un)signed long long* can be now used instead of (u)int64_t*
    __fp16* and _Float16* can be now used instead of float16_t*
    float* can be now used instead of float32_t*
    
    This required me to break down the _coerce_ generics for the specific
    pointer types.
    On the scalar types, the change in this patch is minor, renaming the
    _coerce_ generics and passing all scalars through the `__typeof` for
    consistency with each-other.
    
    No test regressions in the GCC testsuite or CMSIS-NN.
    
    gcc/ChangeLog:
    
            * config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types.
            (__ARM_mve_coerce1): Remove.
            (__ARM_mve_coerce2): Remove.
            (__ARM_mve_coerce3): Remove.
            (__ARM_mve_coerce_i_scalar): New.
            (__ARM_mve_coerce_s8_ptr): New.
            (__ARM_mve_coerce_u8_ptr): New.
            (__ARM_mve_coerce_s16_ptr): New.
            (__ARM_mve_coerce_u16_ptr): New.
            (__ARM_mve_coerce_s32_ptr): New.
            (__ARM_mve_coerce_u32_ptr): New.
            (__ARM_mve_coerce_s64_ptr): New.
            (__ARM_mve_coerce_u64_ptr): New.
            (__ARM_mve_coerce_f_scalar): New.
            (__ARM_mve_coerce_f16_ptr): New.
            (__ARM_mve_coerce_f32_ptr): New.
            (__arm_vst4q): Change _coerce_ overloads.
            (__arm_vbicq): Change _coerce_ overloads.
            (__arm_vmulq): Change _coerce_ overloads.
            (__arm_vcmpeqq): Change _coerce_ overloads.
            (__arm_vcmpneq): Change _coerce_ overloads.
            (__arm_vmaxnmavq): Change _coerce_ overloads.
            (__arm_vmaxnmvq): Change _coerce_ overloads.
            (__arm_vminnmavq): Change _coerce_ overloads.
            (__arm_vsubq): Change _coerce_ overloads.
            (__arm_vminnmvq): Change _coerce_ overloads.
            (__arm_vrshlq): Change _coerce_ overloads.
            (__arm_vqsubq): Change _coerce_ overloads.
            (__arm_vqdmulltq): Change _coerce_ overloads.
            (__arm_vqdmullbq): Change _coerce_ overloads.
            (__arm_vqdmulhq): Change _coerce_ overloads.
            (__arm_vqaddq): Change _coerce_ overloads.
            (__arm_vhaddq): Change _coerce_ overloads.
            (__arm_vhsubq): Change _coerce_ overloads.
            (__arm_vqdmlashq): Change _coerce_ overloads.
            (__arm_vqrdmlahq): Change _coerce_ overloads.
            (__arm_vmlasq): Change _coerce_ overloads.
            (__arm_vqdmlahq): Change _coerce_ overloads.
            (__arm_vmaxnmavq_p): Change _coerce_ overloads.
            (__arm_vmaxnmvq_p): Change _coerce_ overloads.
            (__arm_vminnmavq_p): Change _coerce_ overloads.
            (__arm_vminnmvq_p): Change _coerce_ overloads.
            (__arm_vfmasq_m): Change _coerce_ overloads.
            (__arm_vld1q): Change _coerce_ overloads.
            (__arm_vld1q_z): Change _coerce_ overloads.
            (__arm_vld2q): Change _coerce_ overloads.
            (__arm_vld4q): Change _coerce_ overloads.
            (__arm_vldrhq_gather_offset): Change _coerce_ overloads.
            (__arm_vldrhq_gather_offset_z): Change _coerce_ overloads.
            (__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads.
            (__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads.
            (__arm_vldrwq_gather_offset): Change _coerce_ overloads.
            (__arm_vldrwq_gather_offset_z): Change _coerce_ overloads.
            (__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads.
            (__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads.
            (__arm_vst1q_p): Change _coerce_ overloads.
            (__arm_vst2q): Change _coerce_ overloads.
            (__arm_vst1q): Change _coerce_ overloads.
            (__arm_vstrhq): Change _coerce_ overloads.
            (__arm_vstrhq_p): Change _coerce_ overloads.
            (__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads.
            (__arm_vstrhq_scatter_offset): Change _coerce_ overloads.
            (__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads.
            (__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads.
            (__arm_vstrwq_p): Change _coerce_ overloads.
            (__arm_vstrwq): Change _coerce_ overloads.
            (__arm_vstrwq_scatter_offset): Change _coerce_ overloads.
            (__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads.
            (__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads.
            (__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads.
            (__arm_vsetq_lane): Change _coerce_ overloads.
            (__arm_vcmpneq_m): Change _coerce_ overloads.
            (__arm_vldrbq_gather_offset): Change _coerce_ overloads.
            (__arm_vdwdupq_x_u8): Change _coerce_ overloads.
            (__arm_vdwdupq_x_u16): Change _coerce_ overloads.
            (__arm_vdwdupq_x_u32): Change _coerce_ overloads.
            (__arm_viwdupq_x_u8): Change _coerce_ overloads.
            (__arm_viwdupq_x_u16): Change _coerce_ overloads.
            (__arm_viwdupq_x_u32): Change _coerce_ overloads.
            (__arm_vidupq_x_u8): Change _coerce_ overloads.
            (__arm_vddupq_x_u8): Change _coerce_ overloads.
            (__arm_vidupq_x_u16): Change _coerce_ overloads.
            (__arm_vddupq_x_u16): Change _coerce_ overloads.
            (__arm_vidupq_x_u32): Change _coerce_ overloads.
            (__arm_vddupq_x_u32): Change _coerce_ overloads.
            (__arm_vhaddq_x): Change _coerce_ overloads.
            (__arm_vhsubq_x): Change _coerce_ overloads.
            (__arm_vldrdq_gather_offset): Change _coerce_ overloads.
            (__arm_vldrdq_gather_offset_z): Change _coerce_ overloads.
            (__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads.
            (__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads.
            (__arm_vldrbq_gather_offset_z): Change _coerce_ overloads.
            (__arm_vqrdmlahq_m): Change _coerce_ overloads.
            (__arm_vqrdmlashq_m): Change _coerce_ overloads.
            (__arm_vqdmlashq_m): Change _coerce_ overloads.
            (__arm_vmlaldavaxq_p): Change _coerce_ overloads.
            (__arm_vmlasq_m): Change _coerce_ overloads.
            (__arm_vqdmulhq_m): Change _coerce_ overloads.
            (__arm_vqdmulltq_m): Change _coerce_ overloads.
            (__arm_vidupq_u16): Change _coerce_ overloads.
            (__arm_vidupq_u32): Change _coerce_ overloads.
            (__arm_vidupq_u8): Change _coerce_ overloads.
            (__arm_vddupq_u16): Change _coerce_ overloads.
            (__arm_vddupq_u32): Change _coerce_ overloads.
            (__arm_vddupq_u8): Change _coerce_ overloads.
            (__arm_viwdupq_m): Change _coerce_ overloads.
            (__arm_viwdupq_u16): Change _coerce_ overloads.
            (__arm_viwdupq_u32): Change _coerce_ overloads.
            (__arm_viwdupq_u8): Change _coerce_ overloads.
            (__arm_vdwdupq_m): Change _coerce_ overloads.
            (__arm_vdwdupq_u16): Change _coerce_ overloads.
            (__arm_vdwdupq_u32): Change _coerce_ overloads.
            (__arm_vdwdupq_u8): Change _coerce_ overloads.
            (__arm_vaddlvaq): Change _coerce_ overloads.
            (__arm_vaddlvaq_p): Change _coerce_ overloads.
            (__arm_vaddvaq): Change _coerce_ overloads.
            (__arm_vaddvaq_p): Change _coerce_ overloads.
            (__arm_vcmphiq_m): Change _coerce_ overloads.
            (__arm_vmladavaq_p): Change _coerce_ overloads.
            (__arm_vmladavaxq): Change _coerce_ overloads.
            (__arm_vmlaldavaxq): Change _coerce_ overloads.
            (__arm_vstrbq): Change _coerce_ overloads.
            (__arm_vstrbq_p): Change _coerce_ overloads.
            (__arm_vrmlaldavhaq_p): Change _coerce_ overloads.
            (__arm_vstrbq_scatter_offset): Change _coerce_ overloads.
            (__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads.
            (__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads.
            (__arm_vstrdq_scatter_offset): Change _coerce_ overloads.
            (__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads.
            (__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Add testcases.
            * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Add testcases.

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 0b35bd0eedd..c359e9c6336 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35582,16 +35582,29 @@ enum {
 	short: __ARM_mve_type_int_n, \
 	int: __ARM_mve_type_int_n, \
 	long: __ARM_mve_type_int_n, \
+	long long: __ARM_mve_type_int_n, \
 	_Float16: __ARM_mve_type_fp_n, \
 	__fp16: __ARM_mve_type_fp_n, \
 	float: __ARM_mve_type_fp_n, \
 	double: __ARM_mve_type_fp_n, \
-	long long: __ARM_mve_type_int_n, \
 	unsigned char: __ARM_mve_type_int_n, \
 	unsigned short: __ARM_mve_type_int_n, \
 	unsigned int: __ARM_mve_type_int_n, \
 	unsigned long: __ARM_mve_type_int_n, \
 	unsigned long long: __ARM_mve_type_int_n, \
+	signed char*: __ARM_mve_type_int8_t_ptr, \
+	short*: __ARM_mve_type_int16_t_ptr, \
+	int*: __ARM_mve_type_int32_t_ptr, \
+	long*: __ARM_mve_type_int32_t_ptr, \
+	long long*: __ARM_mve_type_int64_t_ptr, \
+	_Float16*: __ARM_mve_type_float16_t_ptr, \
+	__fp16*: __ARM_mve_type_float16_t_ptr, \
+	float*: __ARM_mve_type_float32_t_ptr, \
+	unsigned char*: __ARM_mve_type_uint8_t_ptr, \
+	unsigned short*: __ARM_mve_type_uint16_t_ptr, \
+	unsigned int*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
 	default: __ARM_mve_unsupported_type))
 #else
 #define __ARM_mve_typeid(x) _Generic(x, \
@@ -35650,32 +35663,67 @@ enum {
 	unsigned int: __ARM_mve_type_int_n, \
 	unsigned long: __ARM_mve_type_int_n, \
 	unsigned long long: __ARM_mve_type_int_n, \
+	signed char*: __ARM_mve_type_int8_t_ptr, \
+	short*: __ARM_mve_type_int16_t_ptr, \
+	int*: __ARM_mve_type_int32_t_ptr, \
+	long*: __ARM_mve_type_int32_t_ptr, \
+	long long*: __ARM_mve_type_int64_t_ptr, \
+	unsigned char*: __ARM_mve_type_uint8_t_ptr, \
+	unsigned short*: __ARM_mve_type_uint16_t_ptr, \
+	unsigned int*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
 	default: __ARM_mve_unsupported_type))
 #endif /* MVE Floating point.  */
 
 extern void *__ARM_undef;
 #define __ARM_mve_coerce(param, type) \
     _Generic(param, type: param, default: *(type *)__ARM_undef)
-#define __ARM_mve_coerce1(param, type) \
-    _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef)
-#define __ARM_mve_coerce2(param, type) \
-    _Generic(param, type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef))
-#define __ARM_mve_coerce3(param, type) \
-    _Generic(param, type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_i_scalar(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s8_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, signed char*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u8_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned char*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s16_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, short*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u16_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned short*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s32_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, int*: param, long*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u32_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned int*: param, unsigned long*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s64_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, long long*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u64_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned long long*: param, default: *(type *)__ARM_undef))
+
+#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
+#define __ARM_mve_coerce_f_scalar(param, type) \
+    _Generic(param, type: param, const type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_f16_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, __fp16*: param, _Float16*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_f32_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, float*: param, default: *(type *)__ARM_undef))
+#endif
 
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
 #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce_f16_ptr(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
 
 #define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -35852,10 +35900,10 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
 
@@ -35882,14 +35930,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -35906,10 +35954,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35934,14 +35982,14 @@ extern void *__ARM_undef;
 #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35966,14 +36014,14 @@ extern void *__ARM_undef;
 #define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36004,16 +36052,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36021,13 +36069,13 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36037,11 +36085,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36049,25 +36097,25 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36122,8 +36170,8 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36134,14 +36182,14 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36152,8 +36200,8 @@ extern void *__ARM_undef;
 #define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36175,14 +36223,14 @@ extern void *__ARM_undef;
 #define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36195,8 +36243,8 @@ extern void *__ARM_undef;
 #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36251,12 +36299,12 @@ extern void *__ARM_undef;
 #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36287,12 +36335,12 @@ extern void *__ARM_undef;
 #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36343,12 +36391,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36356,9 +36404,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36391,8 +36439,8 @@ extern void *__ARM_undef;
 #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
@@ -36405,17 +36453,17 @@ extern void *__ARM_undef;
 #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
 #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -36423,12 +36471,12 @@ extern void *__ARM_undef;
 #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36461,12 +36509,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36491,12 +36539,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36639,12 +36687,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36723,44 +36771,44 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36950,11 +36998,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
@@ -36966,11 +37014,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36980,11 +37028,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36997,14 +37045,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37058,8 +37106,8 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));})
 
@@ -37074,8 +37122,8 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)));})
 
 #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37098,14 +37146,14 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37116,14 +37164,14 @@ extern void *__ARM_undef;
 #define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37185,13 +37233,13 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37292,11 +37340,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
@@ -37325,14 +37373,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37473,15 +37521,15 @@ extern void *__ARM_undef;
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37516,14 +37564,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37550,14 +37598,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37574,236 +37622,236 @@ extern void *__ARM_undef;
 
 #define __arm_vld1q(p0) (\
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
 
 #define __arm_vld1q_z(p0,p1) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), p1), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
 
 #define __arm_vld2q(p0) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
 
 #define __arm_vld4q(p0) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
 
 #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
 
 #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
 
 #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
 
 #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
 
 #define __arm_vldrwq_gather_offset(p0,p1) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
 
 #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2)))
 
 #define __arm_vldrwq_gather_shifted_offset(p0,p1) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
 
 #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2)))
 
 #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));})
 
 #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));})
 
 #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -37820,44 +37868,44 @@ extern void *__ARM_undef;
 #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));})
 
 #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
 
 #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
 
 #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38030,19 +38078,19 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -38165,19 +38213,19 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -38266,19 +38314,19 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vcmulq_rot90_x(p1,p2,p3)  ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -38302,16 +38350,16 @@ extern void *__ARM_undef;
 #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #else /* MVE Integer.  */
 
@@ -38327,12 +38375,12 @@ extern void *__ARM_undef;
 
 #define __arm_vst4q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));})
 
 #define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38429,12 +38477,12 @@ extern void *__ARM_undef;
 #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38461,12 +38509,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38480,12 +38528,12 @@ extern void *__ARM_undef;
 #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38516,12 +38564,12 @@ extern void *__ARM_undef;
 #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38590,12 +38638,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38603,16 +38651,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -38620,12 +38668,12 @@ extern void *__ARM_undef;
 #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38642,10 +38690,10 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38660,12 +38708,12 @@ extern void *__ARM_undef;
 #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38740,12 +38788,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38770,12 +38818,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38825,10 +38873,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38845,12 +38893,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38881,12 +38929,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38967,16 +39015,16 @@ extern void *__ARM_undef;
 #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
 #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
@@ -38986,9 +39034,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38996,9 +39044,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39006,9 +39054,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39016,20 +39064,20 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
@@ -39054,12 +39102,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -39169,25 +39217,25 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39250,9 +39298,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 
 #define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
@@ -39261,9 +39309,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39271,9 +39319,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39281,9 +39329,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39294,12 +39342,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39322,23 +39370,23 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39363,9 +39411,9 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39528,12 +39576,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39633,12 +39681,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39666,12 +39714,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39683,12 +39731,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39703,12 +39751,12 @@ extern void *__ARM_undef;
 
 #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -39717,144 +39765,144 @@ extern void *__ARM_undef;
 
 #define __arm_vld1q(p0) (\
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
 
 #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));})
 
 #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 
 #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -39869,58 +39917,58 @@ extern void *__ARM_undef;
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -40025,15 +40073,15 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -40127,15 +40175,15 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -40219,29 +40267,29 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
 
 #define __arm_vld1q_z(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1)))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1)))
 
 #define __arm_vld2q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
 
 
 #define __arm_vld4q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
 
 #define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -40249,15 +40297,15 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -40273,14 +40321,14 @@ extern void *__ARM_undef;
 #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
 
 #endif /* MVE Integer.  */
 
@@ -40391,62 +40439,62 @@ extern void *__ARM_undef;
 #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u8 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u8 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u16 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u16 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u32 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u32 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -40460,12 +40508,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40490,12 +40538,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40535,20 +40583,20 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
 
 #define __arm_vldrdq_gather_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1)))
 
 #define __arm_vldrdq_gather_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2)))
 
 #define __arm_vldrdq_gather_shifted_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1)))
 
 #define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2)))
 
 #define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40604,36 +40652,36 @@ extern void *__ARM_undef;
 
 #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40734,12 +40782,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40754,9 +40802,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40882,17 +40930,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
 #define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40962,10 +41010,10 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int) , p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int) , p2));})
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2));})
 
 #define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41031,12 +41079,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -41070,12 +41118,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41103,23 +41151,23 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41165,12 +41213,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -41182,17 +41230,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
@@ -41203,15 +41251,15 @@ extern void *__ARM_undef;
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
-  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
@@ -41277,9 +41325,9 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
 #define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41290,12 +41338,12 @@ extern void *__ARM_undef;
 
 #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
  __typeof(p1) __p1 = (p1); \
@@ -41303,9 +41351,9 @@ extern void *__ARM_undef;
  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
  __typeof(p1) __p1 = (p1); \
@@ -41313,89 +41361,89 @@ extern void *__ARM_undef;
  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u16 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u32 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u8 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u16 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u32 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u8 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, (const int) p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, (const int) p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, (const int) p2));})
 
 #define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41431,14 +41479,14 @@ extern void *__ARM_undef;
 #define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41453,22 +41501,22 @@ extern void *__ARM_undef;
 #define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41494,9 +41542,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41504,9 +41552,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41514,16 +41562,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
@@ -41620,34 +41668,34 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41690,17 +41738,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
 
 #define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41864,22 +41912,22 @@ extern void *__ARM_undef;
 
 #define __arm_vstrbq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -41895,61 +41943,61 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
 
 #define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
 
 #define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
 
 #define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
 
 #endif /* __cplusplus  */
 #endif /* __ARM_FEATURE_MVE  */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
index a2787a47859..ee52be54f7b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
@@ -1,6 +1,7 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */
 #include "arm_mve.h"
 
 float f1;
@@ -8,37 +9,18 @@ double f2;
 float16_t f3;
 float32_t f4;
 __fp16 f5;
+#ifndef __cplusplus
 _Float16 f6;
-
-int i1;
-short i2;
-long i3;
-long long i4;
-int8_t i5;
-int16_t i6;
-int32_t i7;
-int64_t i8;
+#endif
 
 float16x8_t floatvec;
-int16x8_t intvec;
 
-void test(void)
+/* Test a few different supported ways of passing a scalar int value.
+The intrinsic vmulq was chosen arbitrarily, but it is representative of
+all intrinsics that take a non-const scalar value.  */
+void
+test_scalars (void)
 {
-    /* Test a few different supported ways of passing an int value.  The
-    intrinsic vmulq was chosen arbitrarily, but it is representative of
-    all intrinsics that take a non-const scalar value.  */
-    intvec = vmulq(intvec, 2);
-    intvec = vmulq(intvec, (int32_t) 2);
-    intvec = vmulq(intvec, (short) 2);
-    intvec = vmulq(intvec, i1);
-    intvec = vmulq(intvec, i2);
-    intvec = vmulq(intvec, i3);
-    intvec = vmulq(intvec, i4);
-    intvec = vmulq(intvec, i5);
-    intvec = vmulq(intvec, i6);
-    intvec = vmulq(intvec, i7);
-    intvec = vmulq(intvec, i8);
-
     /* Test a few different supported ways of passing a float value.  */
     floatvec = vmulq(floatvec, 0.5);
     floatvec = vmulq(floatvec, 0.5f);
@@ -48,9 +30,32 @@ void test(void)
     floatvec = vmulq(floatvec, f3);
     floatvec = vmulq(floatvec, f4);
     floatvec = vmulq(floatvec, f5);
+#ifndef __cplusplus
     floatvec = vmulq(floatvec, f6);
     floatvec = vmulq(floatvec, 0.15f16);
     floatvec = vmulq(floatvec, (_Float16) 0.15);
+#endif
+}
+
+/* Next, test a number of valid pointer overloads.  */
+void
+foo11 (__fp16 * addr, float16x8_t value)
+{
+  vst1q (addr, value);
+}
+
+#ifndef __cplusplus
+void
+foo12 (_Float16 * addr, float16x8_t value)
+{
+  vst1q (addr, value);
+}
+#endif
+
+void
+foo13 (float * addr, float32x4_t value)
+{
+  vst1q (addr, value);
 }
 
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
index 7b88f462e17..7947dc024bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
@@ -1,7 +1,7 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
-
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */
 #include "arm_mve.h"
 
 int i1;
@@ -15,11 +15,12 @@ int64_t i8;
 
 int16x8_t intvec;
 
-void test(void)
+/* Test a few different supported ways of passing a scalar int value.
+The intrinsic vmulq was chosen arbitrarily, but it is representative of
+all intrinsics that take a non-const scalar value.  */
+void
+test_scalars (void)
 {
-    /* Test a few different supported ways of passing an int value.  The
-    intrinsic vmulq was chosen arbitrarily, but it is representative of
-    all intrinsics that take a non-const scalar value.  */
     intvec = vmulq(intvec, 2);
     intvec = vmulq(intvec, (int32_t) 2);
     intvec = vmulq(intvec, (short) 2);
@@ -33,4 +34,65 @@ void test(void)
     intvec = vmulq(intvec, i8);
 }
 
+/* Next, test a number of valid pointer overloads.  */
+void
+foo1 (signed char * addr, int8x16_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo2 (short * addr, int16x8_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo3 (int * addr, int32x4_t value)
+{
+  vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
+}
+
+void
+foo4 (long * addr, int32x4_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo5 (long long * addr, uint64x2_t value)
+{
+  vldrdq_gather_offset (addr, value);
+}
+
+void
+foo6 (unsigned char * addr, uint8x16_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo7 (unsigned short * addr, uint16x8_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo8 (unsigned int * addr, uint32x4_t value)
+{
+  vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
+}
+
+void
+foo9 (unsigned long * addr, uint32x4_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo10 (unsigned long long * addr, uint64x2_t value)
+{
+  vldrdq_gather_offset (addr, value);
+}
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit 379f99f1d7aaab7953530513902edb0a167318af
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 27 16:53:45 2023

    arm testsuite: Remove reduntant tests
    
    Following Andrea's overhaul of the MVE testsuite, these tests are now
    reduntant, as equivalent checks have been added to the each intrinsic's
    <intrinsic name>.c test.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: Removed.
            * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: Removed.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed.
            * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed.

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
deleted file mode 100644
index 714fbf9bfe7..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-int8x16_t foo (int8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int16x8_t foo1 (int16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int32x4_t foo2 (int32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint8x16_t foo3 (uint8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint16x8_t foo4 (uint16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint32x4_t foo5 (uint32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-float16x8_t foo6 (float16x8_t a)
-{
-  return vaddq (a, (float16_t)23.6);
-}
-float32x4_t foo7 (float32x4_t a)
-{
-  return vaddq (a, (float32_t)23.46);
-}
-float16x8_t foo8 (float16x8_t a)
-{
-  return vaddq (a, 23.6);
-}
-float32x4_t foo9 (float32x4_t a)
-{
-  return vaddq (a, 23.46);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
deleted file mode 100644
index 719b95d9020..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-mve_pred16_t p;
-
-int32x4_t fn1 (int32x4_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_s32(), vecIdx, 1, p);
-}
-
-int16x8_t fn2 (int16x8_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_s16(), vecIdx, 1, p);
-}
-
-int8x16_t fn3 (int8x16_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_s8(), vecIdx, 1, p);
-}
-
-uint32x4_t fn4 (uint32x4_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_u32(), vecIdx, 1, p);
-}
-
-uint16x8_t fn5 (uint16x8_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_u16(), vecIdx, 1, p);
-}
-
-uint8x16_t fn6 (uint8x16_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_u8(), vecIdx, 1, p);
-}
-
-float32x4_t fn7 (float32x4_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_f32(), vecIdx, (float32_t) 1.23, p);
-}
-
-float16x8_t fn8 (float16x8_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_f16(), vecIdx, (float16_t) 1.40, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
deleted file mode 100644
index baa7fabe061..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-int8x16_t foo (int8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int16x8_t foo1 (int16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int32x4_t foo2 (int32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint8x16_t foo3 (uint8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint16x8_t foo4 (uint16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint32x4_t foo5 (uint32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
deleted file mode 100644
index 15587802925..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vddupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
deleted file mode 100644
index 8a9ed6327d3..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vddupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
deleted file mode 100644
index fe4aceeea97..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vddupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
deleted file mode 100644
index 05a68cbe559..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a)
-{
-  return vddupq_u16 (a, 4);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
deleted file mode 100644
index f702c4cdb0a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a)
-{
-  return vddupq_u32 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
deleted file mode 100644
index f272056c423..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a)
-{
-  return vddupq_u8 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
deleted file mode 100644
index 31e37827e60..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vddupq_x_u16 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
deleted file mode 100644
index 9989d0b0f00..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vddupq_x_u32 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
deleted file mode 100644
index 19f1501fe4e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint8x16_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vddupq_x_u8 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
deleted file mode 100644
index 07ea2d7d14c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return vdwdupq_x_u16 (a, b, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
deleted file mode 100644
index 9889b0b2b66..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return vdwdupq_x_u32 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
deleted file mode 100644
index 13ad8d69e18..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return vdwdupq_x_u8 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
deleted file mode 100644
index cbe998e2faa..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vidupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
deleted file mode 100644
index c9aa5c661de..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vidupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
deleted file mode 100644
index 7b075744d9a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vidupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
deleted file mode 100644
index a461a1e64b1..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a)
-{
-  return vidupq_u16 (a, 4);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
deleted file mode 100644
index c5b01a7ac90..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a)
-{
-  return vidupq_u32 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
deleted file mode 100644
index f963d51ac0f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a)
-{
-  return vidupq_u8 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
deleted file mode 100644
index aecd4be5e71..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vidupq_x_u16 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
deleted file mode 100644
index d3d33053f92..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vidupq_x_u32 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
deleted file mode 100644
index f71953aeef4..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint8x16_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vidupq_x_u8 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
deleted file mode 100644
index 312966773e6..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return viwdupq_x_u16 (a, b, 2, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
deleted file mode 100644
index a5d758126d4..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return viwdupq_x_u32 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
deleted file mode 100644
index aa4e7375d39..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return viwdupq_x_u8 (a, b, 8, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c
deleted file mode 100644
index e5b635983bf..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c
deleted file mode 100644
index 8d96527c6df..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c
deleted file mode 100644
index e66e4465b19..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c
deleted file mode 100644
index 7ca9590c12c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c
deleted file mode 100644
index b8491680536..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c
deleted file mode 100644
index 851d4a1f435..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c
deleted file mode 100644
index 586e38cfe43..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c
deleted file mode 100644
index dd6f482422f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c
deleted file mode 100644
index 3c0ae4b4262..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c
deleted file mode 100644
index bc7a51b38a5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c
deleted file mode 100644
index d6e83072995..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c
deleted file mode 100644
index 21b0b1cf52e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c
deleted file mode 100644
index 3a9c47e9c47..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c
deleted file mode 100644
index e31d0bc05bb..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c
deleted file mode 100644
index 6a40159be42..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c
deleted file mode 100644
index 1d9a70db727..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c
deleted file mode 100644
index 8fedbef9aef..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c
deleted file mode 100644
index db410437c02..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c
deleted file mode 100644
index c12bd91a733..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c
deleted file mode 100644
index df291626299..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c
deleted file mode 100644
index 9bc6627accf..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c
deleted file mode 100644
index c470871617d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c
deleted file mode 100644
index 2d4fe4c1d25..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c
deleted file mode 100644
index 755540d93b6..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c
deleted file mode 100644
index b9fc8d3242b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c
deleted file mode 100644
index c65df114f15..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c
deleted file mode 100644
index 8bb493bc6c0..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c
deleted file mode 100644
index cac933f0f36..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c
deleted file mode 100644
index 6d10e1ce9e8..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c
deleted file mode 100644
index 0f29a6a8aa1..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c
deleted file mode 100644
index 29e231757ec..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c
deleted file mode 100644
index 77a949fc1a6..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c
deleted file mode 100644
index 849783ab89f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c
deleted file mode 100644
index 3fe47cbeab5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c
deleted file mode 100644
index 0d166348de5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c
deleted file mode 100644
index 78e520b159e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c
deleted file mode 100644
index 6b8b72818d9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c
deleted file mode 100644
index db79e57a2f5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c
deleted file mode 100644
index e060fee10ca..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c
deleted file mode 100644
index 72446470ae3..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c
deleted file mode 100644
index 62dfb450a6d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int
-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[4]);
-    vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foowf32( float32_t * pDataSrc, float32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    float32x4_t vecIn1 = vldrwq_f32 ((float32_t const *) pDataSrc);
-    float32x4_t vecIn2 = vldrwq_f32 ((float32_t const *) &pDataSrc[4]);
-    vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    uint16x8_t vecIn1 = vldrhq_u16 ((uint16_t const *) pDataSrc);
-    uint16x8_t vecIn2 = vldrhq_u16 ((uint16_t const *) &pDataSrc[8]);
-    vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrhq_u32 ((uint16_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrhq_u32 ((uint16_t const *) &pDataSrc[4]);
-    vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohf16( float16_t * pDataSrc, float16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    float16x8_t vecIn1 = vldrhq_f16 ((float16_t const *) pDataSrc);
-    float16x8_t vecIn2 = vldrhq_f16 ((float16_t const *) &pDataSrc[8]);
-    vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[2]);
-
-    vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1);
-    vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-int
-foows32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
-    int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[4]);
-    vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohs16( int16_t * pDataSrc, int16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    int16x8_t vecIn1 = vldrhq_s16 ((int16_t const *) pDataSrc);
-    int16x8_t vecIn2 = vldrhq_s16 ((int16_t const *) &pDataSrc[8]);
-    vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohs32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrhq_s32 ((int16_t const *) pDataSrc);
-    int32x4_t vecIn2 = vldrhq_s32 ((int16_t const *) &pDataSrc[4]);
-    vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foods64( int64_t * pDataSrc, int64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
-    int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[2]);
-
-    vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1);
-    vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-/* { dg-final { scan-assembler-times "vstr\[a-z\]" 20 } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c
deleted file mode 100644
index a51d3a21167..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-mve_pred16_t __p;
-int
-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
-    uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[4], __p);
-    vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foowf32( float32_t * pDataSrc, float32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    float32x4_t vecIn1 = vldrwq_z_f32 ((float32_t const *) pDataSrc, __p);
-    float32x4_t vecIn2 = vldrwq_z_f32 ((float32_t const *) &pDataSrc[4], __p);
-    vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    uint16x8_t vecIn1 = vldrhq_z_u16 ((uint16_t const *) pDataSrc, __p);
-    uint16x8_t vecIn2 = vldrhq_z_u16 ((uint16_t const *) &pDataSrc[8], __p);
-    vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrhq_z_u32 ((uint16_t const *) pDataSrc, __p);
-    uint32x4_t vecIn2 = vldrhq_z_u32 ((uint16_t const *) &pDataSrc[4], __p);
-    vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohf16( float16_t * pDataSrc, float16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    float16x8_t vecIn1 = vldrhq_z_f16 ((float16_t const *) pDataSrc, __p);
-    float16x8_t vecIn2 = vldrhq_z_f16 ((float16_t const *) &pDataSrc[8], __p);
-    vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
-    uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[2], __p);
-
-    vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1, __p);
-    vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2, __p);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-int
-foows32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
-    int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[4], __p);
-    vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohs16( int16_t * pDataSrc, int16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    int16x8_t vecIn1 = vldrhq_z_s16 ((int16_t const *) pDataSrc, __p);
-    int16x8_t vecIn2 = vldrhq_z_s16 ((int16_t const *) &pDataSrc[8], __p);
-    vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohs32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrhq_z_s32 ((int16_t const *) pDataSrc, __p);
-    int32x4_t vecIn2 = vldrhq_z_s32 ((int16_t const *) &pDataSrc[4], __p);
-    vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foods64( int64_t * pDataSrc, int64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
-    int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[2], __p);
-
-    vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1, __p);
-    vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2, __p);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-/* { dg-final { scan-assembler-times "vstr\[a-z\]t" 20 } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
deleted file mode 100644
index 8348098f948..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vaddq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
deleted file mode 100644
index c34cc98385f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vaddq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
deleted file mode 100644
index 3bb01676947..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vaddq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
deleted file mode 100644
index 66dedc7d7e5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vaddq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
deleted file mode 100644
index 909ca936492..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpeqq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
deleted file mode 100644
index 8f993af20af..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpeqq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
deleted file mode 100644
index 223cffc17e5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpeqq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
deleted file mode 100644
index 81669bd7c60..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpeqq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
deleted file mode 100644
index 4a4e4b34fde..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpgeq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
deleted file mode 100644
index c406a63aae2..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpgeq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
deleted file mode 100644
index a65ed4421a8..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpgeq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
deleted file mode 100644
index 2e2fc0170eb..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpgeq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
deleted file mode 100644
index 08c91a72e05..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpgtq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
deleted file mode 100644
index 0b74482211d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpgtq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
deleted file mode 100644
index 3b2faeaf64f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpgtq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
deleted file mode 100644
index 16862e0209c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpgtq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
deleted file mode 100644
index 50e53bdac47..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpleq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
deleted file mode 100644
index b16da273a91..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpleq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
deleted file mode 100644
index 4a4b97312b0..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpleq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
deleted file mode 100644
index 8d8f1051933..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpleq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
deleted file mode 100644
index 62ab53fb2ef..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpltq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
deleted file mode 100644
index 55886fccff1..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpltq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
deleted file mode 100644
index cd95daea48c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpltq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
deleted file mode 100644
index db76687d53e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpltq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
deleted file mode 100644
index 30618e87101..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpneq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
deleted file mode 100644
index 4ecfda6d75c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpneq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
deleted file mode 100644
index 75a0090fcdc..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpneq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
deleted file mode 100644
index 11ae14cff56..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpneq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
deleted file mode 100644
index e47ae6d8e3b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
-{
-  return vfmaq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
deleted file mode 100644
index 78c39f0b2c9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
-{
-  return vfmaq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
deleted file mode 100644
index f7867f2c0c3..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
-{
-  return vfmaq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
deleted file mode 100644
index f0bc45bfed9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
-{
-  return vfmaq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
deleted file mode 100644
index 4750e108b6d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
-{
-  return vfmasq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
deleted file mode 100644
index 4a379711386..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
-{
-  return vfmasq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
deleted file mode 100644
index db824512b2b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
-{
-  return vfmasq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
deleted file mode 100644
index 12b1410c008..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
-{
-  return vfmasq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
deleted file mode 100644
index 7c2349d1ee4..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vmaxnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
deleted file mode 100644
index 0deef79487a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vmaxnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
deleted file mode 100644
index 56a7ac001f9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vmaxnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
deleted file mode 100644
index 36c10a90633..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vmaxnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
deleted file mode 100644
index f60641f5de0..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vmaxnmvq (23.35, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
deleted file mode 100644
index f8c9f44ac78..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vmaxnmvq (34.56, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
deleted file mode 100644
index 96820ecab91..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vmaxnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
deleted file mode 100644
index 826ee8f900a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vmaxnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
deleted file mode 100644
index 37d5136edca..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vminnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
deleted file mode 100644
index 78978d05054..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vminnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
deleted file mode 100644
index 7170b747a40..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vminnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
deleted file mode 100644
index 09559053852..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vminnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
deleted file mode 100644
index 132d1a123f8..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vminnmvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
deleted file mode 100644
index 74909075b09..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vminnmvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
deleted file mode 100644
index c88c3b74a50..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vminnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
deleted file mode 100644
index e4db972fc70..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vminnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
deleted file mode 100644
index c8222c5c7b9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vmulq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
deleted file mode 100644
index 2fae3a7f8fa..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vmulq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
deleted file mode 100644
index cef311d981d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vmulq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
deleted file mode 100644
index d6d4b9a0a7c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vmulq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
deleted file mode 100644
index ea4cab03490..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vmulq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
deleted file mode 100644
index a7a54c7c92c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vmulq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
deleted file mode 100644
index 608dd30788e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo (float16_t a, float16x8_t b)
-{
-  return vsetq_lane (23.26, b, 0);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
deleted file mode 100644
index c5f5db7f28d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo (float32_t a, float32x4_t b)
-{
-    return vsetq_lane (23.34, b, 0);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
deleted file mode 100644
index f3e19613e7e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vsubq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
deleted file mode 100644
index 4b5cd90c9ed..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vsubq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
deleted file mode 100644
index f8832546f54..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vsubq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
deleted file mode 100644
index 88d9675540d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vsubq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
deleted file mode 100644
index b3a67bb43eb..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-    return vsubq_x_n_f16 (a, 23.23, p);
-}
-
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
deleted file mode 100644
index dcb2425397b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-    return vsubq_x_n_f32 (a, 23.23, p);
-}
-
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit 8ed701b52847e49d63634f03ec8800ff92b76dea
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 27 16:54:16 2023

    arm testsuite: XFAIL or relax registers in some tests [PR109697]
    
    Hi all,
    
    This is a simple testsuite tidy-up patch, addressing to types of errors:
    
    * The vcmp vector-scalar tests failing due to the compiler's preference
    of vector-vector comparisons, over vector-scalar comparisons. This is
    due to the lack of cost model for MVE and the compiler not knowing that
    the RTL vec_duplicate is free in those instructions. For now, we simply
    XFAIL these checks.
    * The tests for pr108177 had strict usage of q0 and r0 registers,
    meaning that they would FAIL with -mfloat-abi=softf. The register checks
    have now been relaxed. A couple of these run-tests also had incosistent
    use of integer MVE with floating point vectors, so I've now changed
    these to use FP MVE.
    
    gcc/testsuite/ChangeLog:
            PR target/109697
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: XFAIL check.
            * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: XFAIL check.
            * gcc.target/arm/mve/pr108177-1.c: Relax registers.
            * gcc.target/arm/mve/pr108177-10.c: Relax registers.
            * gcc.target/arm/mve/pr108177-11.c: Relax registers.
            * gcc.target/arm/mve/pr108177-12.c: Relax registers.
            * gcc.target/arm/mve/pr108177-13.c: Relax registers.
            * gcc.target/arm/mve/pr108177-13-run.c: use mve_fp
            * gcc.target/arm/mve/pr108177-14.c: Relax registers.
            * gcc.target/arm/mve/pr108177-14-run.c: use mve_fp
            * gcc.target/arm/mve/pr108177-2.c: Relax registers.
            * gcc.target/arm/mve/pr108177-3.c: Relax registers.
            * gcc.target/arm/mve/pr108177-4.c: Relax registers.
            * gcc.target/arm/mve/pr108177-5.c: Relax registers.
            * gcc.target/arm/mve/pr108177-6.c: Relax registers.
            * gcc.target/arm/mve/pr108177-7.c: Relax registers.
            * gcc.target/arm/mve/pr108177-8.c: Relax registers.
            * gcc.target/arm/mve/pr108177-9.c: Relax registers.

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
index dc63c527743..9f8111438a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
index 8c5d185ca22..799d3bcdab1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
index 2296f3e1655..16c3617c104 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
index 1d870428c55..2f84d751c53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
index 8b8610b0617..6cfe7338fce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
index 409c9de58ba..362e830c908 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
index c3b1736bfa1..583beb97849 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
index 3728c738b54..db7f1877d73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
index 4e9a346ab14..978bd7d4b52 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
index 2cf1d1ab0b6..66b6d8b0056 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
index 89d8e2b9109..9c5f1f2f5c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
index 482ac094cf3..2723aa7f98f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
index 085b8277736..5712db2ceef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
index a62a73ff24c..f7a25af8574 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
index f05c9d24643..8cd28fb1681 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
index 4f6276484ba..1d1f4bf0e58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
index e71dcb8f174..bf77a808064 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
index c6fdb08d8ae..f9f091cd9b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
index 4f1ac3c0977..d22ea1aca30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
index e36d8a95a85..83beca964d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
index 7262503eee6..abe1abfed2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
index 71d878dff9f..ca55fe2f76c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
index 3f997e8e487..77bac757d68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
index 9917a95ffb7..352afa798d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
 }
 
 /*
-**foo2:
+**foo2: { xfail *-*-* }
 **	...
 **	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
 **	...
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
index 2d42062bc8e..8383b4d9e3a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrbt.8	q0, \[r0\]
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrbt.8	q0, \[r0\]
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
index 4db594f588f..7b1cd3711d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrht.32	q0, \[r0\]
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrht.32	q0, \[r0\]
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
index 329fcb33eeb..e6ae8524052 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrwt.32	q0, \[r0\]
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrwt.32	q0, \[r0\]
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
index 3f7c5b2a4c1..e352508e07e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrwt.32	q0, \[r0\]
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrwt.32	q0, \[r0\]
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
index 2e731ee3824..34a5e7d35e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
@@ -1,6 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
 
 #include "pr108177-13.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
index 2f82228d8f6..13afa92771d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrht.16	q0, \[r0\]
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrht.16	q0, \[r0\]
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
index 3cebcf5bbcd..a2dc3338dd3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
@@ -1,6 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
 
 #include "pr108177-14.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
index ba6196b7994..a093cd4b708 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrwt.32	q0, \[r0\]
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrwt.32	q0, \[r0\]
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
index 52c8d87ccc8..da4181ff0b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrbt.8	q0, \[r0\]
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrbt.8	q0, \[r0\]
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
index ac89e7ea883..9604fd100e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrbt.16	q0, \[r0\]
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrbt.16	q0, \[r0\]
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
index dc4f7ddab07..07ba37b466c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrbt.16	q0, \[r0\]
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrbt.16	q0, \[r0\]
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
index d1dfd328d66..72c1dd5a4d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrbt.32	q0, \[r0\]
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrbt.32	q0, \[r0\]
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
index fa70dde9eeb..3fedc9b98c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrbt.32	q0, \[r0\]
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrbt.32	q0, \[r0\]
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
index 73cd8605171..c3b440c3b6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrht.16	q0, \[r0\]
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrht.16	q0, \[r0\]
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
index 187c2b3f4ce..5c450b81d1c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrht.16	q0, \[r0\]
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrht.16	q0, \[r0\]
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
index caecd18a881..b5084efcc00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
@@ -7,9 +7,9 @@
 /*
 ** test:
 **...
-**	vstrht.32	q0, \[r0\]
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
-**	vstrht.32	q0, \[r0\]
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
 **...
 */
 

commit 16df8b8884291171cfdd886f620be496e70e7ee3
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Thu Apr 27 16:55:24 2023

    arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes
    
    These newly updated tests were rewritten by Andrea. Some of them
    needed further manual fixing as follows:
    
    * The #shift immediate value not in the check-function-bodies as expected
    * The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
      this case the test rewritten from the ACLE had the lsr+and pattern,
      but the compiler was able to optimise to ubfx. Hence I've changed the
      test to now match on ubfx.
    * Added a separate test to check shift on constants being optimised to
      movs.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
            * gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
            * gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value.
            * gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value.
            * gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
            * gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
            * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
            * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
            * gcc.target/arm/mve/mve_const_shifts.c: New test.

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 94e3f42fd33..734375d58c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	srshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	srshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 int32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index 65f28ccbfde..a91943c38a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	srshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	srshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 int64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index b23c9d97ba6..462531cad54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	uqshl	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	uqshl	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint32_t
@@ -21,18 +21,6 @@ foo (uint32_t value)
   return uqshl (value, 1);
 }
 
-/*
-**foo1:
-**	...
-**	uqshl	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
-**	...
-*/
-uint32_t
-foo1 ()
-{
-  return uqshl (1, 1);
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 6a3d08eea75..6fa97a561e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint64_t
@@ -21,18 +21,6 @@ foo (uint64_t value)
   return uqshll (value, 1);
 }
 
-/*
-**foo1:
-**	...
-**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
-**	...
-*/
-uint64_t
-foo1 ()
-{
-  return uqshll (1, 1);
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index 23afcb8da4c..ff97bf5c473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	urshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
 /*
 **foo1:
 **	...
-**	urshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index 8014371f47f..ff6a69d300f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint64_t
@@ -24,7 +24,7 @@ foo (uint64_t value)
 /*
 **foo1:
 **	...
-**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index b262bf94d39..a6a059a19e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index d349caed36a..942111339f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index 5166993a355..3b68bb6ac33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index 080bd61d238..82228491043 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 5c2702a3142..da29bb765dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -30,9 +30,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -63,9 +61,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index a3c01710627..be490aaaae7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -30,9 +30,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -63,9 +61,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index efe4f8c778b..d72190d53b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index af778be6917..dbc1ebf3c46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 66a5c4c9da3..dcbaef1a571 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index 9306f152cde..08f67f665c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 0b5040f0b2a..803246c3235 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df211a64daa..22d2b4355bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index ed9e48ce7bb..0c62778d482 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -30,9 +30,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -63,9 +61,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 442a52ed5f3..2532a23fac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -30,9 +30,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -63,9 +61,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index fa88ec5dcd8..5deff8c4018 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index c3ae208ff82..bd0ea2df127 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
new file mode 100644
index 00000000000..b17f9f36057
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
@@ -0,0 +1,41 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo11:
+**     ...
+**     movs	r0, #2
+**     ...
+*/
+uint32_t
+foo11 ()
+{
+  return uqshl (1, 1);
+}
+
+/*
+**foo12:
+**     ...
+**	movs	r0, #2
+**	movs	r1, #0
+**     ...
+*/
+uint64_t
+foo12 ()
+{
+  return uqshll (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */

commit 942374058b7d3f077a3454318c50151468949041
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Fri Mar 3 19:59:17 2023

    [arm] complete vmsr/vmrs blank and case adjustments
    
    Back in September last year, some of the vmsr and vmrs patterns had an
    extraneous blank removed, and the case of register names lowered, but
    another instance remained, and so did a testcase.
    
    for  gcc/ChangeLog
    
            * config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab
            after vmsr and vmrs, and lower the case of P0.
    
    for  gcc/testsuite/ChangeLog
    
            * gcc.target/arm/acle/cde-mve-full-assembly.c: Drop blank
            after tab after vmsr, and lower the case of P0.

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 932e4b7447e..7a430ef8d36 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -312,9 +312,9 @@
     case 12: case 13:
       return output_move_vfp (operands);
     case 14:
-      return \"vmsr\\t P0, %1\";
+      return \"vmsr\\tp0, %1\";
     case 15:
-      return \"vmrs\\t %0, P0\";
+      return \"vmrs\\t%0, p0\";
     case 16:
       return \"mcr\\tp10, 7, %1, cr1, cr0, 0\\t @SET_FPSCR\";
     case 17:
diff --git a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
index 501cc84da10..e3e7f7ef3e5 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
@@ -567,80 +567,80 @@
    contain back references).  */
 /*
 ** test_cde_vcx1q_mfloat16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mfloat32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
@@ -649,80 +649,80 @@
 
 /*
 ** test_cde_vcx1qa_mfloat16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mfloat32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
@@ -731,8 +731,8 @@
 
 /*
 ** test_cde_vcx2q_mfloat16x8_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -740,8 +740,8 @@
 */
 /*
 ** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -749,8 +749,8 @@
 */
 /*
 ** test_cde_vcx2q_mfloat32x4_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -758,8 +758,8 @@
 */
 /*
 ** test_cde_vcx2q_mint64x2_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -767,8 +767,8 @@
 */
 /*
 ** test_cde_vcx2q_mint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -776,8 +776,8 @@
 */
 /*
 ** test_cde_vcx2q_muint16x8_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -785,8 +785,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tint64x2_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -794,8 +794,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -803,8 +803,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -812,8 +812,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -823,8 +823,8 @@
 
 /*
 ** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -832,8 +832,8 @@
 */
 /*
 ** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -841,8 +841,8 @@
 */
 /*
 ** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -850,8 +850,8 @@
 */
 /*
 ** test_cde_vcx2qa_mint64x2_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -859,8 +859,8 @@
 */
 /*
 ** test_cde_vcx2qa_mint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -868,8 +868,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint16x8_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -877,8 +877,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tint64x2_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -886,8 +886,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -895,8 +895,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -904,8 +904,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -915,8 +915,8 @@
 
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -924,8 +924,8 @@
 */
 /*
 ** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -933,8 +933,8 @@
 */
 /*
 ** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -942,8 +942,8 @@
 */
 /*
 ** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -951,8 +951,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -960,8 +960,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -969,8 +969,8 @@
 */
 /*
 ** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -978,8 +978,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -987,8 +987,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -996,8 +996,8 @@
 */
 /*
 ** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1005,8 +1005,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1014,8 +1014,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1023,8 +1023,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1034,8 +1034,8 @@
 
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1043,8 +1043,8 @@
 */
 /*
 ** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1052,8 +1052,8 @@
 */
 /*
 ** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1061,8 +1061,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1070,8 +1070,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1079,8 +1079,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1088,8 +1088,8 @@
 */
 /*
 ** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1097,8 +1097,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1106,8 +1106,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1115,8 +1115,8 @@
 */
 /*
 ** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1124,8 +1124,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1133,8 +1133,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1142,8 +1142,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?

commit 4ca8a87a9a0de933d037b9729a5a72c209261d44
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 19 02:21:45 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3f096df5808..7684ea17fc5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,508 @@
+2023-05-18  Alexandre Oliva  <oliva@adacore.com>
+
+	* config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab
+	after vmsr and vmrs, and lower the case of P0.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types.
+	(__ARM_mve_coerce1): Remove.
+	(__ARM_mve_coerce2): Remove.
+	(__ARM_mve_coerce3): Remove.
+	(__ARM_mve_coerce_i_scalar): New.
+	(__ARM_mve_coerce_s8_ptr): New.
+	(__ARM_mve_coerce_u8_ptr): New.
+	(__ARM_mve_coerce_s16_ptr): New.
+	(__ARM_mve_coerce_u16_ptr): New.
+	(__ARM_mve_coerce_s32_ptr): New.
+	(__ARM_mve_coerce_u32_ptr): New.
+	(__ARM_mve_coerce_s64_ptr): New.
+	(__ARM_mve_coerce_u64_ptr): New.
+	(__ARM_mve_coerce_f_scalar): New.
+	(__ARM_mve_coerce_f16_ptr): New.
+	(__ARM_mve_coerce_f32_ptr): New.
+	(__arm_vst4q): Change _coerce_ overloads.
+	(__arm_vbicq): Change _coerce_ overloads.
+	(__arm_vmulq): Change _coerce_ overloads.
+	(__arm_vcmpeqq): Change _coerce_ overloads.
+	(__arm_vcmpneq): Change _coerce_ overloads.
+	(__arm_vmaxnmavq): Change _coerce_ overloads.
+	(__arm_vmaxnmvq): Change _coerce_ overloads.
+	(__arm_vminnmavq): Change _coerce_ overloads.
+	(__arm_vsubq): Change _coerce_ overloads.
+	(__arm_vminnmvq): Change _coerce_ overloads.
+	(__arm_vrshlq): Change _coerce_ overloads.
+	(__arm_vqsubq): Change _coerce_ overloads.
+	(__arm_vqdmulltq): Change _coerce_ overloads.
+	(__arm_vqdmullbq): Change _coerce_ overloads.
+	(__arm_vqdmulhq): Change _coerce_ overloads.
+	(__arm_vqaddq): Change _coerce_ overloads.
+	(__arm_vhaddq): Change _coerce_ overloads.
+	(__arm_vhsubq): Change _coerce_ overloads.
+	(__arm_vqdmlashq): Change _coerce_ overloads.
+	(__arm_vqrdmlahq): Change _coerce_ overloads.
+	(__arm_vmlasq): Change _coerce_ overloads.
+	(__arm_vqdmlahq): Change _coerce_ overloads.
+	(__arm_vmaxnmavq_p): Change _coerce_ overloads.
+	(__arm_vmaxnmvq_p): Change _coerce_ overloads.
+	(__arm_vminnmavq_p): Change _coerce_ overloads.
+	(__arm_vminnmvq_p): Change _coerce_ overloads.
+	(__arm_vfmasq_m): Change _coerce_ overloads.
+	(__arm_vld1q): Change _coerce_ overloads.
+	(__arm_vld1q_z): Change _coerce_ overloads.
+	(__arm_vld2q): Change _coerce_ overloads.
+	(__arm_vld4q): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_offset): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_offset): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads.
+	(__arm_vst1q_p): Change _coerce_ overloads.
+	(__arm_vst2q): Change _coerce_ overloads.
+	(__arm_vst1q): Change _coerce_ overloads.
+	(__arm_vstrhq): Change _coerce_ overloads.
+	(__arm_vstrhq_p): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads.
+	(__arm_vstrwq_p): Change _coerce_ overloads.
+	(__arm_vstrwq): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads.
+	(__arm_vsetq_lane): Change _coerce_ overloads.
+	(__arm_vcmpneq_m): Change _coerce_ overloads.
+	(__arm_vldrbq_gather_offset): Change _coerce_ overloads.
+	(__arm_vdwdupq_x_u8): Change _coerce_ overloads.
+	(__arm_vdwdupq_x_u16): Change _coerce_ overloads.
+	(__arm_vdwdupq_x_u32): Change _coerce_ overloads.
+	(__arm_viwdupq_x_u8): Change _coerce_ overloads.
+	(__arm_viwdupq_x_u16): Change _coerce_ overloads.
+	(__arm_viwdupq_x_u32): Change _coerce_ overloads.
+	(__arm_vidupq_x_u8): Change _coerce_ overloads.
+	(__arm_vddupq_x_u8): Change _coerce_ overloads.
+	(__arm_vidupq_x_u16): Change _coerce_ overloads.
+	(__arm_vddupq_x_u16): Change _coerce_ overloads.
+	(__arm_vidupq_x_u32): Change _coerce_ overloads.
+	(__arm_vddupq_x_u32): Change _coerce_ overloads.
+	(__arm_vhaddq_x): Change _coerce_ overloads.
+	(__arm_vhsubq_x): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_offset): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads.
+	(__arm_vldrbq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vqrdmlahq_m): Change _coerce_ overloads.
+	(__arm_vqrdmlashq_m): Change _coerce_ overloads.
+	(__arm_vqdmlashq_m): Change _coerce_ overloads.
+	(__arm_vmlaldavaxq_p): Change _coerce_ overloads.
+	(__arm_vmlasq_m): Change _coerce_ overloads.
+	(__arm_vqdmulhq_m): Change _coerce_ overloads.
+	(__arm_vqdmulltq_m): Change _coerce_ overloads.
+	(__arm_vidupq_u16): Change _coerce_ overloads.
+	(__arm_vidupq_u32): Change _coerce_ overloads.
+	(__arm_vidupq_u8): Change _coerce_ overloads.
+	(__arm_vddupq_u16): Change _coerce_ overloads.
+	(__arm_vddupq_u32): Change _coerce_ overloads.
+	(__arm_vddupq_u8): Change _coerce_ overloads.
+	(__arm_viwdupq_m): Change _coerce_ overloads.
+	(__arm_viwdupq_u16): Change _coerce_ overloads.
+	(__arm_viwdupq_u32): Change _coerce_ overloads.
+	(__arm_viwdupq_u8): Change _coerce_ overloads.
+	(__arm_vdwdupq_m): Change _coerce_ overloads.
+	(__arm_vdwdupq_u16): Change _coerce_ overloads.
+	(__arm_vdwdupq_u32): Change _coerce_ overloads.
+	(__arm_vdwdupq_u8): Change _coerce_ overloads.
+	(__arm_vaddlvaq): Change _coerce_ overloads.
+	(__arm_vaddlvaq_p): Change _coerce_ overloads.
+	(__arm_vaddvaq): Change _coerce_ overloads.
+	(__arm_vaddvaq_p): Change _coerce_ overloads.
+	(__arm_vcmphiq_m): Change _coerce_ overloads.
+	(__arm_vmladavaq_p): Change _coerce_ overloads.
+	(__arm_vmladavaxq): Change _coerce_ overloads.
+	(__arm_vmlaldavaxq): Change _coerce_ overloads.
+	(__arm_vstrbq): Change _coerce_ overloads.
+	(__arm_vstrbq_p): Change _coerce_ overloads.
+	(__arm_vrmlaldavhaq_p): Change _coerce_ overloads.
+	(__arm_vstrbq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vbicq): Change coerce on
+	scalar constant.
+	(__arm_vmvnq_m): Likewise.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vorrq): Add _n variant.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
+	(__arm_vadcq_u32): Likewise.
+	(__arm_vadcq_m_s32): Likewise.
+	(__arm_vadcq_m_u32): Likewise.
+	(__arm_vsbcq_s32): Likewise.
+	(__arm_vsbcq_u32): Likewise.
+	(__arm_vsbcq_m_s32): Likewise.
+	(__arm_vsbcq_m_u32): Likewise.
+	* config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrev64q_f<mode>)
+	(mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf)
+	(mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_<supf><mode>)
+	(mve_vrev64q_<supf><mode>, mve_vcvtq_from_f_<supf><mode>)
+	(mve_vmovltq_<supf><mode>, mve_vmovlbq_<supf><mode>)
+	(mve_vcvtpq_<supf><mode>, mve_vcvtnq_<supf><mode>)
+	(mve_vcvtmq_<supf><mode>, mve_vcvtaq_<supf><mode>)
+	(mve_vmvnq_n_<supf><mode>, mve_vrev16q_<supf>v16qi)
+	(mve_vctp<mode1>qhi, mve_vbrsrq_n_f<mode>)
+	(mve_vbrsrq_n_<supf><mode>, mve_vandq_f<mode>, mve_vbicq_f<mode>)
+	(mve_vbicq_n_<supf><mode>, mve_vctp<mode1>q_mhi)
+	(mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf)
+	(mve_veorq_f<mode>, mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
+	(mve_vmlsldavxq_s<mode>, mve_vornq_f<mode>, mve_vorrq_f<mode>)
+	(mve_vrmlaldavhxq_sv4si, mve_vbicq_m_n_<supf><mode>)
+	(mve_vcvtq_m_to_f_<supf><mode>, mve_vshlcq_<supf><mode>)
+	(mve_vmvnq_m_<supf><mode>, mve_vpselq_<supf><mode>)
+	(mve_vcvtbq_m_f16_f32v8hf, mve_vcvtbq_m_f32_f16v4sf)
+	(mve_vcvttq_m_f16_f32v8hf, mve_vcvttq_m_f32_f16v4sf)
+	(mve_vmlaldavq_p_<supf><mode>, mve_vmlsldavaq_s<mode>)
+	(mve_vmlsldavaxq_s<mode>, mve_vmlsldavq_p_s<mode>)
+	(mve_vmlsldavxq_p_s<mode>, mve_vmvnq_m_n_<supf><mode>)
+	(mve_vorrq_m_n_<supf><mode>, mve_vpselq_f<mode>)
+	(mve_vrev32q_m_fv8hf, mve_vrev32q_m_<supf><mode>)
+	(mve_vrev64q_m_f<mode>, mve_vrmlaldavhaxq_sv4si)
+	(mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhaxq_sv4si)
+	(mve_vrmlsldavhq_p_sv4si, mve_vrmlsldavhxq_p_sv4si)
+	(mve_vrev16q_m_<supf>v16qi, mve_vrmlaldavhq_p_<supf>v4si)
+	(mve_vrmlsldavhaq_sv4si, mve_vandq_m_<supf><mode>)
+	(mve_vbicq_m_<supf><mode>, mve_veorq_m_<supf><mode>)
+	(mve_vornq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
+	(mve_vandq_m_f<mode>, mve_vbicq_m_f<mode>, mve_veorq_m_f<mode>)
+	(mve_vornq_m_f<mode>, mve_vorrq_m_f<mode>)
+	(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn)
+	(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn)
+	(mve_vstrdq_scatter_base_wb_p_<supf>v2di) : Fix spacing and
+	capitalization in the emitted asm.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/constraints.md (mve_vldrd_immediate): Move it to
+	predicates.md.
+	(Ri): Move constraint definition from predicates.md.
+	(Rl): Define new constraint.
+	* config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Add
+	missing constraint.
+	(mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
+	for op 1, use mve_vstrw_immediate predicate and Rl constraint for
+	op 2. Fix asm output spacing.
+	(mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing constraint.
+	* config/arm/predicates.md (Ri) Move constraint to constraints.md
+	(mve_vldrd_immediate): Move it from
+	constraints.md.
+	(mve_vstrw_immediate): New predicate.
+
+2023-05-18  Murray Steele  <murray.steele@arm.com>
+
+	Backported from master:
+	2023-01-18  Murray Steele  <murray.steele@arm.com>
+
+	PR target/108442
+	* config/arm/arm_mve.h (__arm_vst1q_p_u8): Use prefixed intrinsic
+	function.
+	(__arm_vst1q_p_s8): Likewise.
+	(__arm_vld1q_z_u8): Likewise.
+	(__arm_vld1q_z_s8): Likewise.
+	(__arm_vst1q_p_u16): Likewise.
+	(__arm_vst1q_p_s16): Likewise.
+	(__arm_vld1q_z_u16): Likewise.
+	(__arm_vld1q_z_s16): Likewise.
+	(__arm_vst1q_p_u32): Likewise.
+	(__arm_vst1q_p_s32): Likewise.
+	(__arm_vld1q_z_u32): Likewise.
+	(__arm_vld1q_z_s32): Likewise.
+	(__arm_vld1q_z_f16): Likewise.
+	(__arm_vst1q_p_f16): Likewise.
+	(__arm_vld1q_z_f32): Likewise.
+	(__arm_vst1q_p_f32): Likewise.
+
+2023-05-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backported from master:
+	2023-01-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	PR target/108177
+	* config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
+	mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
+	as input operand.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-04-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/mve.md (mve_vcvtq_n_to_f_<supf><mode>): Swap operands.
+	(mve_vcreateq_f<mode>): Swap operands.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	PR target/107515
+	* config/arm/arm_mve.h (__ARM_mve_coerce2): Split types.
+	(__ARM_mve_coerce3): Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vqnegq_s<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vqabsq_s<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vnegq_f<mode>, mve_vnegq_s<mode>):
+	Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (@mve_vclzq_s<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vclsq_s<mode>): Fix spacing.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2023-02-03  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* config/arm/mve.md (mve_vabavq_p_<supf><mode>): Add length
+	attribute.
+	(mve_vqshluq_m_n_s<mode>): Likewise.
+	(mve_vshlq_m_<supf><mode>): Likewise.
+	(mve_vsriq_m_n_<supf><mode>): Likewise.
+	(mve_vsubq_m_<supf><mode>): Likewise.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-10-03  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* config/arm/mve.md (mve_vrev64q_m_<supf><mode>): Add early
+	clobber.
+	(mve_vrev64q_m_f<mode>): Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si,
+	mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
+	(mve_vmlaldavaxq_s<mode>, mve_vmlaldavaxq_p_<supf><mode>): Fix
+	spacing vs tabs.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vaddlvq_p_<supf>v4si)
+	(mve_vaddq_n_<supf><mode>, mve_vaddvaq_<supf><mode>)
+	(mve_vaddlvaq_<supf>v4si, mve_vaddq_n_f<mode>)
+	(mve_vaddlvaq_p_<supf>v4si, mve_vaddq<mode>, mve_vaddq_f<mode>):
+	Fix spacing.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads.
+	(__arm_vsubq_x Integer): New.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/107515
+	* config/arm/arm_mve.h (__ARM_mve_typeid): Add float types.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	* config/arm/arm_mve.h (__arm_vaddq): Fix Overloading.
+	(__arm_vmulq): Likewise.
+	(__arm_vcmpeqq): Likewise.
+	(__arm_vcmpneq): Likewise.
+	(__arm_vmaxnmavq): Likewise.
+	(__arm_vmaxnmvq): Likewise.
+	(__arm_vminnmavq): Likewise.
+	(__arm_vsubq): Likewise.
+	(__arm_vminnmvq): Likewise.
+	(__arm_vrshlq): Likewise.
+	(__arm_vqsubq): Likewise.
+	(__arm_vqdmulltq): Likewise.
+	(__arm_vqdmullbq): Likewise.
+	(__arm_vqdmulhq): Likewise.
+	(__arm_vqaddq): Likewise.
+	(__arm_vhaddq): Likewise.
+	(__arm_vhsubq): Likewise.
+	(__arm_vqdmlashq): Likewise.
+	(__arm_vqrdmlahq): Likewise.
+	(__arm_vmlasq): Likewise.
+	(__arm_vqdmlahq): Likewise.
+	(__arm_vmaxnmavq_p): Likewise.
+	(__arm_vmaxnmvq_p): Likewise.
+	(__arm_vminnmavq_p): Likewise.
+	(__arm_vminnmvq_p): Likewise.
+	(__arm_vfmasq_m): Likewise.
+	(__arm_vsetq_lane): Likewise.
+	(__arm_vcmpneq_m): Likewise.
+	(__arm_vhaddq_x): Likewise.
+	(__arm_vhsubq_x): Likewise.
+	(__arm_vqrdmlashq_m): Likewise.
+	(__arm_vqdmlashq_m): Likewise.
+	(__arm_vmlaldavaxq_p): Likewise.
+	(__arm_vmlasq_m): Likewise.
+	(__arm_vqdmulhq_m): Likewise.
+	(__arm_vqdmulltq_m): Likewise.
+	(__arm_viwdupq_m): Likewise.
+	(__arm_viwdupq_u16): Likewise.
+	(__arm_viwdupq_u32): Likewise.
+	(__arm_viwdupq_u8): Likewise.
+	(__arm_vdwdupq_m): Likewise.
+	(__arm_vdwdupq_u16): Likewise.
+	(__arm_vdwdupq_u32): Likewise.
+	(__arm_vdwdupq_u8): Likewise.
+	(__arm_vaddlvaq): Likewise.
+	(__arm_vaddlvaq_p): Likewise.
+	(__arm_vaddvaq): Likewise.
+	(__arm_vaddvaq_p): Likewise.
+	(__arm_vcmphiq_m): Likewise.
+	(__arm_vmladavaq_p): Likewise.
+	(__arm_vmladavaxq): Likewise.
+	(__arm_vmlaldavaxq): Likewise.
+	(__arm_vrmlaldavhaq_p): Likewise.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	* config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types.
+	(__arm_vaddq_m_n_s32): Likewise.
+	(__arm_vaddq_m_n_s16): Likewise.
+	(__arm_vaddq_m_n_u8): Likewise.
+	(__arm_vaddq_m_n_u32): Likewise.
+	(__arm_vaddq_m_n_u16): Likewise.
+	(__arm_vaddq_m): Fix Overloading.
+	(__ARM_mve_coerce3): New.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vabsq_f<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>): Fix
+	spacing.
+	* config/arm/arm_mve.h (__arm_vcmpgtq_m, __arm_vcmpleq_m)
+	(__arm_vcmpltq_m, __arm_vcmpneq_m): Add missing defines.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vdupq_n_f<mode>)
+	(mve_vdupq_n_<supf><mode>, mve_vdupq_m_n_<supf><mode>)
+	(mve_vdupq_m_n_f<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vdwdupq_m_wb_u<mode>_insn): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vddupq_u<mode>_insn): Fix 'vddup.u'
+	spacing.
+	(mve_vddupq_m_wb_u<mode>_insn): Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix
+	'vmsr' spacing and reg capitalization.
+
 2023-05-15  liuhongt  <hongtao.liu@intel.com>
 
 	* config/i386/cygwin.h (ENDFILE_SPEC): Link crtfastmath.o
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 460c1ea9af3..69b7e9e68cc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230518
+20230519
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7f65d308ec8..c6c91cbfd3b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,4037 @@
+2023-05-18  Alexandre Oliva  <oliva@adacore.com>
+
+	* gcc.target/arm/acle/cde-mve-full-assembly.c: Drop blank
+	after tab after vmsr, and lower the case of P0.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/mve_const_shifts.c: New test.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/109697
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/pr108177-1.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-10.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-11.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-12.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-13.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-13-run.c: use mve_fp
+	* gcc.target/arm/mve/pr108177-14.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-14-run.c: use mve_fp
+	* gcc.target/arm/mve/pr108177-2.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-3.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-4.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-5.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-6.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-7.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-8.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-9.c: Relax registers.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Add testcases.
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Add testcases.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/asrl.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/lsll.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqshl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqshll.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/srshr.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/srshrl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqshl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqshll.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/urshr.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/urshrl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp16q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-04-06  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Remove unused variables.
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Remove unused variables.
+
+2023-05-18  Murray Steele  <murray.steele@arm.com>
+
+	Backported from master:
+	2023-01-18  Murray Steele  <murray.steele@arm.com>
+
+	* gcc.target/arm/mve/general/preserve_user_namespace_1.c: New test.
+
+2023-05-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backported from master:
+	2023-01-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	* gcc.target/arm/mve/pr108177-1-run.c: New test.
+	* gcc.target/arm/mve/pr108177-1.c: New test.
+	* gcc.target/arm/mve/pr108177-10-run.c: New test.
+	* gcc.target/arm/mve/pr108177-10.c: New test.
+	* gcc.target/arm/mve/pr108177-11-run.c: New test.
+	* gcc.target/arm/mve/pr108177-11.c: New test.
+	* gcc.target/arm/mve/pr108177-12-run.c: New test.
+	* gcc.target/arm/mve/pr108177-12.c: New test.
+	* gcc.target/arm/mve/pr108177-13-run.c: New test.
+	* gcc.target/arm/mve/pr108177-13.c: New test.
+	* gcc.target/arm/mve/pr108177-14-run.c: New test.
+	* gcc.target/arm/mve/pr108177-14.c: New test.
+	* gcc.target/arm/mve/pr108177-2-run.c: New test.
+	* gcc.target/arm/mve/pr108177-2.c: New test.
+	* gcc.target/arm/mve/pr108177-3-run.c: New test.
+	* gcc.target/arm/mve/pr108177-3.c: New test.
+	* gcc.target/arm/mve/pr108177-4-run.c: New test.
+	* gcc.target/arm/mve/pr108177-4.c: New test.
+	* gcc.target/arm/mve/pr108177-5-run.c: New test.
+	* gcc.target/arm/mve/pr108177-5.c: New test.
+	* gcc.target/arm/mve/pr108177-6-run.c: New test.
+	* gcc.target/arm/mve/pr108177-6.c: New test.
+	* gcc.target/arm/mve/pr108177-7-run.c: New test.
+	* gcc.target/arm/mve/pr108177-7.c: New test.
+	* gcc.target/arm/mve/pr108177-8-run.c: New test.
+	* gcc.target/arm/mve/pr108177-8.c: New test.
+	* gcc.target/arm/mve/pr108177-9-run.c: New test.
+	* gcc.target/arm/mve/pr108177-9.c: New test.
+	* gcc.target/arm/mve/pr108177-main.x: New test include.
+	* gcc.target/arm/mve/pr108177.x: New test include.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-04-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Tighten test.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	PR target/107515
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: New test.
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: New test.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Add missing extern
+	"C".
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vld2q_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vld2q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vnegq_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise.
+	* gcc.target/arm/simd/mve-vneg.c: Update test.
+	* gcc.target/arm/simd/mve-vshr.c: Likewise
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise.
+	* gcc.target/arm/simd/mve-vclz.c: Update test.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks. Use extern
+	"C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-12-08  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Extern functions
+	as "C".
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-09-30  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* gcc.target/arm/mve/mve_load_memory_modes.c: Update expected
+	registers.
+	* gcc.target/arm/mve/mve_store_memory_modes.c: Likewise.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-10-03  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c: New test.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-12-01  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* gcc.target/arm/simd/mve-compare-1.c: Update.
+	* gcc.target/arm/simd/mve-compare-scalar-1.c: Update.
+	* gcc.target/arm/simd/mve-vabs.c: Update.
+	* gcc.target/arm/simd/mve-vadd-1.c: Update.
+	* gcc.target/arm/simd/mve-vadd-scalar-1.c: Update.
+	* gcc.target/arm/simd/mve-vcmp.c: Update.
+	* gcc.target/arm/simd/pr101325.c: Update.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_u8.c:
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c:
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c : Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c : Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
+	Update test.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c:
+	Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c:
+	Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
+
 2023-05-17  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:

commit a4d13e54822dddda4a53137c9f5e23770a798a0b
Author: Patrick Palka <ppalka@redhat.com>
Date:   Mon May 15 18:01:07 2023

    c++: add feature-test macro for auto(x)
    
    This adds the feature-test macro for PR0849R8, as per
    https://github.com/cplusplus/CWG/issues/281.
    
    gcc/c-family/ChangeLog:
    
            * c-cppbuiltin.cc (c_cpp_builtins): Predefine __cpp_auto_cast
            for C++23.
    
    gcc/testsuite/ChangeLog:
    
            * g++.dg/cpp23/feat-cxx2b.C: Test __cpp_auto_cast.
    
    (cherry picked from commit 32b81d897629b6c3bd9e2780831a1c45b38b5ac3)

diff --git a/gcc/c-family/c-cppbuiltin.cc b/gcc/c-family/c-cppbuiltin.cc
index 4672ae8486a..c1b86c1fac0 100644
--- a/gcc/c-family/c-cppbuiltin.cc
+++ b/gcc/c-family/c-cppbuiltin.cc
@@ -1080,6 +1080,7 @@ c_cpp_builtins (cpp_reader *pfile)
 	  cpp_define (pfile, "__cpp_if_consteval=202106L");
 	  cpp_define (pfile, "__cpp_constexpr=202110L");
 	  cpp_define (pfile, "__cpp_multidimensional_subscript=202110L");
+	  cpp_define (pfile, "__cpp_auto_cast=202110L");
 	}
       if (flag_concepts)
         {
diff --git a/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C b/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C
index c1f91e78e66..d8a1acd17df 100644
--- a/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C
+++ b/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C
@@ -557,3 +557,9 @@
 #elif __cpp_multidimensional_subscript != 202110
 #  error "__cpp_multidimensional_subscript != 202110"
 #endif
+
+#ifndef __cpp_auto_cast
+#  error "__cpp_auto_cast"
+#elif __cpp_auto_cast != 202110
+#  error "__cpp_auto_cast != 202110"
+#endif

commit 75526d3f2fc2be8daa8d1e75d2fe6e86f11ba75c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 20 02:20:06 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 69b7e9e68cc..3113e73604c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230519
+20230520
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 7fb93f5f454..797e642b96f 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-19  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-05-15  Patrick Palka  <ppalka@redhat.com>
+
+	* c-cppbuiltin.cc (c_cpp_builtins): Predefine __cpp_auto_cast
+	for C++23.
+
 2023-05-09  Martin Uecker  <uecker@tugraz.at>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c6c91cbfd3b..8aab18d558a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2023-05-19  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-05-15  Patrick Palka  <ppalka@redhat.com>
+
+	* g++.dg/cpp23/feat-cxx2b.C: Test __cpp_auto_cast.
+
 2023-05-18  Alexandre Oliva  <oliva@adacore.com>
 
 	* gcc.target/arm/acle/cde-mve-full-assembly.c: Drop blank

commit 95ca40b04cffd9e3bb8d61654c3a1f2c2d50bb15
Author: Triffid Hunter <triffid.hunter@gmail.com>
Date:   Sat May 20 07:50:00 2023

    target/105753: Fix ICE in add_clobbers due to extra PARALLEL in insn.
    
    This patch removes the superfluous parallel in [u]divmod patterns in
    the AVR backend.  Effect of extra parallel is that add_clobbers reaches
    gcc_unreachable() because the clobbers for [u]divmod are missing.
    If an insn has multiple parts like clobbers, the parallel around the
    parts of the insn pattern is implicit.
    
    gcc/
            PR target/105753
            Backport from 2023-05-20 https://gcc.gnu.org/r14-1016
            * config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi):
            Remove superfluous "parallel" in insn pattern.
            ([u]divmod<mode>4): Tidy code.  Use gcc_unreachable() instead of
            printing error text to assembly.
    
    gcc/testsuite/
            PR target/105753
            Backport from 2023-05-20 https://gcc.gnu.org/r14-1016
            * gcc.target/avr/torture/pr105753.c: New test.

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index efae7efb69b..1c12a5b2def 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -3706,17 +3706,17 @@
 ;;    CSE has problems to operate on hard regs.
 ;;
 (define_insn_and_split "divmodqi4"
-  [(set (match_operand:QI 0 "pseudo_register_operand" "")
-        (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
-                (match_operand:QI 2 "pseudo_register_operand" "")))
-   (set (match_operand:QI 3 "pseudo_register_operand" "")
+  [(set (match_operand:QI 0 "pseudo_register_operand")
+        (div:QI (match_operand:QI 1 "pseudo_register_operand")
+                (match_operand:QI 2 "pseudo_register_operand")))
+   (set (match_operand:QI 3 "pseudo_register_operand")
         (mod:QI (match_dup 1) (match_dup 2)))
    (clobber (reg:QI 22))
    (clobber (reg:QI 23))
    (clobber (reg:QI 24))
    (clobber (reg:QI 25))]
   ""
-  "this divmodqi4 pattern should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:QI 24) (match_dup 1))
    (set (reg:QI 22) (match_dup 2))
@@ -3752,17 +3752,17 @@
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodqi4"
- [(set (match_operand:QI 0 "pseudo_register_operand" "")
-       (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
-                (match_operand:QI 2 "pseudo_register_operand" "")))
-       (set (match_operand:QI 3 "pseudo_register_operand" "")
-            (umod:QI (match_dup 1) (match_dup 2)))
-       (clobber (reg:QI 22))
-       (clobber (reg:QI 23))
-       (clobber (reg:QI 24))
-       (clobber (reg:QI 25))]
-  ""
-  "this udivmodqi4 pattern should have been splitted;"
+ [(set (match_operand:QI 0 "pseudo_register_operand")
+       (udiv:QI (match_operand:QI 1 "pseudo_register_operand")
+                (match_operand:QI 2 "pseudo_register_operand")))
+  (set (match_operand:QI 3 "pseudo_register_operand")
+       (umod:QI (match_dup 1) (match_dup 2)))
+  (clobber (reg:QI 22))
+  (clobber (reg:QI 23))
+  (clobber (reg:QI 24))
+  (clobber (reg:QI 25))]
+  ""
+  { gcc_unreachable(); }
   ""
   [(set (reg:QI 24) (match_dup 1))
    (set (reg:QI 22) (match_dup 2))
@@ -3794,17 +3794,17 @@
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "divmodhi4"
-  [(set (match_operand:HI 0 "pseudo_register_operand" "")
-        (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
-                (match_operand:HI 2 "pseudo_register_operand" "")))
-   (set (match_operand:HI 3 "pseudo_register_operand" "")
+  [(set (match_operand:HI 0 "pseudo_register_operand")
+        (div:HI (match_operand:HI 1 "pseudo_register_operand")
+                (match_operand:HI 2 "pseudo_register_operand")))
+   (set (match_operand:HI 3 "pseudo_register_operand")
         (mod:HI (match_dup 1) (match_dup 2)))
    (clobber (reg:QI 21))
    (clobber (reg:HI 22))
    (clobber (reg:HI 24))
    (clobber (reg:HI 26))]
   ""
-  "this should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:HI 24) (match_dup 1))
    (set (reg:HI 22) (match_dup 2))
@@ -3840,17 +3840,17 @@
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodhi4"
-  [(set (match_operand:HI 0 "pseudo_register_operand" "")
-        (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
-                 (match_operand:HI 2 "pseudo_register_operand" "")))
-   (set (match_operand:HI 3 "pseudo_register_operand" "")
+  [(set (match_operand:HI 0 "pseudo_register_operand")
+        (udiv:HI (match_operand:HI 1 "pseudo_register_operand")
+                 (match_operand:HI 2 "pseudo_register_operand")))
+   (set (match_operand:HI 3 "pseudo_register_operand")
         (umod:HI (match_dup 1) (match_dup 2)))
    (clobber (reg:QI 21))
    (clobber (reg:HI 22))
    (clobber (reg:HI 24))
    (clobber (reg:HI 26))]
   ""
-  "this udivmodhi4 pattern should have been splitted.;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:HI 24) (match_dup 1))
    (set (reg:HI 22) (match_dup 2))
@@ -4091,14 +4091,14 @@
 ;; implementation works the other way round.
 
 (define_insn_and_split "divmodpsi4"
-  [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
-                   (div:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
-                            (match_operand:PSI 2 "pseudo_register_operand" "")))
-              (set (match_operand:PSI 3 "pseudo_register_operand" "")
-                   (mod:PSI (match_dup 1)
-                            (match_dup 2)))
-              (clobber (reg:DI 18))
-              (clobber (reg:QI 26))])]
+  [(set (match_operand:PSI 0 "pseudo_register_operand")
+        (div:PSI (match_operand:PSI 1 "pseudo_register_operand")
+                 (match_operand:PSI 2 "pseudo_register_operand")))
+   (set (match_operand:PSI 3 "pseudo_register_operand")
+        (mod:PSI (match_dup 1)
+                 (match_dup 2)))
+   (clobber (reg:DI 18))
+   (clobber (reg:QI 26))]
   ""
   { gcc_unreachable(); }
   ""
@@ -4140,14 +4140,14 @@
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodpsi4"
-  [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
-                   (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
-                             (match_operand:PSI 2 "pseudo_register_operand" "")))
-              (set (match_operand:PSI 3 "pseudo_register_operand" "")
-                   (umod:PSI (match_dup 1)
-                             (match_dup 2)))
-              (clobber (reg:DI 18))
-              (clobber (reg:QI 26))])]
+  [(set (match_operand:PSI 0 "pseudo_register_operand")
+        (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand")
+                  (match_operand:PSI 2 "pseudo_register_operand")))
+   (set (match_operand:PSI 3 "pseudo_register_operand")
+        (umod:PSI (match_dup 1)
+                  (match_dup 2)))
+   (clobber (reg:DI 18))
+   (clobber (reg:QI 26))]
   ""
   { gcc_unreachable(); }
   ""
@@ -4191,17 +4191,18 @@
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (define_insn_and_split "divmodsi4"
-  [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
-                   (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
-                           (match_operand:SI 2 "pseudo_register_operand" "")))
-              (set (match_operand:SI 3 "pseudo_register_operand" "")
-                   (mod:SI (match_dup 1) (match_dup 2)))
-              (clobber (reg:SI 18))
-              (clobber (reg:SI 22))
-              (clobber (reg:HI 26))
-              (clobber (reg:HI 30))])]
+  [(set (match_operand:SI 0 "pseudo_register_operand")
+        (div:SI (match_operand:SI 1 "pseudo_register_operand")
+                (match_operand:SI 2 "pseudo_register_operand")))
+   (set (match_operand:SI 3 "pseudo_register_operand")
+        (mod:SI (match_dup 1)
+	        (match_dup 2)))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 22))
+   (clobber (reg:HI 26))
+   (clobber (reg:HI 30))]
   ""
-  "this divmodsi4 pattern should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:SI 22) (match_dup 1))
    (set (reg:SI 18) (match_dup 2))
@@ -4237,17 +4238,18 @@
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodsi4"
-  [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
-                   (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
-                           (match_operand:SI 2 "pseudo_register_operand" "")))
-              (set (match_operand:SI 3 "pseudo_register_operand" "")
-                   (umod:SI (match_dup 1) (match_dup 2)))
-              (clobber (reg:SI 18))
-              (clobber (reg:SI 22))
-              (clobber (reg:HI 26))
-              (clobber (reg:HI 30))])]
+  [(set (match_operand:SI 0 "pseudo_register_operand")
+        (udiv:SI (match_operand:SI 1 "pseudo_register_operand")
+                 (match_operand:SI 2 "pseudo_register_operand")))
+   (set (match_operand:SI 3 "pseudo_register_operand")
+        (umod:SI (match_dup 1)
+                 (match_dup 2)))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 22))
+   (clobber (reg:HI 26))
+   (clobber (reg:HI 30))]
   ""
-  "this udivmodsi4 pattern should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:SI 22) (match_dup 1))
    (set (reg:SI 18) (match_dup 2))
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr105753.c b/gcc/testsuite/gcc.target/avr/torture/pr105753.c
new file mode 100644
index 00000000000..7d7cea1de7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr105753.c
@@ -0,0 +1,13 @@
+int digit_sum (unsigned long n)
+{
+  int sum = 0;
+
+  do
+    {
+      int x = n % 10;
+      n /= 10;
+      sum += x;
+    } while(n);
+
+  return sum;
+}

commit 7259fd5bd4c922f396465c9cfec2ec342969f9a9
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Sun May 14 21:53:51 2023

    Fortran: CLASS pointer function result in variable definition context [PR109846]
    
    gcc/fortran/ChangeLog:
    
            PR fortran/109846
            * expr.cc (gfc_check_vardef_context): Check appropriate pointer
            attribute for CLASS vs. non-CLASS function result in variable
            definition context.
    
    gcc/testsuite/ChangeLog:
    
            PR fortran/109846
            * gfortran.dg/ptr-func-5.f90: New test.
    
    (cherry picked from commit fa0569e90efe8a5cb895a3f50dd502f849940828)

diff --git a/gcc/fortran/expr.cc b/gcc/fortran/expr.cc
index 1369f25011f..c04403a2b89 100644
--- a/gcc/fortran/expr.cc
+++ b/gcc/fortran/expr.cc
@@ -6254,7 +6254,7 @@ gfc_check_vardef_context (gfc_expr* e, bool pointer, bool alloc_obj,
       && !(sym->attr.flavor == FL_PROCEDURE && sym == sym->result)
       && !(sym->attr.flavor == FL_PROCEDURE && sym->attr.proc_pointer)
       && !(sym->attr.flavor == FL_PROCEDURE
-	   && sym->attr.function && sym->attr.pointer))
+	   && sym->attr.function && attr.pointer))
     {
       if (context)
 	gfc_error ("%qs in variable definition context (%s) at %L is not"
diff --git a/gcc/testsuite/gfortran.dg/ptr-func-5.f90 b/gcc/testsuite/gfortran.dg/ptr-func-5.f90
new file mode 100644
index 00000000000..05fd56703ca
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/ptr-func-5.f90
@@ -0,0 +1,39 @@
+! { dg-do compile }
+! PR fortran/109846
+! CLASS pointer function result in variable definition context
+
+module foo
+  implicit none
+  type :: parameter_list
+  contains
+    procedure :: sublist, sublist_nores
+  end type
+contains
+  function sublist (this) result (slist)
+    class(parameter_list), intent(inout) :: this
+    class(parameter_list), pointer       :: slist
+    allocate (slist)
+  end function
+  function sublist_nores (this)
+    class(parameter_list), intent(inout) :: this
+    class(parameter_list), pointer       :: sublist_nores
+    allocate (sublist_nores)
+  end function
+end module
+
+program example
+  use foo
+  implicit none
+  type(parameter_list) :: plist
+  call sub1 (plist%sublist())
+  call sub1 (plist%sublist_nores())
+  call sub2 (plist%sublist())
+  call sub2 (plist%sublist_nores())
+contains
+  subroutine sub1 (plist)
+    type(parameter_list), intent(inout) :: plist
+  end subroutine
+  subroutine sub2 (plist)
+    type(parameter_list) :: plist
+  end subroutine
+end program

commit bdbb2ba03096392b749866a9f47c6823b2d12f42
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 21 02:20:00 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7684ea17fc5..47fc2c9c019 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2023-05-20  Triffid Hunter  <triffid.hunter@gmail.com>
+
+	PR target/105753
+	Backport from 2023-05-20 https://gcc.gnu.org/r14-1016
+	* config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi):
+	Remove superfluous "parallel" in insn pattern.
+	([u]divmod<mode>4): Tidy code.  Use gcc_unreachable() instead of
+	printing error text to assembly.
+
 2023-05-18  Alexandre Oliva  <oliva@adacore.com>
 
 	* config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3113e73604c..7b10b7bde80 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230520
+20230521
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index c8ecd75c778..111242f14d6 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2023-05-20  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-05-15  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/109846
+	* expr.cc (gfc_check_vardef_context): Check appropriate pointer
+	attribute for CLASS vs. non-CLASS function result in variable
+	definition context.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8aab18d558a..4180855541f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2023-05-20  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-05-15  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/109846
+	* gfortran.dg/ptr-func-5.f90: New test.
+
+2023-05-20  Triffid Hunter  <triffid.hunter@gmail.com>
+
+	PR target/105753
+	Backport from 2023-05-20 https://gcc.gnu.org/r14-1016
+	* gcc.target/avr/torture/pr105753.c: New test.
+
 2023-05-19  Patrick Palka  <ppalka@redhat.com>
 
 	Backported from master:

commit 1df72374dd367d7549217c2625b7f843ec1c8e6e
Author: Iain Sandoe <iain@sandoe.co.uk>
Date:   Mon Apr 17 11:23:16 2023

    libsanitizer, darwin: Unsupport Darwin >= 22 for now.
    
    The mechanism for location dyld has altered from Darwin22 since dyld is now
    in the shared cache.  The implemented mechanism for walking the cache uses
    Apple Blocks which GCC does not yet support, and the fallback to the original
    mechanism does not work there.
    
    Until a suitable work-around can be found, unsupport Darwin22+.
    
            Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
    
    libsanitizer/ChangeLog:
    
            * configure.tgt: Unsupport Darwin22+ until a mechanism can be found
            to locate dyld in the shared cache.
    
    (cherry picked from commit e722a1f42b28092c9f709a3f758fc4fe57db32b0)

diff --git a/libsanitizer/configure.tgt b/libsanitizer/configure.tgt
index fb89df4935c..bc169c365f2 100644
--- a/libsanitizer/configure.tgt
+++ b/libsanitizer/configure.tgt
@@ -64,7 +64,7 @@ case "${target}" in
 		HWASAN_SUPPORTED=yes
 	fi
 	;;
-  x86_64-*-darwin2* | x86_64-*-darwin1[2-9]* | i?86-*-darwin1[2-9]*)
+  x86_64-*-darwin2[01]* | x86_64-*-darwin1[2-9]* | i?86-*-darwin1[2-9]*)
 	TSAN_SUPPORTED=no
 	EXTRA_CXXFLAGS="${EXTRA_CXXFLAGS} -Wl,-undefined,dynamic_lookup"
 	;;

commit a3ec0bd85945a271a6a253faea4a073cc1efec9a
Author: Iain Sandoe <iain@sandoe.co.uk>
Date:   Fri May 12 00:24:02 2023

    Darwin, libgcc : Adjust min version supported for the OS.
    
    Tools from later versions of the OS deprecate or fail to support
    earlier OS revisions.
    
    Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
    
    libgcc/ChangeLog:
    
            * config.host: Arrange to set min Darwin OS versions from
            the configured host version.
            * config/darwin10-unwind-find-enc-func.c: Do not use current
            headers, but declare the nexessary structures locally to the
            versions in use for Mac OSX 10.6.
            * config/t-darwin: Amend to handle configured min OS
            versions.
            * config/t-darwin-min-1: New.
            * config/t-darwin-min-5: New.
            * config/t-darwin-min-8: New.
    
    (cherry picked from commit 20b8779ea9bd82b26eeb195b30f695168cd7ae1d)

diff --git a/libgcc/config.host b/libgcc/config.host
index 8c56fcae5d2..89e3dbc7c8a 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -241,6 +241,24 @@ case ${host} in
       ;;
   esac
   tmake_file="$tmake_file t-slibgcc-darwin"
+  # newer toolsets produce warnings when building for unsupported versions.
+  case ${host} in
+    *-*-darwin1[89]* | *-*-darwin2* )
+      tmake_file="t-darwin-min-8 $tmake_file"
+      ;;
+    *-*-darwin9* | *-*-darwin1[0-7]*)
+      tmake_file="t-darwin-min-5 $tmake_file"
+      ;;
+    *-*-darwin[4-8]*)
+      tmake_file="t-darwin-min-1 $tmake_file"
+      ;;
+    *)
+      # Fall back to configuring for the oldest system known to work with
+      # all archs and the current sources.
+      tmake_file="t-darwin-min-5 $tmake_file"
+      echo "Warning: libgcc configured to support macOS 10.5" 1>&2
+      ;;
+  esac
   extra_parts="crt3.o libd10-uwfef.a crttms.o crttme.o libemutls_w.a"
   ;;
 *-*-dragonfly*)
diff --git a/libgcc/config/darwin10-unwind-find-enc-func.c b/libgcc/config/darwin10-unwind-find-enc-func.c
index 882ec3a2372..b08396c5f1b 100644
--- a/libgcc/config/darwin10-unwind-find-enc-func.c
+++ b/libgcc/config/darwin10-unwind-find-enc-func.c
@@ -1,8 +1,34 @@
-#include "tconfig.h"
-#include "tsystem.h"
-#include "unwind-dw2-fde.h"
 #include "libgcc_tm.h"
 
+/* This shim is special, it needs to be built for Mac OSX 10.6
+   regardless of the current system version.
+   We must also build it to use the unwinder layout that was
+   present for 10.6 (and not update that).
+   So we copy the referenced structures from unwind-dw2-fde.h
+   to avoid pulling in newer system headers and/or changed
+   layouts.  */
+struct dwarf_eh_bases
+{
+  void *tbase;
+  void *dbase;
+  void *func;
+};
+
+typedef          int  sword __attribute__ ((mode (SI)));
+typedef unsigned int  uword __attribute__ ((mode (SI)));
+
+/* The first few fields of an FDE.  */
+struct dwarf_fde
+{
+  uword length;
+  sword CIE_delta;
+  unsigned char pc_begin[];
+} __attribute__ ((packed, aligned (__alignof__ (void *))));
+
+typedef struct dwarf_fde fde;
+
+extern const fde * _Unwind_Find_FDE (void *, struct dwarf_eh_bases *);
+
 void *
 _darwin10_Unwind_FindEnclosingFunction (void *pc)
 {
@@ -10,5 +36,5 @@ _darwin10_Unwind_FindEnclosingFunction (void *pc)
   const struct dwarf_fde *fde = _Unwind_Find_FDE (pc-1, &bases);
   if (fde)
     return bases.func;
-  return NULL;
+  return (void *) 0;
 }
diff --git a/libgcc/config/t-darwin b/libgcc/config/t-darwin
index 299d26c2c96..a3bb70c6a0a 100644
--- a/libgcc/config/t-darwin
+++ b/libgcc/config/t-darwin
@@ -1,15 +1,15 @@
 # Set this as a minimum (unless overriden by arch t-files) since it's a
 # reasonable lowest common denominator that works for all our archs.
-HOST_LIBGCC2_CFLAGS += -mmacosx-version-min=10.4
+HOST_LIBGCC2_CFLAGS += $(DARWIN_MIN_LIB_VERSION)
 
 crt3.o: $(srcdir)/config/darwin-crt3.c
-	$(crt_compile) -mmacosx-version-min=10.4 -c $<
+	$(crt_compile) $(DARWIN_MIN_CRT_VERSION) -c $<
 
 crttms.o: $(srcdir)/config/darwin-crt-tm.c
-	$(crt_compile) -mmacosx-version-min=10.4 -DSTART -c $<
+	$(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DSTART -c $<
 
 crttme.o: $(srcdir)/config/darwin-crt-tm.c
-	$(crt_compile) -mmacosx-version-min=10.4 -DEND -c $<
+	$(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DEND -c $<
 
 # Make emutls weak so that we can deal with -static-libgcc, override the
 # hidden visibility when this is present in libgcc_eh.
@@ -25,6 +25,8 @@ libemutls_w.a: emutls_s.o
 	$(RANLIB_FOR_TARGET) $@
 
 # Patch to __Unwind_Find_Enclosing_Function for Darwin10.
+# This needs to be built for darwin10, regardless of the current platform
+# version.
 d10-uwfef.o: $(srcdir)/config/darwin10-unwind-find-enc-func.c libgcc_tm.h
 	$(crt_compile) -mmacosx-version-min=10.6 -c $<
 
diff --git a/libgcc/config/t-darwin-min-1 b/libgcc/config/t-darwin-min-1
new file mode 100644
index 00000000000..8c2cf8acd39
--- /dev/null
+++ b/libgcc/config/t-darwin-min-1
@@ -0,0 +1,3 @@
+# Support building with -mmacosx-version-min back to 10.1.
+DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.4
+DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.1
diff --git a/libgcc/config/t-darwin-min-5 b/libgcc/config/t-darwin-min-5
new file mode 100644
index 00000000000..138193151e7
--- /dev/null
+++ b/libgcc/config/t-darwin-min-5
@@ -0,0 +1,3 @@
+# Support building with -mmacosx-version-min back to 10.5.
+DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.5
+DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.5
diff --git a/libgcc/config/t-darwin-min-8 b/libgcc/config/t-darwin-min-8
new file mode 100644
index 00000000000..9efc9dc0257
--- /dev/null
+++ b/libgcc/config/t-darwin-min-8
@@ -0,0 +1,3 @@
+# Support building with -mmacosx-version-min back to 10.8.
+DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.8
+DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.8

commit cdab84e127daf8ea2582e2f0c8faaeadb6dca66a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon May 22 02:20:36 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7b10b7bde80..f25bef13f1e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230521
+20230522
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 673c62f12dc..a45d5185770 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,19 @@
+2023-05-21  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-05-19  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* config.host: Arrange to set min Darwin OS versions from
+	the configured host version.
+	* config/darwin10-unwind-find-enc-func.c: Do not use current
+	headers, but declare the nexessary structures locally to the
+	versions in use for Mac OSX 10.6.
+	* config/t-darwin: Amend to handle configured min OS
+	versions.
+	* config/t-darwin-min-1: New.
+	* config/t-darwin-min-5: New.
+	* config/t-darwin-min-8: New.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/libsanitizer/ChangeLog b/libsanitizer/ChangeLog
index 2f85d1dbdfb..77752060f6f 100644
--- a/libsanitizer/ChangeLog
+++ b/libsanitizer/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-21  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-04-18  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* configure.tgt: Unsupport Darwin22+ until a mechanism can be found
+	to locate dyld in the shared cache.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.

commit 15db4bdc93826fe262abcb254b81edf6cfab6fe8
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed May 17 09:48:40 2023

    vect: Don't retry if the previous analysis fails
    
    When working on a cost tweaking patch, I found that a newly
    added test case has different dumpings with stage-1 and
    bootstrapped gcc.  By looking into it, the apparent reason
    is vect_analyze_loop_2 doesn't get slp_done_for_suggested_uf
    set expectedly, the following retrying will use the garbage
    slp_done_for_suggested_uf instead.  In fact, the setting of
    slp_done_for_suggested_uf only happens when the previous
    analysis succeeds, for the mentioned test case, its previous
    analysis does fail, it's unexpected to use the value of
    slp_done_for_suggested_uf any more.
    
    In function vect_analyze_loop_1, we only return success when
    res is true, which is the result of 1st analysis.  It means
    we never try to vectorize with unroll_vinfo if the previous
    analysis fails.  So this patch shouldn't break anything, and
    just stop some useless analysis early.
    
    gcc/ChangeLog:
    
            * tree-vect-loop.cc (vect_analyze_loop_1): Don't retry analysis with
            suggested unroll factor once the previous analysis fails.
    
    (cherry picked from commit a04bf39f61ce7814d197d712760f08c206daf4f1)

diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 3435f9378da..9df2d5690b7 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -2874,7 +2874,7 @@ vect_analyze_loop_1 (class loop *loop, vec_info_shared *shared,
 		     res ? "succeeded" : " failed",
 		     GET_MODE_NAME (loop_vinfo->vector_mode));
 
-  if (!main_loop_vinfo && suggested_unroll_factor > 1)
+  if (res && !main_loop_vinfo && suggested_unroll_factor > 1)
     {
       if (dump_enabled_p ())
 	dump_printf_loc (MSG_NOTE, vect_location,

commit 6ef4e2e11c653f1d51f9a304a8d1cf44a53b4ad7
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sun May 21 13:36:56 2023

    atch.pd: Ensure (op CONSTANT_CLASS_P CONSTANT_CLASS_P) is simplified [PR109505]
    
    On the following testcase we hang, because POLY_INT_CST is CONSTANT_CLASS_P,
    but BIT_AND_EXPR with it and INTEGER_CST doesn't simplify and the
    (x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2)
    simplification actually relies on the (CST1 & CST2) simplification,
    otherwise it is a deoptimization, trading 2 ops for 3 and furthermore
    running into
    /* Given a bit-wise operation CODE applied to ARG0 and ARG1, see if both
       operands are another bit-wise operation with a common input.  If so,
       distribute the bit operations to save an operation and possibly two if
       constants are involved.  For example, convert
         (A | B) & (A | C) into A | (B & C)
       Further simplification will occur if B and C are constants.  */
    simplification which simplifies that
    (x & CST2) | (CST1 & CST2) back to
    CST2 & (x | CST1).
    I went through all other places I could find where we have a simplification
    with 2 CONSTANT_CLASS_P operands and perform some operation on those two,
    while the other spots aren't that severe (just trade 2 operations for
    another 2 if the two constants don't simplify, rather than as in the above
    case trading 2 ops for 3), I still think all those spots really intend
    to optimize only if the 2 constants simplify.
    
    So, the following patch adds to those a ! modifier to ensure that,
    even at GENERIC that modifier means !EXPR_P which is exactly what we want
    IMHO.
    
    2023-05-21  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/109505
            * match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2),
            Combine successive equal operations with constants,
            (A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A,
            CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P
            operands.
    
            * gcc.target/aarch64/sve/pr109505.c: New test.
    
    (cherry picked from commit f211757f6fa9515e3fd1a4f66f1a8b48e500c9de)

diff --git a/gcc/match.pd b/gcc/match.pd
index fc2833bbdca..70b85b965b9 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -1723,7 +1723,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 /* (x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2) */
 (simplify
   (bit_and (bit_ior @0 CONSTANT_CLASS_P@1) CONSTANT_CLASS_P@2)
-  (bit_ior (bit_and @0 @2) (bit_and @1 @2)))
+  (bit_ior (bit_and @0 @2) (bit_and! @1 @2)))
 
 /* Combine successive equal operations with constants.  */
 (for bitop (bit_and bit_ior bit_xor)
@@ -1732,7 +1732,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
   (if (!CONSTANT_CLASS_P (@0))
    /* This is the canonical form regardless of whether (bitop @1 @2) can be
       folded to a constant.  */
-   (bitop @0 (bitop @1 @2))
+   (bitop @0 (bitop! @1 @2))
    /* In this case we have three constants and (bitop @0 @1) doesn't fold
       to a constant.  This can happen if @0 or @1 is a POLY_INT_CST and if
       the values involved are such that the operation can't be decided at
@@ -2635,13 +2635,13 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 	 forever if something doesn't simplify into a constant.  */
       (if (!CONSTANT_CLASS_P (@0))
        (if (outer_op == PLUS_EXPR)
-	(plus (view_convert @0) (inner_op @2 (view_convert @1)))
-	(minus (view_convert @0) (neg_inner_op @2 (view_convert @1)))))
+	(plus (view_convert @0) (inner_op! @2 (view_convert @1)))
+	(minus (view_convert @0) (neg_inner_op! @2 (view_convert @1)))))
       (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0))
 	   || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
        (if (outer_op == PLUS_EXPR)
-	(view_convert (plus @0 (inner_op (view_convert @2) @1)))
-	(view_convert (minus @0 (neg_inner_op (view_convert @2) @1))))
+	(view_convert (plus @0 (inner_op! (view_convert @2) @1)))
+	(view_convert (minus @0 (neg_inner_op! (view_convert @2) @1))))
        /* If the constant operation overflows we cannot do the transform
 	  directly as we would introduce undefined overflow, for example
 	  with (a - 1) + INT_MIN.  */
@@ -2672,10 +2672,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
      /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse
 	forever if something doesn't simplify into a constant.  */
      (if (!CONSTANT_CLASS_P (@0))
-      (minus (outer_op (view_convert @1) @2) (view_convert @0)))
+      (minus (outer_op! (view_convert @1) @2) (view_convert @0)))
      (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0))
 	  || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
-      (view_convert (minus (outer_op @1 (view_convert @2)) @0))
+      (view_convert (minus (outer_op! @1 (view_convert @2)) @0))
       (if (types_match (type, @0))
        (with { tree cst = const_binop (outer_op, type, @1, @2); }
 	(if (cst && !TREE_OVERFLOW (cst))
@@ -2691,10 +2691,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
     /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse
       forever if something doesn't simplify into a constant.  */
     (if (!CONSTANT_CLASS_P (@0))
-     (plus (view_convert @0) (minus @1 (view_convert @2))))
+     (plus (view_convert @0) (minus! @1 (view_convert @2))))
     (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0))
 	 || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
-     (view_convert (plus @0 (minus (view_convert @1) @2)))
+     (view_convert (plus @0 (minus! (view_convert @1) @2)))
      (if (types_match (type, @0))
       (with { tree cst = const_binop (MINUS_EXPR, type, @1, @2); }
        (if (cst && !TREE_OVERFLOW (cst))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c b/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c
new file mode 100644
index 00000000000..b975ae75ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c
@@ -0,0 +1,12 @@
+/* PR tree-optimization/109505 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.2-a+sve" } */
+
+#pragma GCC aarch64 "arm_sve.h"
+
+unsigned long
+foo (unsigned long x)
+{
+  unsigned long y = svcntb ();
+  return (x | 15) & y;
+}

commit 3bb91d31a272d7fd9f02301df101e3041d5aeb5d
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon May 22 17:08:13 2023

    Do not generate vmaddfp and vnmsubfp
    
    This is version 3 of the patch.  This is essentially version 1 with the removal
    of changes to altivec.md, and cleanup of the comments.
    
    Version 2 generated the vmaddfp and vnmsubfp instructions if -Ofast was used,
    and those changes are deleted in this patch.
    
    The Altivec instructions vmaddfp and vnmsubfp have different rounding behaviors
    than the VSX xvmaddsp and xvnmsubsp instructions.  In particular, generating
    these instructions seems to break Eigen on big endian systems.
    
    I have done bootstrap builds on power9 little endian (with both IEEE long
    double and IBM long double).  I have also done the builds and test on a power8
    big endian system (testing both 32-bit and 64-bit code generation).  Chip has
    verified that it fixes the problem that Eigen encountered.  Can I check this
    into the master GCC branch?  After a burn-in period, can I check this patch
    into the active GCC branches?
    
    Thanks in advance.
    
    2023-05-22   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            PR target/70243
            * config/rs6000/vsx.md (vsx_fmav4sf4): Do not generate vmaddfp.
            (vsx_nfmsv4sf4): Do not generate vnmsubfp.  Back port from master
            04/10/2023 change.
    
    gcc/testsuite/
    
            PR target/70243
            * gcc.target/powerpc/pr70243.c: New test.  Back port from master
            04/10/2023 change.

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 068abc1d62e..0b69b60dc14 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2018,22 +2018,20 @@
   "x<VSv>tsqrt<sd>p %0,%x1"
   [(set_attr "type" "<VStype_simple>")])
 
-;; Fused vector multiply/add instructions. Support the classical Altivec
-;; versions of fma, which allows the target to be a separate register from the
-;; 3 inputs.  Under VSX, the target must be either the addend or the first
-;; multiply.
-
+;; Fused vector multiply/add instructions. Do not generate the Altivec versions
+;; of fma (vmaddfp and vnmsubfp).  These instructions allows the target to be a
+;; separate register from the 3 inputs, but they have different rounding
+;; behaviors than the VSX instructions.
 (define_insn "*vsx_fmav4sf4"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
 	(fma:V4SF
-	  (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
-	  (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
-	  (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
+	  (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
+	  (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
+	  (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))]
   "VECTOR_UNIT_VSX_P (V4SFmode)"
   "@
    xvmaddasp %x0,%x1,%x2
-   xvmaddmsp %x0,%x1,%x3
-   vmaddfp %0,%1,%2,%3"
+   xvmaddmsp %x0,%x1,%x3"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "*vsx_fmav2df4"
@@ -2075,18 +2073,17 @@
   [(set_attr "type" "<VStype_mul>")])
 
 (define_insn "*vsx_nfmsv4sf4"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
 	(neg:V4SF
 	 (fma:V4SF
-	   (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
-	   (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
+	   (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
+	   (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
 	   (neg:V4SF
-	     (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
+	     (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))]
   "VECTOR_UNIT_VSX_P (V4SFmode)"
   "@
    xvnmsubasp %x0,%x1,%x2
-   xvnmsubmsp %x0,%x1,%x3
-   vnmsubfp %0,%1,%2,%3"
+   xvnmsubmsp %x0,%x1,%x3"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "*vsx_nfmsv2df4"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
new file mode 100644
index 00000000000..18a5ce78792
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr70243.c
@@ -0,0 +1,41 @@
+/* { dg-do compile */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* PR 70423, Make sure we don't generate vmaddfp or vnmsubfp.  These
+   instructions have different rounding modes than the VSX instructions
+   xvmaddsp and xvnmsubsp.  These tests are written where the 3 inputs and
+   target are all separate registers.  Because vmaddfp and vnmsubfp are no
+   longer generated the compiler will have to generate an xsmaddsp or xsnmsubsp
+   instruction followed by a move operation.  */
+
+#include <altivec.h>
+
+vector float
+do_add1 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return (a * b) + c;
+}
+
+vector float
+do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return -((a * b) - c);
+}
+
+vector float
+do_add2 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return vec_madd (a, b, c);
+}
+
+vector float
+do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return vec_nmsub (a, b, c);
+}
+
+/* { dg-final { scan-assembler     {\mxvmadd[am]sp\M}  } } */
+/* { dg-final { scan-assembler     {\mxvnmsub[am]sp\M} } } */
+/* { dg-final { scan-assembler-not {\mvmaddfp\M}       } } */
+/* { dg-final { scan-assembler-not {\mvnmsubfp\M}      } } */

commit a460f10796ed21900c9f85e702de6bde5134f3c7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 23 02:19:56 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 47fc2c9c019..5fe69aaf2d0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,30 @@
+2023-05-22   Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/70243
+	* config/rs6000/vsx.md (vsx_fmav4sf4): Do not generate vmaddfp.
+	(vsx_nfmsv4sf4): Do not generate vnmsubfp.  Back port from master
+	04/10/2023 change.
+
+2023-05-22  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109505
+	* match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2),
+	Combine successive equal operations with constants,
+	(A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A,
+	CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P
+	operands.
+
+2023-05-22  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-05-17  Kewen Lin  <linkw@linux.ibm.com>
+
+	* tree-vect-loop.cc (vect_analyze_loop_1): Don't retry analysis with
+	suggested unroll factor once the previous analysis fails.
+
 2023-05-20  Triffid Hunter  <triffid.hunter@gmail.com>
 
 	PR target/105753
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f25bef13f1e..b7d9ba7ed1a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230522
+20230523
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4180855541f..00cb9083c22 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2023-05-22   Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/70243
+	* gcc.target/powerpc/pr70243.c: New test.  Back port from master
+	04/10/2023 change.
+
+2023-05-22  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109505
+	* gcc.target/aarch64/sve/pr109505.c: New test.
+
 2023-05-20  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:

commit d3217028725f06f4eb67a4c80b12e1a3219d3502
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Sat Jan 14 17:07:59 2023

    libstdc++: Annotate most lambdas with always_inline
    
    All of the annotated lambdas are simply a necessary means for
    implementing these functions and should never result in an actual
    function call. Many of these lambdas would go away if C++ had better
    language support for packs.
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/108030
            * include/experimental/bits/simd_detail.h: Define
            _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA.
            * include/experimental/bits/simd.h: Annotate lambdas with
            _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA.
            * include/experimental/bits/simd_builtin.h: Ditto.
            * include/experimental/bits/simd_converter.h: Ditto.
            * include/experimental/bits/simd_fixed_size.h: Ditto.
            * include/experimental/bits/simd_math.h: Ditto.
            * include/experimental/bits/simd_neon.h: Ditto.
            * include/experimental/bits/simd_x86.h: Ditto.
    
    (cherry picked from commit 53b55701aed6896f456cdec7997ac6bbef1d6074)

diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h
index 7c5a32f6e95..8fcd45c6c45 100644
--- a/libstdc++-v3/include/experimental/bits/simd.h
+++ b/libstdc++-v3/include/experimental/bits/simd.h
@@ -609,28 +609,34 @@ template <size_t _Bytes>
 	  operator&(_Ip __rhs) const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return __rhs._M_data[__i] & _M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __rhs._M_data[__i] & _M_data[__i];
+	      });
 	  }
 
 	  _GLIBCXX_SIMD_INTRINSIC constexpr _Ip
 	  operator|(_Ip __rhs) const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return __rhs._M_data[__i] | _M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __rhs._M_data[__i] | _M_data[__i];
+	      });
 	  }
 
 	  _GLIBCXX_SIMD_INTRINSIC constexpr _Ip
 	  operator^(_Ip __rhs) const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return __rhs._M_data[__i] ^ _M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __rhs._M_data[__i] ^ _M_data[__i];
+	      });
 	  }
 
 	  _GLIBCXX_SIMD_INTRINSIC constexpr _Ip
 	  operator~() const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return ~_M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return ~_M_data[__i]; });
 	  }
 	};
 	return _Ip{};
@@ -1391,7 +1397,7 @@ template <size_t _Np, bool _Sanitized>
     operator^=(const _BitMask& __b) & noexcept
     {
       __execute_n_times<_S_array_size>(
-	[&](auto __i) { _M_bits[__i] ^= __b._M_bits[__i]; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] ^= __b._M_bits[__i]; });
       return *this;
     }
 
@@ -1399,7 +1405,7 @@ template <size_t _Np, bool _Sanitized>
     operator|=(const _BitMask& __b) & noexcept
     {
       __execute_n_times<_S_array_size>(
-	[&](auto __i) { _M_bits[__i] |= __b._M_bits[__i]; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] |= __b._M_bits[__i]; });
       return *this;
     }
 
@@ -1407,7 +1413,7 @@ template <size_t _Np, bool _Sanitized>
     operator&=(const _BitMask& __b) & noexcept
     {
       __execute_n_times<_S_array_size>(
-	[&](auto __i) { _M_bits[__i] &= __b._M_bits[__i]; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] &= __b._M_bits[__i]; });
       return *this;
     }
 
@@ -2206,7 +2212,7 @@ template <int _Offset,
 #endif
 	constexpr int _O = _Offset * __return_width;
 	return __call_with_subscripts<__return_width, _O>(
-	  __x, [](auto... __entries) {
+	  __x, [](auto... __entries) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    return reinterpret_cast<_R>(_Up{__entries...});
 	  });
       }
@@ -2608,7 +2614,7 @@ template <typename _Tp, size_t _Width>
 
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(initializer_list<_Tp> __init)
       : _Base(__generate_from_n_evaluations<_Width, _BuiltinType>(
-	[&](auto __i) { return __init.begin()[__i.value]; })) {}
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __init.begin()[__i.value]; })) {}
 
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper() = default;
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(const _SimdWrapper&)
@@ -2633,10 +2639,9 @@ template <typename _Tp, size_t _Width>
       _GLIBCXX_SIMD_INTRINSIC constexpr
       operator _SimdTuple<_Tp, _As...>() const
       {
-	const auto& dd = _M_data; // workaround for GCC7 ICE
-	return __generate_from_n_evaluations<sizeof...(_As),
-					     _SimdTuple<_Tp, _As...>>([&](
-	  auto __i) constexpr { return dd[int(__i)]; });
+	return __generate_from_n_evaluations<sizeof...(_As), _SimdTuple<_Tp, _As...>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		 { return _M_data[int(__i)]; });
       }
 
     _GLIBCXX_SIMD_INTRINSIC constexpr operator const _BuiltinType&() const
@@ -3193,21 +3198,19 @@ template <typename _Tp, int _Np>
   { return __x; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC auto
+  _GLIBCXX_SIMD_INTRINSIC fixed_size_simd<_Tp, simd_size_v<_Tp, _Ap>>
   to_fixed_size(const simd<_Tp, _Ap>& __x)
   {
-    return simd<_Tp, simd_abi::fixed_size<simd_size_v<_Tp, _Ap>>>([&__x](
-      auto __i) constexpr { return __x[__i]; });
+    using _Rp = fixed_size_simd<_Tp, simd_size_v<_Tp, _Ap>>;
+    return _Rp([&__x](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
   }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC auto
+  _GLIBCXX_SIMD_INTRINSIC fixed_size_simd_mask<_Tp, simd_size_v<_Tp, _Ap>>
   to_fixed_size(const simd_mask<_Tp, _Ap>& __x)
   {
-    constexpr int _Np = simd_mask<_Tp, _Ap>::size();
-    fixed_size_simd_mask<_Tp, _Np> __r;
-    __execute_n_times<_Np>([&](auto __i) constexpr { __r[__i] = __x[__i]; });
-    return __r;
+    return {__private_init,
+	    [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }};
   }
 
 // to_native {{{2
@@ -3226,7 +3229,9 @@ template <typename _Tp, size_t _Np>
   enable_if_t<(_Np == native_simd_mask<_Tp>::size()), native_simd_mask<_Tp>>
   to_native(const fixed_size_simd_mask<_Tp, _Np>& __x)
   {
-    return native_simd_mask<_Tp>([&](auto __i) constexpr { return __x[__i]; });
+    return native_simd_mask<_Tp>(
+	     __private_init,
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
   }
 
 // to_compatible {{{2
@@ -3243,7 +3248,10 @@ template <typename _Tp, size_t _Np>
   _GLIBCXX_SIMD_INTRINSIC
   enable_if_t<(_Np == simd_mask<_Tp>::size()), simd_mask<_Tp>>
   to_compatible(const simd_mask<_Tp, simd_abi::fixed_size<_Np>>& __x)
-  { return simd_mask<_Tp>([&](auto __i) constexpr { return __x[__i]; }); }
+  {
+    return simd_mask<_Tp>(
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
+  }
 
 // masked assignment [simd_mask.where] {{{1
 
@@ -3401,9 +3409,9 @@ template <typename _M, typename _Tp>
       _Impl::template _S_masked_cassign(                                       \
 	__data(_M_k), __data(_M_value),                                        \
 	__to_value_type_or_member_type<_Tp>(static_cast<_Up&&>(__x)),          \
-	[](auto __impl, auto __lhs, auto __rhs) constexpr {                    \
-	return __impl.__name(__lhs, __rhs);                                    \
-	});                                                                    \
+	[](auto __impl, auto __lhs, auto __rhs)                                \
+	  constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA                         \
+	{ return __impl.__name(__lhs, __rhs); });                              \
     }                                                                          \
   static_assert(true)
     _GLIBCXX_SIMD_OP_(+, _S_plus);
@@ -3900,12 +3908,11 @@ template <typename _V, typename _Ap,
       }
     else if (__x._M_is_constprop())
       {
-	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	  auto __i) constexpr {
-	  return _V([&](auto __j) constexpr {
-	    return __x[__i * _V::size() + __j];
-	  });
-	});
+	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+			     { return __x[__i * _V::size() + __j]; });
+		 });
       }
     else if constexpr (
       __is_fixed_size_abi_v<_Ap>
@@ -3918,41 +3925,40 @@ template <typename _V, typename _Ap,
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
       const __may_alias<_Tp>* const __element_ptr
 	= reinterpret_cast<const __may_alias<_Tp>*>(&__data(__x));
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr {
-	return _V(__element_ptr + __i * _V::size(), vector_aligned);
-      });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	       { return _V(__element_ptr + __i * _V::size(), vector_aligned); });
 #else
       const auto& __xx = __data(__x);
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr {
-	[[maybe_unused]] constexpr size_t __offset
-	  = decltype(__i)::value * _V::size();
-	return _V([&](auto __j) constexpr {
-	  constexpr _SizeConstant<__j + __offset> __k;
-	  return __xx[__k];
-	});
-      });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 [[maybe_unused]] constexpr size_t __offset
+		   = decltype(__i)::value * _V::size();
+		 return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			  constexpr _SizeConstant<__j + __offset> __k;
+			  return __xx[__k];
+			});
+	       });
 #endif
     }
   else if constexpr (is_same_v<typename _V::abi_type, simd_abi::scalar>)
     {
       // normally memcpy should work here as well
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr { return __x[__i]; });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
     }
   else
     {
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr {
-	if constexpr (__is_fixed_size_abi_v<typename _V::abi_type>)
-	  return _V([&](auto __j) constexpr {
-	    return __x[__i * _V::size() + __j];
-	  });
-	else
-	  return _V(__private_init,
-		    __extract_part<decltype(__i)::value, _Parts>(__data(__x)));
-      });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 if constexpr (__is_fixed_size_abi_v<typename _V::abi_type>)
+		   return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			    return __x[__i * _V::size() + __j];
+			  });
+		 else
+		   return _V(__private_init,
+			     __extract_part<decltype(__i)::value, _Parts>(__data(__x)));
+	       });
     }
   }
 
@@ -3976,22 +3982,22 @@ template <typename _V, typename _Ap,
     else if constexpr (_V::size() <= __CHAR_BIT__ * sizeof(_ULLong))
       {
 	const bitset __bits = __x.__to_bitset();
-	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	  auto __i) constexpr {
-	  constexpr size_t __offset = __i * _V::size();
-	  return _V(__bitset_init, (__bits >> __offset).to_ullong());
-	});
+	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   constexpr size_t __offset = __i * _V::size();
+		   return _V(__bitset_init, (__bits >> __offset).to_ullong());
+		 });
       }
     else
       {
-	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	  auto __i) constexpr {
-	  constexpr size_t __offset = __i * _V::size();
-	  return _V(
-	    __private_init, [&](auto __j) constexpr {
-	      return __x[__j + __offset];
-	    });
-	});
+	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   constexpr size_t __offset = __i * _V::size();
+		   return _V(__private_init,
+			     [&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			       return __x[__j + __offset];
+			     });
+		 });
       }
   }
 
@@ -4009,12 +4015,14 @@ template <size_t... _Sizes, typename _Tp, typename _Ap, typename>
     using _V = __deduced_simd<_Tp, _N0>;
 
     if (__x._M_is_constprop())
-      return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>([&](
-	auto __i) constexpr {
-	using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
-	constexpr size_t __offset = _SL::_S_before(__i);
-	return _Vi([&](auto __j) constexpr { return __x[__offset + __j]; });
-      });
+      return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
+		 constexpr size_t __offset = _SL::_S_before(__i);
+		 return _Vi([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			  return __x[__offset + __j];
+			});
+	       });
     else if constexpr (_Np == _N0)
       {
 	static_assert(sizeof...(_Sizes) == 1);
@@ -4081,28 +4089,28 @@ template <size_t... _Sizes, typename _Tp, typename _Ap, typename>
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
     const __may_alias<_Tp>* const __element_ptr
       = reinterpret_cast<const __may_alias<_Tp>*>(&__x);
-    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>([&](
-      auto __i) constexpr {
-      using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
-      constexpr size_t __offset = _SL::_S_before(__i);
-      constexpr size_t __base_align = alignof(simd<_Tp, _Ap>);
-      constexpr size_t __a
-	= __base_align - ((__offset * sizeof(_Tp)) % __base_align);
-      constexpr size_t __b = ((__a - 1) & __a) ^ __a;
-      constexpr size_t __alignment = __b == 0 ? __a : __b;
-      return _Vi(__element_ptr + __offset, overaligned<__alignment>);
-    });
+    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>(
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	       using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
+	       constexpr size_t __offset = _SL::_S_before(__i);
+	       constexpr size_t __base_align = alignof(simd<_Tp, _Ap>);
+	       constexpr size_t __a
+		 = __base_align - ((__offset * sizeof(_Tp)) % __base_align);
+	       constexpr size_t __b = ((__a - 1) & __a) ^ __a;
+	       constexpr size_t __alignment = __b == 0 ? __a : __b;
+	       return _Vi(__element_ptr + __offset, overaligned<__alignment>);
+	     });
 #else
-    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>([&](
-      auto __i) constexpr {
-      using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
-      const auto& __xx = __data(__x);
-      using _Offset = decltype(_SL::_S_before(__i));
-      return _Vi([&](auto __j) constexpr {
-	constexpr _SizeConstant<_Offset::value + __j> __k;
-	return __xx[__k];
-      });
-    });
+    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>(
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	       using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
+	       const auto& __xx = __data(__x);
+	       using _Offset = decltype(_SL::_S_before(__i));
+	       return _Vi([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			constexpr _SizeConstant<_Offset::value + __j> __k;
+			return __xx[__k];
+		      });
+	     });
 #endif
   }
 
@@ -4144,8 +4152,9 @@ template <typename _Tp, typename... _As, typename = __detail::__odr_helper>
       return simd_cast<_Rp>(__xs...);
     else if ((... && __xs._M_is_constprop()))
       return simd<_Tp,
-		  simd_abi::deduce_t<_Tp, (simd_size_v<_Tp, _As> + ...)>>([&](
-	auto __i) constexpr { return __subscript_in_pack<__i>(__xs...); });
+		  simd_abi::deduce_t<_Tp, (simd_size_v<_Tp, _As> + ...)>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	       { return __subscript_in_pack<__i>(__xs...); });
     else
       {
 	_Rp __r{};
@@ -4161,9 +4170,10 @@ template <typename _Tp, typename _Abi, size_t _Np>
   _GLIBCXX_SIMD_CONSTEXPR __deduced_simd<_Tp, simd_size_v<_Tp, _Abi> * _Np>
   concat(const array<simd<_Tp, _Abi>, _Np>& __x)
   {
-    return __call_with_subscripts<_Np>(__x, [](const auto&... __xs) {
-      return concat(__xs...);
-    });
+    return __call_with_subscripts<_Np>(
+	     __x, [](const auto&... __xs) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	       return concat(__xs...);
+	     });
   }
 
 // }}}
@@ -4696,7 +4706,7 @@ template <typename _Tp, typename _Abi>
       simd_mask(_PrivateInit, _Fp&& __gen)
       : _M_data()
       {
-	__execute_n_times<size()>([&](auto __i) constexpr {
+	__execute_n_times<size()>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  _Impl::_S_set(_M_data, __i, __gen(__i));
 	});
       }
@@ -4882,7 +4892,9 @@ template <typename _Tp, typename _Abi>
     if (__builtin_is_constant_evaluated() || __k._M_is_constprop())
       {
 	const int __r = __call_with_subscripts<simd_size_v<_Tp, _Abi>>(
-	  __k, [](auto... __elements) { return ((__elements != 0) + ...); });
+			  __k, [](auto... __elements) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			    return ((__elements != 0) + ...);
+			  });
 	if (__builtin_is_constant_evaluated() || __builtin_constant_p(__r))
 	  return __r;
       }
@@ -4897,8 +4909,11 @@ template <typename _Tp, typename _Abi>
       {
 	constexpr size_t _Np = simd_size_v<_Tp, _Abi>;
 	const size_t _Idx = __call_with_n_evaluations<_Np>(
-	  [](auto... __indexes) { return std::min({__indexes...}); },
-	  [&](auto __i) { return __k[__i] ? +__i : _Np; });
+			      [](auto... __indexes) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				return std::min({__indexes...});
+			      }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				return __k[__i] ? +__i : _Np;
+			      });
 	if (_Idx >= _Np)
 	  __invoke_ub("find_first_set(empty mask) is UB");
 	if (__builtin_constant_p(_Idx))
@@ -4915,8 +4930,11 @@ template <typename _Tp, typename _Abi>
       {
 	constexpr size_t _Np = simd_size_v<_Tp, _Abi>;
 	const int _Idx = __call_with_n_evaluations<_Np>(
-	  [](auto... __indexes) { return std::max({__indexes...}); },
-	  [&](auto __i) { return __k[__i] ? int(__i) : -1; });
+			   [](auto... __indexes) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     return std::max({__indexes...});
+			   }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     return __k[__i] ? int(__i) : -1;
+			   });
 	if (_Idx < 0)
 	  __invoke_ub("find_first_set(empty mask) is UB");
 	if (__builtin_constant_p(_Idx))
diff --git a/libstdc++-v3/include/experimental/bits/simd_builtin.h b/libstdc++-v3/include/experimental/bits/simd_builtin.h
index 5901dee24b2..119e0deb2af 100644
--- a/libstdc++-v3/include/experimental/bits/simd_builtin.h
+++ b/libstdc++-v3/include/experimental/bits/simd_builtin.h
@@ -194,8 +194,11 @@ template <unsigned __shift, typename _Tp, typename _TVT = _VectorTraits<_Tp>>
 	using _Up = decltype(__w);
 	return __intrin_bitcast<_Tp>(
 	  __call_with_n_evaluations<(sizeof(_Tp) - __shift) / __chunksize>(
-	    [](auto... __chunks) { return _Up{__chunks...}; },
-	    [&](auto __i) { return __w[__shift / __chunksize + __i]; }));
+	    [](auto... __chunks) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return _Up{__chunks...};
+	    }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return __w[__shift / __chunksize + __i];
+	    }));
       }
   }
 
@@ -225,7 +228,9 @@ template <int _Index, int _Total, int _Combine, typename _Tp, size_t _Np>
 	// by _Total");
 	if (__x._M_is_constprop())
 	  return __generate_from_n_evaluations<__return_size, _R>(
-	    [&](auto __i) { return __x[__values_to_skip + __i]; });
+	    [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return __x[__values_to_skip + __i];
+	    });
 	if constexpr (_Index == 0 && _Total == 1)
 	  return __x;
 	else if constexpr (_Index == 0)
@@ -570,7 +575,9 @@ template <typename _To,
 	constexpr auto _Np
 	  = _NParts == 0 ? _FromVT::_S_partial_width - _Offset : _NParts;
 	return __generate_from_n_evaluations<_Np, array<_To, _Np>>(
-	  [&](auto __i) { return static_cast<_To>(__v[__i + _Offset]); });
+		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return static_cast<_To>(__v[__i + _Offset]);
+		 });
       }
     else
       {
@@ -611,13 +618,14 @@ template <typename _To,
 	      return __vector_bitcast<_FromT, decltype(__n)::value>(__vv);
 	    };
 	    [[maybe_unused]] const auto __vi = __to_intrin(__v);
-	    auto&& __make_array = [](auto __x0, [[maybe_unused]] auto __x1) {
-	      if constexpr (_Np == 1)
-		return _R{__intrin_bitcast<_To>(__x0)};
-	      else
-		return _R{__intrin_bitcast<_To>(__x0),
-			  __intrin_bitcast<_To>(__x1)};
-	    };
+	    auto&& __make_array
+		= [](auto __x0, [[maybe_unused]] auto __x1) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		  if constexpr (_Np == 1)
+		    return _R{__intrin_bitcast<_To>(__x0)};
+		  else
+		    return _R{__intrin_bitcast<_To>(__x0),
+			      __intrin_bitcast<_To>(__x1)};
+		};
 
 	    if constexpr (_Np == 0)
 	      return _R{};
@@ -642,7 +650,7 @@ template <typename _To,
 		      = __convert_all<__vector_type16_t<int>, _Np>(
 			__adjust(_SizeConstant<_Np * 4>(), __v));
 		    return __generate_from_n_evaluations<_Np, _R>(
-		      [&](auto __i) {
+		      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 			return __vector_convert<_To>(__as_wrapper(__ints[__i]));
 		      });
 		  }
@@ -687,36 +695,40 @@ template <typename _To,
 		  __vector_bitcast<int>(_mm_unpacklo_epi16(__vv[1], __vv[1])),
 		  __vector_bitcast<int>(_mm_unpackhi_epi16(__vv[1], __vv[1]))};
 		if constexpr (sizeof(_ToT) == 4)
-		  return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		    return __vector_convert<_To>(
-		      _SimdWrapper<int, 4>(__vvvv[__i] >> 24));
-		  });
+		  return __generate_from_n_evaluations<_Np, _R>(
+			   [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     return __vector_convert<_To>(
+				      _SimdWrapper<int, 4>(__vvvv[__i] >> 24));
+			   });
 		else if constexpr (is_integral_v<_ToT>)
-		  return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		    const auto __signbits = __to_intrin(__vvvv[__i / 2] >> 31);
-		    const auto __sx32 = __to_intrin(__vvvv[__i / 2] >> 24);
-		    return __vector_bitcast<_ToT>(
-		      __i % 2 == 0 ? _mm_unpacklo_epi32(__sx32, __signbits)
-				   : _mm_unpackhi_epi32(__sx32, __signbits));
-		  });
+		  return __generate_from_n_evaluations<_Np, _R>(
+			   [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     const auto __signbits = __to_intrin(__vvvv[__i / 2] >> 31);
+			     const auto __sx32 = __to_intrin(__vvvv[__i / 2] >> 24);
+			     return __vector_bitcast<_ToT>(
+				      __i % 2 == 0 ? _mm_unpacklo_epi32(__sx32, __signbits)
+						   : _mm_unpackhi_epi32(__sx32, __signbits));
+			   });
 		else
-		  return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		    const _SimdWrapper<int, 4> __int4 = __vvvv[__i / 2] >> 24;
-		    return __vector_convert<_To>(
-		      __i % 2 == 0 ? __int4
-				   : _SimdWrapper<int, 4>(
-				     _mm_unpackhi_epi64(__to_intrin(__int4),
-							__to_intrin(__int4))));
-		  });
+		  return __generate_from_n_evaluations<_Np, _R>(
+			   [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     const _SimdWrapper<int, 4> __int4 = __vvvv[__i / 2] >> 24;
+			     return __vector_convert<_To>(
+				      __i % 2 == 0 ? __int4
+						   : _SimdWrapper<int, 4>(
+						       _mm_unpackhi_epi64(__to_intrin(__int4),
+									  __to_intrin(__int4))));
+			   });
 	      }
 	    else if constexpr (sizeof(_FromT) == 1 && sizeof(_ToT) == 4)
 	      {
 		const auto __shorts = __convert_all<__vector_type16_t<
 		  conditional_t<is_signed_v<_FromT>, short, unsigned short>>>(
 		  __adjust(_SizeConstant<(_Np + 1) / 2 * 8>(), __v));
-		return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		  return __convert_all<_To>(__shorts[__i / 2])[__i % 2];
-		});
+		return __generate_from_n_evaluations<_Np, _R>(
+			 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			   return __convert_all<_To>(__shorts[__i / 2])[__i % 2];
+			 });
 	      }
 	    else if constexpr (sizeof(_FromT) == 2 && sizeof(_ToT) == 8
 			       && is_signed_v<_FromT> && is_integral_v<_ToT>)
@@ -736,9 +748,10 @@ template <typename _To,
 		     __vector_bitcast<int>(
 		       _mm_unpackhi_epi32(_mm_srai_epi32(__vv[1], 16),
 					  _mm_srai_epi32(__vv[1], 31)))};
-		return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		  return __vector_bitcast<_ToT>(__vvvv[__i]);
-		});
+		return __generate_from_n_evaluations<_Np, _R>(
+			 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			   return __vector_bitcast<_ToT>(__vvvv[__i]);
+			 });
 	      }
 	    else if constexpr (sizeof(_FromT) <= 2 && sizeof(_ToT) == 8)
 	      {
@@ -747,9 +760,10 @@ template <typename _To,
 		    is_signed_v<_FromT> || is_floating_point_v<_ToT>, int,
 		    unsigned int>>>(
 		    __adjust(_SizeConstant<(_Np + 1) / 2 * 4>(), __v));
-		return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		  return __convert_all<_To>(__ints[__i / 2])[__i % 2];
-		});
+		return __generate_from_n_evaluations<_Np, _R>(
+			 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			   return __convert_all<_To>(__ints[__i / 2])[__i % 2];
+			 });
 	      }
 	    else
 	      __assert_unreachable<_To>();
@@ -779,14 +793,14 @@ template <typename _To,
 		__extract_part<_Offset, _FromVT::_S_partial_width,
 			       _ToVT::_S_full_size>(__v))};
 	    else
-	      return __generate_from_n_evaluations<_Np, _R>([&](
-		auto __i) constexpr {
-		auto __part
-		  = __extract_part<__i * _ToVT::_S_full_size + _Offset,
-				   _FromVT::_S_partial_width,
-				   _ToVT::_S_full_size>(__v);
-		return __vector_convert<_To>(__part);
-	      });
+	      return __generate_from_n_evaluations<_Np, _R>(
+		       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			 auto __part
+			   = __extract_part<__i * _ToVT::_S_full_size + _Offset,
+					    _FromVT::_S_partial_width,
+					    _ToVT::_S_full_size>(__v);
+			 return __vector_convert<_To>(__part);
+		       });
 	  }
 	else if constexpr (_Offset == 0)
 	  return array<_To, 1>{__vector_convert<_To>(__v)};
@@ -1017,8 +1031,9 @@ template <int _UsedBytes>
 	else
 	  {
 	    constexpr auto __size = _S_size<_Tp>;
-	    _GLIBCXX_SIMD_USE_CONSTEXPR auto __r = __generate_vector<_UV>(
-	      [](auto __i) constexpr { return __i < __size ? -1 : 0; });
+	    _GLIBCXX_SIMD_USE_CONSTEXPR auto __r
+	      = __generate_vector<_UV>([](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+				       { return __i < __size ? -1 : 0; });
 	    return __r;
 	  }
       }
@@ -1208,7 +1223,7 @@ template <int _UsedBytes>
 	    if constexpr (is_integral_v<typename _TVT::value_type>)
 	      return __x
 		     | __generate_vector<_Tp, _S_full_size<_Tp>>(
-		       [](auto __i) -> _Tp {
+		       [](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Tp {
 			 if (__i < _Np)
 			   return 0;
 			 else
@@ -1348,26 +1363,27 @@ struct _CommonImplBuiltin
 	}
       else
 	{
-	  __execute_n_times<__div_roundup(_Np, 4)>([&](auto __i) {
-	    constexpr int __offset = __i * 4;
-	    constexpr int __remaining = _Np - __offset;
-	    if constexpr (__remaining > 4 && __remaining <= 7)
-	      {
-		const _ULLong __bool7
-		  = (__x.template _M_extract<__offset>()._M_to_bits()
-		     * 0x40810204081ULL)
-		    & 0x0101010101010101ULL;
-		_S_store<__remaining>(__bool7, __mem + __offset);
-	      }
-	    else if constexpr (__remaining >= 4)
-	      {
-		int __bits = __x.template _M_extract<__offset>()._M_to_bits();
-		if constexpr (__remaining > 7)
-		  __bits &= 0xf;
-		const int __bool4 = (__bits * 0x204081) & 0x01010101;
-		_S_store<4>(__bool4, __mem + __offset);
-	      }
-	  });
+	  __execute_n_times<__div_roundup(_Np, 4)>(
+	    [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      constexpr int __offset = __i * 4;
+	      constexpr int __remaining = _Np - __offset;
+	      if constexpr (__remaining > 4 && __remaining <= 7)
+		{
+		  const _ULLong __bool7
+		    = (__x.template _M_extract<__offset>()._M_to_bits()
+			 * 0x40810204081ULL)
+			& 0x0101010101010101ULL;
+		  _S_store<__remaining>(__bool7, __mem + __offset);
+		}
+	      else if constexpr (__remaining >= 4)
+		{
+		  int __bits = __x.template _M_extract<__offset>()._M_to_bits();
+		  if constexpr (__remaining > 7)
+		    __bits &= 0xf;
+		  const int __bool4 = (__bits * 0x204081) & 0x01010101;
+		  _S_store<4>(__bool4, __mem + __offset);
+		}
+	    });
 	}
     }
 
@@ -1434,13 +1450,13 @@ template <typename _Abi, typename>
       inline static constexpr _SimdMember<_Tp> _S_generator(_Fp&& __gen,
 							    _TypeTag<_Tp>)
       {
-	return __generate_vector<_Tp, _S_full_size<_Tp>>([&](
-	  auto __i) constexpr {
-	  if constexpr (__i < _S_size<_Tp>)
-	    return __gen(__i);
-	  else
-	    return 0;
-	});
+	return __generate_vector<_Tp, _S_full_size<_Tp>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   if constexpr (__i < _S_size<_Tp>)
+		     return __gen(__i);
+		   else
+		     return 0;
+		 });
       }
 
     // _S_load {{{2
@@ -1455,10 +1471,10 @@ template <typename _Abi, typename>
 								      : 16;
 	constexpr size_t __bytes_to_load = sizeof(_Up) * _Np;
 	if constexpr (sizeof(_Up) > 8)
-	  return __generate_vector<_Tp, _SimdMember<_Tp>::_S_full_size>([&](
-	    auto __i) constexpr {
-	    return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0);
-	  });
+	  return __generate_vector<_Tp, _SimdMember<_Tp>::_S_full_size>(
+		   [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		     return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0);
+		   });
 	else if constexpr (is_same_v<_Up, _Tp>)
 	  return _CommonImpl::template _S_load<_Tp, _S_full_size<_Tp>,
 					       _Np * sizeof(_Tp)>(__mem);
@@ -1470,13 +1486,12 @@ template <typename _Abi, typename>
 	    constexpr size_t __n_loads = __bytes_to_load / __max_load_size;
 	    constexpr size_t __elements_per_load = _Np / __n_loads;
 	    return __call_with_n_evaluations<__n_loads>(
-	      [](auto... __uncvted) {
-		return __convert<_SimdMember<_Tp>>(__uncvted...);
-	      },
-	      [&](auto __i) {
-		return _CommonImpl::template _S_load<_Up, __elements_per_load>(
-		  __mem + __i * __elements_per_load);
-	      });
+		     [](auto... __uncvted) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return __convert<_SimdMember<_Tp>>(__uncvted...);
+		     }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return _CommonImpl::template _S_load<_Up, __elements_per_load>(
+						      __mem + __i * __elements_per_load);
+		     });
 	  }
 	else if constexpr (__bytes_to_load % (__max_load_size / 2) == 0
 			   && __max_load_size > 16)
@@ -1485,20 +1500,19 @@ template <typename _Abi, typename>
 	      = __bytes_to_load / (__max_load_size / 2);
 	    constexpr size_t __elements_per_load = _Np / __n_loads;
 	    return __call_with_n_evaluations<__n_loads>(
-	      [](auto... __uncvted) {
-		return __convert<_SimdMember<_Tp>>(__uncvted...);
-	      },
-	      [&](auto __i) {
-		return _CommonImpl::template _S_load<_Up, __elements_per_load>(
-		  __mem + __i * __elements_per_load);
-	      });
+		     [](auto... __uncvted) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return __convert<_SimdMember<_Tp>>(__uncvted...);
+		     }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return _CommonImpl::template _S_load<_Up, __elements_per_load>(
+						      __mem + __i * __elements_per_load);
+		     });
 	  }
 	else // e.g. int[] -> <char, 9>
 	  return __call_with_subscripts(
-	    __mem, make_index_sequence<_Np>(), [](auto... __args) {
-	      return __vector_type_t<_Tp, _S_full_size<_Tp>>{
-		static_cast<_Tp>(__args)...};
-	    });
+	    __mem, make_index_sequence<_Np>(),
+		   [](auto... __args) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		     return __vector_type_t<_Tp, _S_full_size<_Tp>>{static_cast<_Tp>(__args)...};
+		   });
       }
 
     // _S_masked_load {{{2
@@ -1507,9 +1521,10 @@ template <typename _Abi, typename>
       _S_masked_load(_SimdWrapper<_Tp, _Np> __merge, _MaskMember<_Tp> __k,
 		     const _Up* __mem) noexcept
       {
-	_BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k), [&](auto __i) {
-	  __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
-	});
+	_BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k),
+				  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				    __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
+				  });
 	return __merge;
       }
 
@@ -1523,7 +1538,7 @@ template <typename _Abi, typename>
 	constexpr size_t __max_store_size
 	  = _SuperImpl::template _S_max_store_size<_Up>;
 	if constexpr (sizeof(_Up) > 8)
-	  __execute_n_times<_Np>([&](auto __i) constexpr {
+	  __execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __mem[__i] = __v[__i];
 	  });
 	else if constexpr (is_same_v<_Up, _Tp>)
@@ -1540,9 +1555,10 @@ template <typename _Abi, typename>
 	    using _V = __vector_type_t<_Up, __vsize>;
 	    const array<_V, __stores> __converted
 	      = __convert_all<_V, __stores>(__v);
-	    __execute_n_times<__full_stores>([&](auto __i) constexpr {
-	      _CommonImpl::_S_store(__converted[__i], __mem + __i * __vsize);
-	    });
+	    __execute_n_times<__full_stores>(
+	      [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		_CommonImpl::_S_store(__converted[__i], __mem + __i * __vsize);
+	      });
 	    if constexpr (__full_stores < __stores)
 	      _CommonImpl::template _S_store<(_Np - __full_stores * __vsize)
 					     * sizeof(_Up)>(
@@ -1557,7 +1573,8 @@ template <typename _Abi, typename>
 			    _MaskMember<_Tp> __k)
       {
 	_BitOps::_S_bit_iteration(
-	  _MaskImpl::_S_to_bits(__k), [&](auto __i) constexpr {
+	  _MaskImpl::_S_to_bits(__k),
+	  [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __mem[__i] = __v[__i];
 	  });
       }
@@ -1579,7 +1596,7 @@ template <typename _Abi, typename>
 	    _Up> || (is_integral_v<_Tp> && is_integral_v<_Up> && sizeof(_Tp) == sizeof(_Up)))
 	  {
 	    // bitwise or no conversion, reinterpret:
-	    const _MaskMember<_Up> __kk = [&]() {
+	    const _MaskMember<_Up> __kk = [&]() _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	      if constexpr (__is_bitmask_v<decltype(__k)>)
 		return _MaskMember<_Up>(__k._M_data);
 	      else
@@ -1618,7 +1635,7 @@ template <typename _Abi, typename>
 		constexpr size_t _NParts = _S_full_size<_Tp> / _UW_size;
 		const array<_UV, _NAllStores> __converted
 		  = __convert_all<_UV, _NAllStores>(__v);
-		__execute_n_times<_NFullStores>([&](auto __i) {
+		__execute_n_times<_NFullStores>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  _SuperImpl::_S_masked_store_nocvt(
 		    _UW(__converted[__i]), __mem + __i * _UW_size,
 		    _UAbi::_MaskImpl::template _S_convert<
@@ -1637,10 +1654,10 @@ template <typename _Abi, typename>
 	      }
 	  }
 	else
-	  _BitOps::_S_bit_iteration(
-	    _MaskImpl::_S_to_bits(__k), [&](auto __i) constexpr {
-	      __mem[__i] = static_cast<_Up>(__v[__i]);
-	    });
+	  _BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k),
+				    [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				      __mem[__i] = static_cast<_Up>(__v[__i]);
+				    });
       }
 
     // _S_complement {{{2
@@ -1932,7 +1949,9 @@ template <typename _Abi, typename>
       static _Tp _S_##__name(const _Tp& __x, const _More&... __more)           \
       {                                                                        \
 	return __generate_vector<_Tp>(                                         \
-	  [&](auto __i) { return __name(__x[__i], __more[__i]...); });         \
+		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {            \
+		   return __name(__x[__i], __more[__i]...);                    \
+		 });                                                           \
       }
 
 #define _GLIBCXX_SIMD_MATH_FALLBACK_MASKRET(__name)                            \
@@ -1941,23 +1960,25 @@ template <typename _Abi, typename>
 						 const _More&... __more)       \
       {                                                                        \
 	return __generate_vector<_Tp>(                                         \
-	  [&](auto __i) { return __name(__x[__i], __more[__i]...); });         \
-      }
-
-#define _GLIBCXX_SIMD_MATH_FALLBACK_FIXEDRET(_RetTp, __name)                   \
-    template <typename _Tp, typename... _More>                                 \
-      static auto _S_##__name(const _Tp& __x, const _More&... __more)          \
-      {                                                                        \
-	return __fixed_size_storage_t<_RetTp,                                  \
-				      _VectorTraits<_Tp>::_S_partial_width>::  \
-	  _S_generate([&](auto __meta) constexpr {                             \
-	    return __meta._S_generator(                                        \
-	      [&](auto __i) {                                                  \
-		return __name(__x[__meta._S_offset + __i],                     \
-			      __more[__meta._S_offset + __i]...);              \
-	      },                                                               \
-	      static_cast<_RetTp*>(nullptr));                                  \
-	  });                                                                  \
+		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {            \
+		   return __name(__x[__i], __more[__i]...);                    \
+		 });                                                           \
+      }
+
+#define _GLIBCXX_SIMD_MATH_FALLBACK_FIXEDRET(_RetTp, __name)                          \
+    template <typename _Tp, typename... _More>                                        \
+      static auto _S_##__name(const _Tp& __x, const _More&... __more)                 \
+      {                                                                               \
+	return __fixed_size_storage_t<_RetTp,                                         \
+				      _VectorTraits<_Tp>::_S_partial_width>::         \
+	  _S_generate([&](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { \
+	    return __meta._S_generator(                                               \
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {                      \
+		return __name(__x[__meta._S_offset + __i],                            \
+			      __more[__meta._S_offset + __i]...);                     \
+	      },                                                                      \
+	      static_cast<_RetTp*>(nullptr));                                         \
+	  });                                                                         \
       }
 
     _GLIBCXX_SIMD_MATH_FALLBACK(acos)
@@ -2010,7 +2031,7 @@ template <typename _Abi, typename>
       _S_remquo(const _Tp __x, const _Tp __y,
 		__fixed_size_storage_t<int, _TVT::_S_partial_width>* __z)
       {
-	return __generate_vector<_Tp>([&](auto __i) {
+	return __generate_vector<_Tp>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  int __tmp;
 	  auto __r = remquo(__x[__i], __y[__i], &__tmp);
 	  __z->_M_set(__i, __tmp);
@@ -2423,7 +2444,7 @@ template <typename _Abi, typename>
   #endif // _GLIBCXX_SIMD_X86INTRIN
       else if constexpr (__fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
 	return {__call_with_subscripts<_Np>(__vector_bitcast<_LLong>(__tmp),
-					    [](auto... __l) {
+					    [](auto... __l) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 					      return __make_wrapper<int>(__l...);
 					    })};
       else
@@ -2554,13 +2575,13 @@ struct _MaskImplBuiltinMixin
     _S_to_maskvector(_BitMask<_Np, _Sanitized> __x)
     {
       static_assert(is_same_v<_Up, __int_for_sizeof_t<_Up>>);
-      return __generate_vector<__vector_type_t<_Up, _ToN>>([&](
-	auto __i) constexpr {
-	if constexpr (__i < _Np)
-	  return __x[__i] ? ~_Up() : _Up();
-	else
-	  return _Up();
-      });
+      return __generate_vector<__vector_type_t<_Up, _ToN>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 if constexpr (__i < _Np)
+		   return __x[__i] ? ~_Up() : _Up();
+		 else
+		   return _Up();
+	       });
     }
 
   template <typename _Up, size_t _UpN = 0, typename _Tp, size_t _Np,
@@ -2601,13 +2622,13 @@ struct _MaskImplBuiltinMixin
 	  -1, -1, -1, -1, -1>(__y); else
 	  */
 	  {
-	    return __generate_vector<__vector_type_t<_Up, _ToN>>([&](
-	      auto __i) constexpr {
-	      if constexpr (__i < _Np)
-		return _Up(__x[__i.value]);
-	      else
-		return _Up();
-	    });
+	    return __generate_vector<__vector_type_t<_Up, _ToN>>(
+		     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       if constexpr (__i < _Np)
+			 return _Up(__x[__i.value]);
+		       else
+			 return _Up();
+		     });
 	  }
 	}
     }
@@ -2625,7 +2646,9 @@ struct _MaskImplBuiltinMixin
 	= __vector_bitcast<_Up>(__x) >> (sizeof(_Up) * __CHAR_BIT__ - 1);
       _ULLong __r = 0;
       __execute_n_times<_Np>(
-	[&](auto __i) { __r |= _ULLong(__bools[__i.value]) << __i; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	  __r |= _ULLong(__bools[__i.value]) << __i;
+	});
       return __r;
     }
 
@@ -2677,9 +2700,10 @@ template <typename _Abi, typename>
 	    return __bools > 0;
 	  }
 	else
-	  return __generate_vector<_I, _S_size<_Tp>>([&](auto __i) constexpr {
-	    return __mem[__i] ? ~_I() : _I();
-	  });
+	  return __generate_vector<_I, _S_size<_Tp>>(
+		   [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		     return __mem[__i] ? ~_I() : _I();
+		   });
       }
 
     // }}}
@@ -2752,7 +2776,7 @@ template <typename _Abi, typename>
 	// AVX(2) has 32/64 bit maskload, but nothing at 8 bit granularity
 	auto __tmp = __wrapper_bitcast<__int_for_sizeof_t<_Tp>>(__merge);
 	_BitOps::_S_bit_iteration(_SuperImpl::_S_to_bits(__mask),
-				  [&](auto __i) {
+				  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 				    __tmp._M_set(__i, -__mem[__i]);
 				  });
 	__merge = __wrapper_bitcast<_Tp>(__tmp);
@@ -2764,7 +2788,7 @@ template <typename _Abi, typename>
       _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __v,
 						   bool* __mem) noexcept
       {
-	__execute_n_times<_Np>([&](auto __i) constexpr {
+	__execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  __mem[__i] = __v[__i];
 	});
       }
@@ -2775,10 +2799,10 @@ template <typename _Abi, typename>
       _S_masked_store(const _SimdWrapper<_Tp, _Np> __v, bool* __mem,
 		      const _SimdWrapper<_Tp, _Np> __k) noexcept
       {
-	_BitOps::_S_bit_iteration(
-	  _SuperImpl::_S_to_bits(__k), [&](auto __i) constexpr {
-	    __mem[__i] = __v[__i];
-	  });
+	_BitOps::_S_bit_iteration(_SuperImpl::_S_to_bits(__k),
+				  [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				    __mem[__i] = __v[__i];
+				  });
       }
 
     // _S_from_bitmask{{{2
@@ -2845,7 +2869,7 @@ template <typename _Abi, typename>
 	      {
 		__k = __generate_from_n_evaluations<_Np,
 						    __vector_type_t<_Tp, _Np>>(
-		  [&](auto __j) {
+		  [&](auto __j) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    if (__i == static_cast<int>(__j))
 		      return _Tp(-__x);
 		    else
@@ -2890,7 +2914,8 @@ template <typename _Abi, typename>
       {
 	return __call_with_subscripts(
 	  __data(__k), make_index_sequence<_S_size<_Tp>>(),
-	  [](const auto... __ent) constexpr { return (... && !(__ent == 0)); });
+	  [](const auto... __ent) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	  { return (... && !(__ent == 0)); });
       }
 
     // }}}
@@ -2901,7 +2926,8 @@ template <typename _Abi, typename>
       {
 	return __call_with_subscripts(
 	  __data(__k), make_index_sequence<_S_size<_Tp>>(),
-	  [](const auto... __ent) constexpr { return (... || !(__ent == 0)); });
+	  [](const auto... __ent) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	  { return (... || !(__ent == 0)); });
       }
 
     // }}}
@@ -2912,7 +2938,8 @@ template <typename _Abi, typename>
       {
 	return __call_with_subscripts(
 	  __data(__k), make_index_sequence<_S_size<_Tp>>(),
-	  [](const auto... __ent) constexpr { return (... && (__ent == 0)); });
+	  [](const auto... __ent) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	  { return (... && (__ent == 0)); });
       }
 
     // }}}
diff --git a/libstdc++-v3/include/experimental/bits/simd_converter.h b/libstdc++-v3/include/experimental/bits/simd_converter.h
index f6e8569a1c9..cfca421cd6f 100644
--- a/libstdc++-v3/include/experimental/bits/simd_converter.h
+++ b/libstdc++-v3/include/experimental/bits/simd_converter.h
@@ -121,7 +121,7 @@ template <typename _From, typename _To, int _Np>
 	{
 	  return __call_with_subscripts(
 	    __x, make_index_sequence<_Np>(),
-	    [](auto... __values) constexpr->_Ret {
+	    [](auto... __values) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Ret {
 	      return __make_simd_tuple<_To, decltype((void) __values,
 						     simd_abi::scalar())...>(
 		static_cast<_To>(__values)...);
@@ -233,7 +233,9 @@ template <typename _From, typename _To, int _Np>
 	  static_assert(_Ret::_FirstAbi::template _S_is_partial<_To>);
 	  return _Ret{__generate_from_n_evaluations<
 	    _Np, typename _VectorTraits<typename _Ret::_FirstType>::type>(
-	    [&](auto __i) { return static_cast<_To>(__x[__i]); })};
+	    [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return static_cast<_To>(__x[__i]);
+	    })};
 	}
       else
 	{
@@ -241,7 +243,7 @@ template <typename _From, typename _To, int _Np>
 	  constexpr auto __n
 	    = __div_roundup(_Ret::_S_first_size, _Arg::_S_first_size);
 	  return __call_with_n_evaluations<__n>(
-	    [&__x](auto... __uncvted) {
+	    [&__x](auto... __uncvted) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	      // assuming _Arg Abi tags for all __i are _Arg::_FirstAbi
 	      _SimdConverter<_From, typename _Arg::_FirstAbi, _To,
 			     typename _Ret::_FirstAbi>
@@ -255,8 +257,9 @@ template <typename _From, typename _To, int _Np>
 		    _From, simd_abi::fixed_size<_Np - _Ret::_S_first_size>, _To,
 		    simd_abi::fixed_size<_Np - _Ret::_S_first_size>>()(
 		    __simd_tuple_pop_front<_Ret::_S_first_size>(__x))};
-	    },
-	    [&__x](auto __i) { return __get_tuple_at<__i>(__x); });
+	    }, [&__x](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return __get_tuple_at<__i>(__x);
+	    });
 	}
     }
   };
@@ -322,13 +325,14 @@ template <typename _From, int _Np, typename _To, typename _Ap>
 	return __vector_convert<__vector_type_t<_To, _Np>>(__x.first);
       else if constexpr (_Arg::_S_is_homogeneous)
 	return __call_with_n_evaluations<_Arg::_S_tuple_size>(
-	  [](auto... __members) {
+	  [](auto... __members) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    if constexpr ((is_convertible_v<decltype(__members), _To> && ...))
 	      return __vector_type_t<_To, _Np>{static_cast<_To>(__members)...};
 	    else
 	      return __vector_convert<__vector_type_t<_To, _Np>>(__members...);
-	  },
-	  [&](auto __i) { return __get_tuple_at<__i>(__x); });
+	  }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	    return __get_tuple_at<__i>(__x);
+	  });
       else if constexpr (__fixed_size_storage_t<_To, _Np>::_S_tuple_size == 1)
 	{
 	  _SimdConverter<_From, simd_abi::fixed_size<_Np>, _To,
@@ -340,7 +344,7 @@ template <typename _From, int _Np, typename _To, typename _Ap>
 	{
 	  const _SimdWrapper<_From, _Np> __xv
 	    = __generate_from_n_evaluations<_Np, __vector_type_t<_From, _Np>>(
-	      [&](auto __i) { return __x[__i]; });
+		[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
 	  return __vector_convert<__vector_type_t<_To, _Np>>(__xv);
 	}
     }
diff --git a/libstdc++-v3/include/experimental/bits/simd_detail.h b/libstdc++-v3/include/experimental/bits/simd_detail.h
index de8d018c515..bd4e380df65 100644
--- a/libstdc++-v3/include/experimental/bits/simd_detail.h
+++ b/libstdc++-v3/include/experimental/bits/simd_detail.h
@@ -262,6 +262,7 @@
 #define _GLIBCXX_SIMD_INTRINSIC                                                \
   [[__gnu__::__always_inline__, __gnu__::__artificial__]] inline
 #define _GLIBCXX_SIMD_ALWAYS_INLINE [[__gnu__::__always_inline__]] inline
+#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA __attribute__((__always_inline__))
 #define _GLIBCXX_SIMD_IS_UNLIKELY(__x) __builtin_expect(__x, 0)
 #define _GLIBCXX_SIMD_IS_LIKELY(__x) __builtin_expect(__x, 1)
 
@@ -294,6 +295,8 @@
 #ifdef _GLIBCXX_SIMD_NO_ALWAYS_INLINE
 #undef _GLIBCXX_SIMD_ALWAYS_INLINE
 #define _GLIBCXX_SIMD_ALWAYS_INLINE inline
+#undef _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
 #undef _GLIBCXX_SIMD_INTRINSIC
 #define _GLIBCXX_SIMD_INTRINSIC inline
 #endif
diff --git a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
index 7bb248cf9d0..eb71a7b6295 100644
--- a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
+++ b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
@@ -434,14 +434,15 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	if constexpr (is_same_v<_SimdTuple, __remove_cvref_t<_Tup>>)
 	  return __tup.first;
 	else if (__builtin_is_constant_evaluated())
-	  return __fixed_size_storage_t<_TupT, _S_first_size>::_S_generate([&](
-	    auto __meta) constexpr {
-	    return __meta._S_generator(
-	      [&](auto __i) constexpr { return __tup[__i]; },
-	      static_cast<_TupT*>(nullptr));
+	  return __fixed_size_storage_t<_TupT, _S_first_size>::_S_generate(
+		   [&](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		     return __meta._S_generator(
+			      [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				return __tup[__i];
+			      }, static_cast<_TupT*>(nullptr));
 	  });
 	else
-	  return [&]() {
+	  return [&]() { // not always_inline; allow the compiler to decide
 	    __fixed_size_storage_t<_TupT, _S_first_size> __r;
 	    __builtin_memcpy(__r._M_as_charptr(), __tup._M_as_charptr(),
 			     sizeof(__r));
@@ -515,12 +516,11 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 			 negation<is_const<remove_reference_t<_More>>>>) )
 	  {
 	    // need to write back at least one of __more after calling __fun
-	    auto&& __first = [&](auto... __args) constexpr
-	    {
+	    auto&& __first = [&](auto... __args) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	      auto __r = __fun(__tuple_element_meta<_Tp, _Abi0, 0>(), first,
 			       __args...);
 	      [[maybe_unused]] auto&& __ignore_me = {(
-		[](auto&& __dst, const auto& __src) {
+		[](auto&& __dst, const auto& __src) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  if constexpr (is_assignable_v<decltype(__dst),
 						decltype(__dst)>)
 		    {
@@ -530,8 +530,7 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 		}(static_cast<_More&&>(__more), __args),
 		0)...};
 	      return __r;
-	    }
-	    (_M_extract_argument(__more)...);
+	    }(_M_extract_argument(__more)...);
 	    if constexpr (_S_tuple_size == 1)
 	      return {__first};
 	    else
@@ -776,18 +775,18 @@ template <typename _Tp, size_t _Np, typename _V, size_t _NV, typename... _VX>
 	  sizeof...(_VX) == 0,
 	  "An array of scalars must be the last argument to __to_simd_tuple");
 	return __call_with_subscripts(
-	  __from,
-	  make_index_sequence<_NV>(), [&](const auto... __args) constexpr {
-	    return __simd_tuple_concat(
-	      _SimdTuple<_Tp, simd_abi::scalar>{__args}..., _SimdTuple<_Tp>());
-	  });
+		 __from, make_index_sequence<_NV>(),
+		 [&](const auto... __args) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __simd_tuple_concat(
+			    _SimdTuple<_Tp, simd_abi::scalar>{__args}..., _SimdTuple<_Tp>());
+		 });
       }
     else
       return __call_with_subscripts(
-	__from,
-	make_index_sequence<_NV>(), [&](const auto... __args) constexpr {
-	  return __to_simd_tuple<_Tp, _Np>(__args..., __fromX...);
-	});
+	       __from, make_index_sequence<_NV>(),
+	       [&](const auto... __args) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 return __to_simd_tuple<_Tp, _Np>(__args..., __fromX...);
+	       });
   }
 
 template <size_t, typename _Tp>
@@ -841,7 +840,7 @@ template <typename _Tp, typename _A0, typename _A1, typename... _Abis,
 		       || _A0::template _S_is_partial<_Tp>)
       return {__generate_from_n_evaluations<_R::_S_first_size,
 					    typename _R::_FirstType>(
-		[&](auto __i) { return __x[__i]; }),
+		[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }),
 	      __optimize_simd_tuple(
 		__simd_tuple_pop_front<_R::_S_first_size>(__x))};
     else if constexpr (is_same_v<_A0, _A1>
@@ -994,10 +993,11 @@ template <int _Index, int _Total, int _Combine, typename _Tp, typename _A0,
 	return __as_vector(simd<_Tp, _RetAbi>(element_ptr, element_aligned));
 #else
 	[[maybe_unused]] constexpr size_t __offset = __values_to_skip;
-	return __as_vector(simd<_Tp, _RetAbi>([&](auto __i) constexpr {
-	  constexpr _SizeConstant<__i + __offset> __k;
-	  return __x[__k];
-	}));
+	return __as_vector(simd<_Tp, _RetAbi>(
+			     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			       constexpr _SizeConstant<__i + __offset> __k;
+			       return __x[__k];
+			     }));
 #endif
       }
 
@@ -1286,9 +1286,10 @@ template <int _Np, typename>
     template <typename _Tp>
       static constexpr inline _SimdMember<_Tp> _S_broadcast(_Tp __x) noexcept
       {
-	return _SimdMember<_Tp>::_S_generate([&](auto __meta) constexpr {
-	  return __meta._S_broadcast(__x);
-	});
+	return _SimdMember<_Tp>::_S_generate(
+		 [&](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __meta._S_broadcast(__x);
+		 });
       }
 
     // _S_generator {{{2
@@ -1296,14 +1297,15 @@ template <int _Np, typename>
       static constexpr inline _SimdMember<_Tp> _S_generator(_Fp&& __gen,
 							    _TypeTag<_Tp>)
       {
-	return _SimdMember<_Tp>::_S_generate([&__gen](auto __meta) constexpr {
-	  return __meta._S_generator(
-	    [&](auto __i) constexpr {
-	      return __i < _Np ? __gen(_SizeConstant<__meta._S_offset + __i>())
-			       : 0;
-	    },
-	    _TypeTag<_Tp>());
-	});
+	return _SimdMember<_Tp>::_S_generate(
+		 [&__gen](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __meta._S_generator(
+			    [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			      return __i < _Np ? __gen(_SizeConstant<__meta._S_offset + __i>())
+					       : 0;
+			    },
+			    _TypeTag<_Tp>());
+		 });
       }
 
     // _S_load {{{2
@@ -1311,9 +1313,10 @@ template <int _Np, typename>
       static inline _SimdMember<_Tp> _S_load(const _Up* __mem,
 					     _TypeTag<_Tp>) noexcept
       {
-	return _SimdMember<_Tp>::_S_generate([&](auto __meta) {
-	  return __meta._S_load(&__mem[__meta._S_offset], _TypeTag<_Tp>());
-	});
+	return _SimdMember<_Tp>::_S_generate(
+		 [&](auto __meta) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __meta._S_load(&__mem[__meta._S_offset], _TypeTag<_Tp>());
+		 });
       }
 
     // _S_masked_load {{{2
@@ -1323,7 +1326,7 @@ template <int _Np, typename>
 		     const _MaskMember __bits, const _Up* __mem) noexcept
       {
 	auto __merge = __old;
-	__for_each(__merge, [&](auto __meta, auto& __native) {
+	__for_each(__merge, [&](auto __meta, auto& __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__meta._S_submask(__bits).any())
 #pragma GCC diagnostic push
 	  // __mem + __mem._S_offset could be UB ([expr.add]/4.3, but it punts
@@ -1344,7 +1347,7 @@ template <int _Np, typename>
       static inline void _S_store(const _SimdMember<_Tp>& __v, _Up* __mem,
 				  _TypeTag<_Tp>) noexcept
       {
-	__for_each(__v, [&](auto __meta, auto __native) {
+	__for_each(__v, [&](auto __meta, auto __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  __meta._S_store(__native, &__mem[__meta._S_offset], _TypeTag<_Tp>());
 	});
       }
@@ -1355,7 +1358,7 @@ template <int _Np, typename>
 					 _Up* __mem,
 					 const _MaskMember __bits) noexcept
       {
-	__for_each(__v, [&](auto __meta, auto __native) {
+	__for_each(__v, [&](auto __meta, auto __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__meta._S_submask(__bits).any())
 #pragma GCC diagnostic push
 	  // __mem + __mem._S_offset could be UB ([expr.add]/4.3, but it punts
@@ -1376,7 +1379,7 @@ template <int _Np, typename>
       {
 	_MaskMember __bits = 0;
 	__for_each(
-	  __x, [&__bits](auto __meta, auto __native) constexpr {
+	  __x, [&__bits](auto __meta, auto __native) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __bits
 	      |= __meta._S_mask_to_shifted_ullong(__meta._S_negate(__native));
 	  });
@@ -1414,7 +1417,7 @@ template <int _Np, typename>
 	  {
 	    const auto& __x2 = __call_with_n_evaluations<
 	      __div_roundup(_Tup::_S_tuple_size, 2)>(
-	      [](auto __first_simd, auto... __remaining) {
+	      [](auto __first_simd, auto... __remaining) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		if constexpr (sizeof...(__remaining) == 0)
 		  return __first_simd;
 		else
@@ -1428,7 +1431,7 @@ template <int _Np, typename>
 		      __make_simd_tuple(__first_simd, __remaining...));
 		  }
 	      },
-	      [&](auto __i) {
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		auto __left = __tup.template _M_simd_at<2 * __i>();
 		if constexpr (2 * __i + 1 == _Tup::_S_tuple_size)
 		  return __left;
@@ -1444,7 +1447,9 @@ template <int _Np, typename>
 			_GLIBCXX_SIMD_USE_CONSTEXPR_API
 			typename _LT::mask_type __k(
 			  __private_init,
-			  [](auto __j) constexpr { return __j < _RT::size(); });
+			  [](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			    return __j < _RT::size();
+			  });
 			_LT __ext_right = __left;
 			where(__k, __ext_right)
 			  = __proposed::resizing_simd_cast<_LT>(__right);
@@ -1464,7 +1469,7 @@ template <int _Np, typename>
 	     const _SimdTuple<_Tp, _As...>& __b)
       {
 	return __a._M_apply_per_chunk(
-	  [](auto __impl, auto __aa, auto __bb) constexpr {
+	  [](auto __impl, auto __aa, auto __bb) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    return __impl._S_min(__aa, __bb);
 	  },
 	  __b);
@@ -1476,7 +1481,7 @@ template <int _Np, typename>
 	     const _SimdTuple<_Tp, _As...>& __b)
       {
 	return __a._M_apply_per_chunk(
-	  [](auto __impl, auto __aa, auto __bb) constexpr {
+	  [](auto __impl, auto __aa, auto __bb) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    return __impl._S_max(__aa, __bb);
 	  },
 	  __b);
@@ -1487,9 +1492,10 @@ template <int _Np, typename>
       static inline constexpr _SimdTuple<_Tp, _As...>
       _S_complement(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
-	return __x._M_apply_per_chunk([](auto __impl, auto __xx) constexpr {
-	  return __impl._S_complement(__xx);
-	});
+	return __x._M_apply_per_chunk(
+		 [](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_complement(__xx);
+		 });
       }
 
     // _S_unary_minus {{{2
@@ -1497,23 +1503,24 @@ template <int _Np, typename>
       static inline constexpr _SimdTuple<_Tp, _As...>
       _S_unary_minus(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
-	return __x._M_apply_per_chunk([](auto __impl, auto __xx) constexpr {
-	  return __impl._S_unary_minus(__xx);
-	});
+	return __x._M_apply_per_chunk(
+		 [](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_unary_minus(__xx);
+		 });
       }
 
     // arithmetic operators {{{2
 
-#define _GLIBCXX_SIMD_FIXED_OP(name_, op_)                                     \
-    template <typename _Tp, typename... _As>                                   \
-      static inline constexpr _SimdTuple<_Tp, _As...> name_(                   \
-	const _SimdTuple<_Tp, _As...>& __x, const _SimdTuple<_Tp, _As...>& __y)\
-      {                                                                        \
-	return __x._M_apply_per_chunk(                                         \
-	  [](auto __impl, auto __xx, auto __yy) constexpr {                    \
-	    return __impl.name_(__xx, __yy);                                   \
-	  },                                                                   \
-	  __y);                                                                \
+#define _GLIBCXX_SIMD_FIXED_OP(name_, op_)                                                     \
+    template <typename _Tp, typename... _As>                                                   \
+      static inline constexpr _SimdTuple<_Tp, _As...> name_(                                   \
+	const _SimdTuple<_Tp, _As...>& __x, const _SimdTuple<_Tp, _As...>& __y)                \
+      {                                                                                        \
+	return __x._M_apply_per_chunk(                                                         \
+	  [](auto __impl, auto __xx, auto __yy) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { \
+	    return __impl.name_(__xx, __yy);                                                   \
+	  },                                                                                   \
+	  __y);                                                                                \
       }
 
     _GLIBCXX_SIMD_FIXED_OP(_S_plus, +)
@@ -1532,18 +1539,20 @@ template <int _Np, typename>
       static inline constexpr _SimdTuple<_Tp, _As...>
       _S_bit_shift_left(const _SimdTuple<_Tp, _As...>& __x, int __y)
       {
-	return __x._M_apply_per_chunk([__y](auto __impl, auto __xx) constexpr {
-	  return __impl._S_bit_shift_left(__xx, __y);
-	});
+	return __x._M_apply_per_chunk(
+		 [__y](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_bit_shift_left(__xx, __y);
+		 });
       }
 
     template <typename _Tp, typename... _As>
       static inline constexpr _SimdTuple<_Tp, _As...>
       _S_bit_shift_right(const _SimdTuple<_Tp, _As...>& __x, int __y)
       {
-	return __x._M_apply_per_chunk([__y](auto __impl, auto __xx) constexpr {
-	  return __impl._S_bit_shift_right(__xx, __y);
-	});
+	return __x._M_apply_per_chunk(
+		 [__y](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_bit_shift_right(__xx, __y);
+		 });
       }
 
   // math {{{2
@@ -1557,35 +1566,40 @@ template <int _Np, typename>
 	  {                                                                    \
 	    if constexpr (is_same_v<_Tp, _RetTp>)                              \
 	      return __x._M_apply_per_chunk(                                   \
-		[](auto __impl, auto __xx) constexpr {                         \
-		  using _V = typename decltype(__impl)::simd_type;             \
-		  return __data(__name(_V(__private_init, __xx)));             \
-		});                                                            \
+		       [](auto __impl, auto __xx)                              \
+			 constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA          \
+		       {                                                       \
+			 using _V = typename decltype(__impl)::simd_type;      \
+			 return __data(__name(_V(__private_init, __xx)));      \
+		       });                                                     \
 	    else                                                               \
 	      return __optimize_simd_tuple(                                    \
-		__x.template _M_apply_r<_RetTp>([](auto __impl, auto __xx) {   \
-		  return __impl._S_##__name(__xx);                             \
-		}));                                                           \
+		       __x.template _M_apply_r<_RetTp>(                        \
+			 [](auto __impl, auto __xx)                            \
+			   _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA                  \
+			 { return __impl._S_##__name(__xx); }));               \
 	  }                                                                    \
 	else if constexpr (                                                    \
 	  is_same_v<                                                           \
 	    _Tp,                                                               \
 	    _RetTp> && (... && is_same_v<_SimdTuple<_Tp, _As...>, _More>) )    \
 	  return __x._M_apply_per_chunk(                                       \
-	    [](auto __impl, auto __xx, auto... __pack) constexpr {             \
-	      using _V = typename decltype(__impl)::simd_type;                 \
-	      return __data(__name(_V(__private_init, __xx),                   \
-				   _V(__private_init, __pack)...));            \
-	    },                                                                 \
-	    __more...);                                                        \
+		   [](auto __impl, auto __xx, auto... __pack)                  \
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA              \
+		   {                                                           \
+		     using _V = typename decltype(__impl)::simd_type;          \
+		     return __data(__name(_V(__private_init, __xx),            \
+					  _V(__private_init, __pack)...));     \
+		   }, __more...);                                              \
 	else if constexpr (is_same_v<_Tp, _RetTp>)                             \
 	  return __x._M_apply_per_chunk(                                       \
-	    [](auto __impl, auto __xx, auto... __pack) constexpr {             \
-	      using _V = typename decltype(__impl)::simd_type;                 \
-	      return __data(__name(_V(__private_init, __xx),                   \
-				   __autocvt_to_simd(__pack)...));             \
-	    },                                                                 \
-	    __more...);                                                        \
+		   [](auto __impl, auto __xx, auto... __pack)                  \
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA              \
+		   {                                                           \
+		     using _V = typename decltype(__impl)::simd_type;          \
+		     return __data(__name(_V(__private_init, __xx),            \
+					  __autocvt_to_simd(__pack)...));      \
+		   }, __more...);                                              \
 	else                                                                   \
 	  __assert_unreachable<_Tp>();                                         \
       }
@@ -1657,10 +1671,10 @@ template <int _Np, typename>
 	__fixed_size_storage_t<int, _SimdTuple<_Tp, _Abis...>::_S_size()>* __z)
       {
 	return __x._M_apply_per_chunk(
-	  [](auto __impl, const auto __xx, const auto __yy, auto& __zz) {
-	    return __impl._S_remquo(__xx, __yy, &__zz);
-	  },
-	  __y, *__z);
+		 [](auto __impl, const auto __xx, const auto __yy, auto& __zz)
+		   _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		 { return __impl._S_remquo(__xx, __yy, &__zz); },
+		 __y, *__z);
       }
 
     template <typename _Tp, typename... _As>
@@ -1669,12 +1683,10 @@ template <int _Np, typename>
 	       __fixed_size_storage_t<int, _Np>& __exp) noexcept
       {
 	return __x._M_apply_per_chunk(
-	  [](auto __impl, const auto& __a, auto& __b) {
-	    return __data(
-	      frexp(typename decltype(__impl)::simd_type(__private_init, __a),
-		    __autocvt_to_simd(__b)));
-	  },
-	  __exp);
+		 [](auto __impl, const auto& __a, auto& __b) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __data(frexp(typename decltype(__impl)::simd_type(__private_init, __a),
+				       __autocvt_to_simd(__b)));
+		 }, __exp);
       }
 
 #define _GLIBCXX_SIMD_TEST_ON_TUPLE_(name_)                                    \
@@ -1700,7 +1712,7 @@ template <int _Np, typename>
       _S_increment(_SimdTuple<_Ts...>& __x)
       {
 	__for_each(
-	  __x, [](auto __meta, auto& native) constexpr {
+	  __x, [](auto __meta, auto& native) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta._S_increment(native);
 	  });
       }
@@ -1710,7 +1722,7 @@ template <int _Np, typename>
       _S_decrement(_SimdTuple<_Ts...>& __x)
       {
 	__for_each(
-	  __x, [](auto __meta, auto& native) constexpr {
+	  __x, [](auto __meta, auto& native) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta._S_decrement(native);
 	  });
       }
@@ -1722,11 +1734,10 @@ template <int _Np, typename>
       __cmp(const _SimdTuple<_Tp, _As...>& __x,                                \
 	    const _SimdTuple<_Tp, _As...>& __y)                                \
       {                                                                        \
-	return _M_test(                                                        \
-	  [](auto __impl, auto __xx, auto __yy) constexpr {                    \
-	    return __impl.__cmp(__xx, __yy);                                   \
-	  },                                                                   \
-	  __x, __y);                                                           \
+	return _M_test([](auto __impl, auto __xx, auto __yy)                   \
+			 constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA          \
+		       { return __impl.__cmp(__xx, __yy); },                   \
+		       __x, __y);                                              \
       }
 
     _GLIBCXX_SIMD_CMP_OPERATIONS(_S_equal_to)
@@ -1753,12 +1764,13 @@ template <int _Np, typename>
       _S_masked_assign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
 		       const __type_identity_t<_SimdTuple<_Tp, _As...>>& __rhs)
       {
-	__for_each(
-	  __lhs, __rhs,
-	  [&](auto __meta, auto& __native_lhs, auto __native_rhs) constexpr {
-	    __meta._S_masked_assign(__meta._S_make_mask(__bits), __native_lhs,
-				    __native_rhs);
-	  });
+	__for_each(__lhs, __rhs,
+		   [&](auto __meta, auto& __native_lhs, auto __native_rhs)
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		   {
+		     __meta._S_masked_assign(__meta._S_make_mask(__bits), __native_lhs,
+					     __native_rhs);
+		   });
       }
 
     // Optimization for the case where the RHS is a scalar. No need to broadcast
@@ -1769,7 +1781,7 @@ template <int _Np, typename>
 		       const __type_identity_t<_Tp> __rhs)
       {
 	__for_each(
-	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr {
+	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta._S_masked_assign(__meta._S_make_mask(__bits), __native_lhs,
 				    __rhs);
 	  });
@@ -1782,12 +1794,13 @@ template <int _Np, typename>
 					   const _SimdTuple<_Tp, _As...>& __rhs,
 					   _Op __op)
       {
-	__for_each(
-	  __lhs, __rhs,
-	  [&](auto __meta, auto& __native_lhs, auto __native_rhs) constexpr {
-	    __meta.template _S_masked_cassign(__meta._S_make_mask(__bits),
-					      __native_lhs, __native_rhs, __op);
-	  });
+	__for_each(__lhs, __rhs,
+		   [&](auto __meta, auto& __native_lhs, auto __native_rhs)
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		   {
+		     __meta.template _S_masked_cassign(__meta._S_make_mask(__bits),
+						       __native_lhs, __native_rhs, __op);
+		   });
       }
 
     // Optimization for the case where the RHS is a scalar. No need to broadcast
@@ -1798,7 +1811,7 @@ template <int _Np, typename>
 					   const _Tp& __rhs, _Op __op)
       {
 	__for_each(
-	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr {
+	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta.template _S_masked_cassign(__meta._S_make_mask(__bits),
 					      __native_lhs, __rhs, __op);
 	  });
@@ -1899,7 +1912,7 @@ template <int _Np, typename>
       // _Np _UShort, _UInt, _ULLong, float, and double can be more efficient.
       _ULLong __r = 0;
       using _Vs = __fixed_size_storage_t<_UChar, _Np>;
-      __for_each(_Vs{}, [&](auto __meta, auto) {
+      __for_each(_Vs{}, [&](auto __meta, auto) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	__r |= __meta._S_mask_to_shifted_ullong(
 	  __meta._S_mask_impl._S_load(&__mem[__meta._S_offset],
 				      _SizeConstant<__meta._S_size()>()));
@@ -1912,9 +1925,10 @@ template <int _Np, typename>
 					     _MaskMember __mask,
 					     const bool* __mem) noexcept
     {
-      _BitOps::_S_bit_iteration(__mask.to_ullong(), [&](auto __i) {
-	__merge.set(__i, __mem[__i]);
-      });
+      _BitOps::_S_bit_iteration(__mask.to_ullong(),
+				[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				  __merge.set(__i, __mem[__i]);
+				});
       return __merge;
     }
 
@@ -1932,7 +1946,8 @@ template <int _Np, typename>
     static inline void _S_masked_store(const _MaskMember __v, bool* __mem,
 				       const _MaskMember __k) noexcept
     {
-      _BitOps::_S_bit_iteration(__k, [&](auto __i) { __mem[__i] = __v[__i]; });
+      _BitOps::_S_bit_iteration(
+	__k, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { __mem[__i] = __v[__i]; });
     }
 
     // logical and bitwise operators {{{2
diff --git a/libstdc++-v3/include/experimental/bits/simd_math.h b/libstdc++-v3/include/experimental/bits/simd_math.h
index b008139c11c..61f9ad2ee7c 100644
--- a/libstdc++-v3/include/experimental/bits/simd_math.h
+++ b/libstdc++-v3/include/experimental/bits/simd_math.h
@@ -788,7 +788,7 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 
 	// __exponent(__x) returns the exponent value (bias removed) as
 	// simd<_Up> with integral _Up
-	auto&& __exponent = [](const _V& __v) {
+	auto&& __exponent = [](const _V& __v) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  using namespace std::experimental::__proposed;
 	  using _IV = rebind_simd_t<
 	    conditional_t<sizeof(_Tp) == sizeof(_LLong), _LLong, int>, _V>;
@@ -931,7 +931,7 @@ template <typename _R, typename _ToApply, typename _Tp, typename... _Tps>
   {
     return {__private_init,
 	    __data(__arg0)._M_apply_per_chunk(
-	      [&](auto __impl, const auto&... __inner) {
+	      [&](auto __impl, const auto&... __inner) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		using _V = typename decltype(__impl)::simd_type;
 		return __data(__apply(_V(__private_init, __inner)...));
 	      },
@@ -1092,8 +1092,9 @@ _GLIBCXX_SIMD_CVTING2(hypot)
     if constexpr (__is_fixed_size_abi_v<_Abi> && _V::size() > 1)
       {
 	return __fixed_size_apply<simd<_Tp, _Abi>>(
-	  [](auto __a, auto __b, auto __c) { return hypot(__a, __b, __c); },
-	  __x, __y, __z);
+		 [](auto __a, auto __b, auto __c) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return hypot(__a, __b, __c);
+		 }, __x, __y, __z);
       }
     else
       {
@@ -1380,9 +1381,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 		 const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __m,
 		 const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>([&](auto __i) {
-      return std::assoc_laguerre(__n[__i], __m[__i], __x[__i]);
-    });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::assoc_laguerre(__n[__i], __m[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1391,9 +1392,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 		 const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __m,
 		 const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>([&](auto __i) {
-      return std::assoc_legendre(__n[__i], __m[__i], __x[__i]);
-    });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::assoc_legendre(__n[__i], __m[__i], __x[__i]);
+	   });
   }
 
 _GLIBCXX_SIMD_MATH_CALL2_(beta, _Tp)
@@ -1414,8 +1415,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   hermite(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	  const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::hermite(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::hermite(__n[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1423,8 +1425,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   laguerre(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	   const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::laguerre(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::laguerre(__n[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1432,8 +1435,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   legendre(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	   const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::legendre(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::legendre(__n[__i], __x[__i]);
+	   });
   }
 
 _GLIBCXX_SIMD_MATH_CALL_(riemann_zeta)
@@ -1443,8 +1447,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   sph_bessel(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	     const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::sph_bessel(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::sph_bessel(__n[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1453,9 +1458,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 	       const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __m,
 	       const simd<_Tp, _Abi>& theta)
   {
-    return simd<_Tp, _Abi>([&](auto __i) {
-      return std::assoc_legendre(__l[__i], __m[__i], theta[__i]);
-    });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::assoc_legendre(__l[__i], __m[__i], theta[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1463,8 +1468,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   sph_neumann(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	      const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::sph_neumann(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::sph_neumann(__n[__i], __x[__i]);
+	   });
   }
 // }}}
 
diff --git a/libstdc++-v3/include/experimental/bits/simd_neon.h b/libstdc++-v3/include/experimental/bits/simd_neon.h
index 0945092940a..c809addd2af 100644
--- a/libstdc++-v3/include/experimental/bits/simd_neon.h
+++ b/libstdc++-v3/include/experimental/bits/simd_neon.h
@@ -61,7 +61,7 @@ template <typename _Abi, typename>
       _S_masked_load(_SimdWrapper<_Tp, _Np> __merge, _MaskMember<_Tp> __k,
 		     const _Up* __mem) noexcept
       {
-	__execute_n_times<_Np>([&](auto __i) {
+	__execute_n_times<_Np>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__k[__i] != 0)
 	    __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
 	});
@@ -75,7 +75,7 @@ template <typename _Abi, typename>
       _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem,
 			    _MaskMember<_Tp> __k)
       {
-	__execute_n_times<_Np>([&](auto __i) {
+	__execute_n_times<_Np>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__k[__i] != 0)
 	    __mem[__i] = __v[__i];
 	});
@@ -286,7 +286,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<16, __vector_type_t<_I, 16>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(
 		      __i < _Np ? (__i < 8 ? 1 << __i : 1 << (__i - 8)) : 0);
 		  });
@@ -306,7 +306,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<8, __vector_type_t<_I, 8>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
@@ -322,7 +322,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<4, __vector_type_t<_I, 4>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
@@ -346,7 +346,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<8, __vector_type_t<_I, 8>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
@@ -361,7 +361,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<4, __vector_type_t<_I, 4>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
diff --git a/libstdc++-v3/include/experimental/bits/simd_x86.h b/libstdc++-v3/include/experimental/bits/simd_x86.h
index 35702464608..c8dde61380e 100644
--- a/libstdc++-v3/include/experimental/bits/simd_x86.h
+++ b/libstdc++-v3/include/experimental/bits/simd_x86.h
@@ -537,16 +537,17 @@ struct _CommonImplX86 : _CommonImplBuiltin
     _S_store_bool_array(const _BitMask<_Np, _Sanitized> __x, bool* __mem)
     {
       if constexpr (__have_avx512bw_vl) // don't care for BW w/o VL
-	_S_store<_Np>(1 & __vector_bitcast<_UChar, _Np>([=]() constexpr {
-			if constexpr (_Np <= 16)
-			  return _mm_movm_epi8(__x._M_to_bits());
-			else if constexpr (_Np <= 32)
-			  return _mm256_movm_epi8(__x._M_to_bits());
-			else if constexpr (_Np <= 64)
-			  return _mm512_movm_epi8(__x._M_to_bits());
-			else
-			  __assert_unreachable<_SizeConstant<_Np>>();
-		      }()),
+	_S_store<_Np>(1 & __vector_bitcast<_UChar, _Np>(
+			    [=]() constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			      if constexpr (_Np <= 16)
+				return _mm_movm_epi8(__x._M_to_bits());
+			      else if constexpr (_Np <= 32)
+				return _mm256_movm_epi8(__x._M_to_bits());
+			      else if constexpr (_Np <= 64)
+				return _mm512_movm_epi8(__x._M_to_bits());
+			      else
+				__assert_unreachable<_SizeConstant<_Np>>();
+			    }()),
 		      __mem);
       else if constexpr (__have_bmi2)
 	{
@@ -554,7 +555,7 @@ struct _CommonImplX86 : _CommonImplBuiltin
 	    _S_store<_Np>(_pdep_u32(__x._M_to_bits(), 0x01010101U), __mem);
 	  else
 	    __execute_n_times<__div_roundup(_Np, sizeof(size_t))>(
-	      [&](auto __i) {
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		constexpr size_t __offset = __i * sizeof(size_t);
 		constexpr int __todo = std::min(sizeof(size_t), _Np - __offset);
 		if constexpr (__todo == 1)
@@ -575,7 +576,7 @@ struct _CommonImplX86 : _CommonImplBuiltin
 	      });
 	}
       else if constexpr (__have_sse2 && _Np > 7)
-	__execute_n_times<__div_roundup(_Np, 16)>([&](auto __i) {
+	__execute_n_times<__div_roundup(_Np, 16)>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  constexpr int __offset = __i * 16;
 	  constexpr int __todo = std::min(16, int(_Np) - __offset);
 	  const int __bits = __x.template _M_extract<__offset>()._M_to_bits();
@@ -765,9 +766,10 @@ struct _CommonImplX86 : _CommonImplBuiltin
       static_assert(is_same_v<_Tp, _Tp> && __have_avx512f);
       if (__k._M_is_constprop() && __at0._M_is_constprop()
 	  && __at1._M_is_constprop())
-	return __generate_from_n_evaluations<_Np,
-					     __vector_type_t<_Tp, _Np>>([&](
-	  auto __i) constexpr { return __k[__i] ? __at1[__i] : __at0[__i]; });
+	return __generate_from_n_evaluations<_Np, __vector_type_t<_Tp, _Np>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __k[__i] ? __at1[__i] : __at0[__i];
+		 });
       else if constexpr (sizeof(__at0) == 64
 			 || (__have_avx512vl && sizeof(__at0) >= 16))
 	return _S_blend_avx512(__k._M_data, __at0._M_data, __at1._M_data);
@@ -994,9 +996,8 @@ template <typename _Abi, typename>
 	      }
 	    else
 	      _BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k),
-					[&](auto __i) {
-					  __merge._M_set(__i, static_cast<_Tp>(
-								__mem[__i]));
+					[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+					  __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
 					});
 	  }
 	/* Very uncertain, that the following improves anything. Needs
@@ -1417,11 +1418,12 @@ template <typename _Abi, typename>
 	      const auto __yf = __convert_all<_FloatV, __n_floatv>(
 		_Abi::__make_padding_nonzero(__as_vector(__y)));
 	      return __call_with_n_evaluations<__n_floatv>(
-		[](auto... __quotients) {
+		[](auto... __quotients) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  return __vector_convert<_R>(__quotients...);
 		},
-		[&__xf,
-		 &__yf](auto __i) -> _SimdWrapper<_Float, __n_intermediate> {
+		[&__xf, &__yf](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		  -> _SimdWrapper<_Float, __n_intermediate>
+		{
 #if __RECIPROCAL_MATH__
 		  // If -freciprocal-math is active, using the `/` operator is
 		  // incorrect because it may be translated to an imprecise
@@ -1980,7 +1982,7 @@ template <typename _Abi, typename>
 	      {
 		auto __mask = __vector_bitcast<_UChar>(
 		  __vector_bitcast<_UShort>(__iy) << 5);
-		auto __maskl = [&]() {
+		auto __maskl = [&]() _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  return __to_intrin(__vector_bitcast<_UShort>(__mask) << 8);
 		};
 		auto __xh = __vector_bitcast<short>(__ix);
@@ -2067,19 +2069,20 @@ template <typename _Abi, typename>
 	  }                                                      //}}}
 	else if constexpr (sizeof(_Up) == 2 && sizeof(__x) >= 4) //{{{
 	  {
-	    [[maybe_unused]] auto __blend_0xaa = [](auto __a, auto __b) {
-	      if constexpr (sizeof(__a) == 16)
-		return _mm_blend_epi16(__to_intrin(__a), __to_intrin(__b),
-				       0xaa);
-	      else if constexpr (sizeof(__a) == 32)
-		return _mm256_blend_epi16(__to_intrin(__a), __to_intrin(__b),
-					  0xaa);
-	      else if constexpr (sizeof(__a) == 64)
-		return _mm512_mask_blend_epi16(0xaaaa'aaaaU, __to_intrin(__a),
-					       __to_intrin(__b));
-	      else
-		__assert_unreachable<decltype(__a)>();
-	    };
+	    [[maybe_unused]] auto __blend_0xaa
+	      = [](auto __a, auto __b) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		if constexpr (sizeof(__a) == 16)
+		  return _mm_blend_epi16(__to_intrin(__a), __to_intrin(__b),
+					 0xaa);
+		else if constexpr (sizeof(__a) == 32)
+		  return _mm256_blend_epi16(__to_intrin(__a), __to_intrin(__b),
+					    0xaa);
+		else if constexpr (sizeof(__a) == 64)
+		  return _mm512_mask_blend_epi16(0xaaaa'aaaaU, __to_intrin(__a),
+						 __to_intrin(__b));
+		else
+		  __assert_unreachable<decltype(__a)>();
+	      };
 	    if constexpr (__have_avx512bw_vl && sizeof(_Tp) <= 16)
 	      return __intrin_bitcast<_V>(is_signed_v<_Up>
 					    ? _mm_srav_epi16(__ix, __iy)
@@ -2136,9 +2139,10 @@ template <typename _Abi, typename>
 	      {
 		auto __k = __vector_bitcast<_UShort>(__iy) << 11;
 		auto __x128 = __vector_bitcast<_Up>(__ix);
-		auto __mask = [](__vector_type16_t<_UShort> __kk) {
-		  return __vector_bitcast<short>(__kk) < 0;
-		};
+		auto __mask
+		  = [](__vector_type16_t<_UShort> __kk) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		    return __vector_bitcast<short>(__kk) < 0;
+		  };
 		// do __x128 = 0 where __y[4] is set
 		__x128 = __mask(__k) ? decltype(__x128)() : __x128;
 		// do __x128 =>> 8 where __y[3] is set
@@ -2178,7 +2182,7 @@ template <typename _Abi, typename>
 	      }
 	    else
 	      {
-		auto __shift = [](auto __a, auto __b) {
+		auto __shift = [](auto __a, auto __b) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  if constexpr (is_signed_v<_Up>)
 		    return _mm_sra_epi32(__a, __b);
 		  else
@@ -3495,7 +3499,7 @@ struct _MaskImplX86Mixin
 	return _S_to_maskvector<_Up, _ToN>(__k);
       else if (__x._M_is_constprop() || __builtin_is_constant_evaluated())
 	return __generate_from_n_evaluations<std::min(_ToN, _Np), _UV>(
-	  [&](auto __i) -> _Up { return -__x[__i.value]; });
+	  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Up { return -__x[__i.value]; });
       else if constexpr (sizeof(_Up) == 1)
 	{
 	  if constexpr (sizeof(_UI) == 16)
@@ -3740,9 +3744,9 @@ struct _MaskImplX86Mixin
       else if constexpr (__bits_per_element >= _ToN)
 	{
 	  constexpr auto __bitmask
-	    = __generate_vector<_V>([](auto __i) constexpr->_UpUInt {
-		return __i < _ToN ? 1ull << __i : 0;
-	      });
+	    = __generate_vector<_V>([](auto __i)
+				    constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _UpUInt
+				    { return __i < _ToN ? 1ull << __i : 0; });
 	  const auto __bits
 	    = __vector_broadcast<_ToN, _UpUInt>(__k) & __bitmask;
 	  if constexpr (__bits_per_element > _ToN)
@@ -3753,11 +3757,11 @@ struct _MaskImplX86Mixin
       else
 	{
 	  const _V __tmp
-	    = __generate_vector<_V>([&](auto __i) constexpr {
+	    = __generate_vector<_V>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		return static_cast<_UpUInt>(
 		  __k >> (__bits_per_element * (__i / __bits_per_element)));
 	      })
-	      & __generate_vector<_V>([](auto __i) constexpr {
+	      & __generate_vector<_V>([](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  return static_cast<_UpUInt>(1ull
 					      << (__i % __bits_per_element));
 		}); // mask bit index
@@ -3793,7 +3797,7 @@ struct _MaskImplX86Mixin
 	      const auto __y = __vector_bitcast<__int_for_sizeof_t<_Tp>>(__x);
 	      return __generate_from_n_evaluations<std::min(_ToN, _Np),
 						   __vector_type_t<_Up, _ToN>>(
-		[&](auto __i) -> _Up { return __y[__i.value]; });
+		[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Up { return __y[__i.value]; });
 	    }
 	  using _To = __vector_type_t<_Up, _ToN>;
 	  [[maybe_unused]] constexpr size_t _FromN = _Np;
@@ -4128,8 +4132,11 @@ struct _MaskImplX86Mixin
 	    {
 	      const auto __bools = -__x._M_data;
 	      const _ULLong __k = __call_with_n_evaluations<_Np>(
-		[](auto... __bits) { return (__bits | ...); },
-		[&](auto __i) { return _ULLong(__bools[+__i]) << __i; });
+		[](auto... __bits) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		  return (__bits | ...);
+		}, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		  return _ULLong(__bools[+__i]) << __i;
+		});
 	      if (__builtin_is_constant_evaluated()
 		  || __builtin_constant_p(__k))
 		return __k;
@@ -4285,13 +4292,14 @@ template <typename _Abi, typename>
 	static_assert(is_same_v<_Tp, __int_for_sizeof_t<_Tp>>);
 	if constexpr (__have_avx512bw)
 	  {
-	    const auto __to_vec_or_bits = [](auto __bits) -> decltype(auto) {
-	      if constexpr (__is_avx512_abi<_Abi>())
-		return __bits;
-	      else
-		return _S_to_maskvector<_Tp>(
-		  _BitMask<_S_size<_Tp>>(__bits)._M_sanitized());
-	    };
+	    const auto __to_vec_or_bits
+	      = [](auto __bits) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> decltype(auto) {
+		if constexpr (__is_avx512_abi<_Abi>())
+		  return __bits;
+		else
+		  return _S_to_maskvector<_Tp>(
+			   _BitMask<_S_size<_Tp>>(__bits)._M_sanitized());
+	      };
 
 	    if constexpr (_S_size<_Tp> <= 16 && __have_avx512vl)
 	      {
@@ -4478,7 +4486,7 @@ template <typename _Abi, typename>
 	      }
 	    else
 	      {
-		_BitOps::_S_bit_iteration(__mask, [&](auto __i) {
+		_BitOps::_S_bit_iteration(__mask, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  __merge._M_set(__i, __mem[__i]);
 		});
 		return __merge;
@@ -4557,7 +4565,7 @@ template <typename _Abi, typename>
 	  {
 	    if constexpr (__have_avx512bw_vl)
 	      _CommonImplX86::_S_store<_Np>(
-		__vector_bitcast<char>([](auto __data) {
+		__vector_bitcast<char>([](auto __data) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  if constexpr (_Np <= 16)
 		    return _mm_maskz_set1_epi8(__data, 1);
 		  else if constexpr (_Np <= 32)

commit 41f75cfea48d97ea5cadd220d932163a1e17cf9a
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Mon Feb 20 11:13:44 2023

    libstdc++: Fix simd build failure on clang
    
    Clang does not support __attribute__ on lambdas. Therefore, only set
    _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA if __clang__ is not defined.
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/108030
            * include/experimental/bits/simd_detail.h
            (_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA): Define as empty for
            __clang__.
    
    (cherry picked from commit 92c47b15d5af3e7f93d11ad69a45b6d1cb8661c5)

diff --git a/libstdc++-v3/include/experimental/bits/simd_detail.h b/libstdc++-v3/include/experimental/bits/simd_detail.h
index bd4e380df65..fee7f871176 100644
--- a/libstdc++-v3/include/experimental/bits/simd_detail.h
+++ b/libstdc++-v3/include/experimental/bits/simd_detail.h
@@ -254,15 +254,16 @@
 
 #ifdef __clang__
 #define _GLIBCXX_SIMD_NORMAL_MATH
+#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
 #else
 #define _GLIBCXX_SIMD_NORMAL_MATH                                              \
   [[__gnu__::__optimize__("finite-math-only,no-signed-zeros")]]
+#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA __attribute__((__always_inline__))
 #endif
 #define _GLIBCXX_SIMD_NEVER_INLINE [[__gnu__::__noinline__]]
 #define _GLIBCXX_SIMD_INTRINSIC                                                \
   [[__gnu__::__always_inline__, __gnu__::__artificial__]] inline
 #define _GLIBCXX_SIMD_ALWAYS_INLINE [[__gnu__::__always_inline__]] inline
-#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA __attribute__((__always_inline__))
 #define _GLIBCXX_SIMD_IS_UNLIKELY(__x) __builtin_expect(__x, 0)
 #define _GLIBCXX_SIMD_IS_LIKELY(__x) __builtin_expect(__x, 1)
 

commit 88cfa0807472946db6af345f2b7ac7e1626697e3
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Tue Feb 21 10:43:13 2023

    libstdc++: Test that integral simd reductions are precise
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * testsuite/experimental/simd/tests/reductions.cc: Introduce
            max_distance as the type-dependent max error.
    
    (cherry picked from commit 8fda668e0919af9ceda9435f02a1708b375b2913)

diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/reductions.cc b/libstdc++-v3/testsuite/experimental/simd/tests/reductions.cc
index f3fd1487cbf..00fba1b039c 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/reductions.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/reductions.cc
@@ -114,6 +114,7 @@ template <typename V>
       T acc = x[0];
       for (size_t i = 1; i < V::size(); ++i)
 	acc += x[i];
-      ULP_COMPARE(reduce(x), acc, V::size() / 2).on_failure("x = ", x);
+      const T max_distance = std::is_integral_v<T> ? 0 : V::size() / 2;
+      ULP_COMPARE(reduce(x), acc, max_distance).on_failure("x = ", x);
     });
   }

commit 4452077962d0c327dcb08670ab73f7197be53e91
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Mon Feb 20 16:33:31 2023

    libstdc++: More efficient masked inc-/decrement implementation
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/108856
            * include/experimental/bits/simd_builtin.h
            (_SimdImplBuiltin::_S_masked_unary): More efficient
            implementation of masked inc-/decrement for integers and floats
            without AVX2.
            * include/experimental/bits/simd_x86.h
            (_SimdImplX86::_S_masked_unary): New. Use AVX512 masked subtract
            builtins for masked inc-/decrement.
    
    (cherry picked from commit 6ce55180d494b616e2e3e68ffedfe9007e42ca06)

diff --git a/libstdc++-v3/include/experimental/bits/simd_builtin.h b/libstdc++-v3/include/experimental/bits/simd_builtin.h
index 119e0deb2af..71469483276 100644
--- a/libstdc++-v3/include/experimental/bits/simd_builtin.h
+++ b/libstdc++-v3/include/experimental/bits/simd_builtin.h
@@ -2546,8 +2546,31 @@ template <typename _Abi, typename>
 	_Op<decltype(__vv)> __op;
 	if (__k._M_is_constprop_all_of())
 	  return __data(__op(__vv));
-	else
-	  return _CommonImpl::_S_blend(__k, __v, __data(__op(__vv)));
+	else if constexpr (is_same_v<_Op<void>, __increment<void>>)
+	  {
+	    static_assert(not std::is_same_v<_K, bool>);
+	    if constexpr (is_integral_v<_Tp>)
+	      // Take a shortcut knowing that __k is an integer vector with values -1 or 0.
+	      return __v._M_data - __vector_bitcast<_Tp>(__k._M_data);
+	    else if constexpr (not __have_avx2)
+	      return __v._M_data
+		       + __vector_bitcast<_Tp>(__k._M_data & __builtin_bit_cast(
+							       _K, _Tp(1)));
+	    // starting with AVX2 it is more efficient to blend after add
+	  }
+	else if constexpr (is_same_v<_Op<void>, __decrement<void>>)
+	  {
+	    static_assert(not std::is_same_v<_K, bool>);
+	    if constexpr (is_integral_v<_Tp>)
+	      // Take a shortcut knowing that __k is an integer vector with values -1 or 0.
+	      return __v._M_data + __vector_bitcast<_Tp>(__k._M_data);
+	    else if constexpr (not __have_avx2)
+	      return __v._M_data
+		       - __vector_bitcast<_Tp>(__k._M_data & __builtin_bit_cast(
+							       _K, _Tp(1)));
+	    // starting with AVX2 it is more efficient to blend after sub
+	  }
+	return _CommonImpl::_S_blend(__k, __v, __data(__op(__vv)));
       }
 
     //}}}2
diff --git a/libstdc++-v3/include/experimental/bits/simd_x86.h b/libstdc++-v3/include/experimental/bits/simd_x86.h
index c8dde61380e..a9ec5c6f9d8 100644
--- a/libstdc++-v3/include/experimental/bits/simd_x86.h
+++ b/libstdc++-v3/include/experimental/bits/simd_x86.h
@@ -3462,6 +3462,74 @@ template <typename _Abi, typename>
       }
 
     //}}} }}}
+    template <template <typename> class _Op, typename _Tp, typename _K,
+	      size_t _Np>
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_masked_unary(const _SimdWrapper<_K, _Np> __k,
+		      const _SimdWrapper<_Tp, _Np> __v)
+      {
+	if (__k._M_is_constprop_none_of())
+	  return __v;
+	else if (__k._M_is_constprop_all_of())
+	  {
+	    auto __vv = _Base::_M_make_simd(__v);
+	    _Op<decltype(__vv)> __op;
+	    return __data(__op(__vv));
+	  }
+	else if constexpr (__is_bitmask_v<decltype(__k)>
+			     && (is_same_v<_Op<void>, __increment<void>>
+				   || is_same_v<_Op<void>, __decrement<void>>))
+	  {
+	    // optimize masked unary increment and decrement as masked sub +/-1
+	    constexpr int __pm_one
+	      = is_same_v<_Op<void>, __increment<void>> ? -1 : 1;
+	    if constexpr (is_integral_v<_Tp>)
+	      {
+		constexpr bool __lp64 = sizeof(long) == sizeof(long long);
+		using _Ip = std::make_signed_t<_Tp>;
+		using _Up = std::conditional_t<
+			      std::is_same_v<_Ip, long>,
+			      std::conditional_t<__lp64, long long, int>,
+			      std::conditional_t<
+				std::is_same_v<_Ip, signed char>, char, _Ip>>;
+		const auto __value = __vector_bitcast<_Up>(__v._M_data);
+#define _GLIBCXX_SIMD_MASK_SUB(_Sizeof, _Width, _Instr)                        \
+  if constexpr (sizeof(_Tp) == _Sizeof && sizeof(__v) == _Width)               \
+    return __vector_bitcast<_Tp>(__builtin_ia32_##_Instr##_mask(__value,       \
+	     __vector_broadcast<_Np>(_Up(__pm_one)), __value, __k._M_data))
+		_GLIBCXX_SIMD_MASK_SUB(1, 64, psubb512);
+		_GLIBCXX_SIMD_MASK_SUB(1, 32, psubb256);
+		_GLIBCXX_SIMD_MASK_SUB(1, 16, psubb128);
+		_GLIBCXX_SIMD_MASK_SUB(2, 64, psubw512);
+		_GLIBCXX_SIMD_MASK_SUB(2, 32, psubw256);
+		_GLIBCXX_SIMD_MASK_SUB(2, 16, psubw128);
+		_GLIBCXX_SIMD_MASK_SUB(4, 64, psubd512);
+		_GLIBCXX_SIMD_MASK_SUB(4, 32, psubd256);
+		_GLIBCXX_SIMD_MASK_SUB(4, 16, psubd128);
+		_GLIBCXX_SIMD_MASK_SUB(8, 64, psubq512);
+		_GLIBCXX_SIMD_MASK_SUB(8, 32, psubq256);
+		_GLIBCXX_SIMD_MASK_SUB(8, 16, psubq128);
+#undef _GLIBCXX_SIMD_MASK_SUB
+	      }
+	    else
+	      {
+#define _GLIBCXX_SIMD_MASK_SUB(_Sizeof, _Width, _Instr)                        \
+  if constexpr (sizeof(_Tp) == _Sizeof && sizeof(__v) == _Width)               \
+    return __builtin_ia32_##_Instr##_mask(                                     \
+	     __v._M_data, __vector_broadcast<_Np>(_Tp(__pm_one)), __v._M_data, \
+	     __k._M_data, _MM_FROUND_CUR_DIRECTION)
+		_GLIBCXX_SIMD_MASK_SUB(4, 64, subps512);
+		_GLIBCXX_SIMD_MASK_SUB(4, 32, subps256);
+		_GLIBCXX_SIMD_MASK_SUB(4, 16, subps128);
+		_GLIBCXX_SIMD_MASK_SUB(8, 64, subpd512);
+		_GLIBCXX_SIMD_MASK_SUB(8, 32, subpd256);
+		_GLIBCXX_SIMD_MASK_SUB(8, 16, subpd128);
+#undef _GLIBCXX_SIMD_MASK_SUB
+	      }
+	  }
+	else
+	  return _Base::template _S_masked_unary<_Op>(__k, __v);
+      }
   };
 
 // }}}

commit c989c9196f6900c2ab6f0665751ca0320d2f3cdc
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Mon Feb 20 17:49:37 2023

    libstdc++: Always-inline most of non-cmath fixed_size implementation
    
    For simd, the inlining behavior should be similar to builtin types. (No
    operator on buitin types is ever translated into a function call.)
    Therefore, always_inline is the right choice (i.e. inline on -O0 as
    well).
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/108030
            * include/experimental/bits/simd_fixed_size.h
            (_SimdImplFixedSize::_S_broadcast): Replace inline with
            _GLIBCXX_SIMD_INTRINSIC.
            (_SimdImplFixedSize::_S_generate): Likewise.
            (_SimdImplFixedSize::_S_load): Likewise.
            (_SimdImplFixedSize::_S_masked_load): Likewise.
            (_SimdImplFixedSize::_S_store): Likewise.
            (_SimdImplFixedSize::_S_masked_store): Likewise.
            (_SimdImplFixedSize::_S_min): Likewise.
            (_SimdImplFixedSize::_S_max): Likewise.
            (_SimdImplFixedSize::_S_complement): Likewise.
            (_SimdImplFixedSize::_S_unary_minus): Likewise.
            (_SimdImplFixedSize::_S_plus): Likewise.
            (_SimdImplFixedSize::_S_minus): Likewise.
            (_SimdImplFixedSize::_S_multiplies): Likewise.
            (_SimdImplFixedSize::_S_divides): Likewise.
            (_SimdImplFixedSize::_S_modulus): Likewise.
            (_SimdImplFixedSize::_S_bit_and): Likewise.
            (_SimdImplFixedSize::_S_bit_or): Likewise.
            (_SimdImplFixedSize::_S_bit_xor): Likewise.
            (_SimdImplFixedSize::_S_bit_shift_left): Likewise.
            (_SimdImplFixedSize::_S_bit_shift_right): Likewise.
            (_SimdImplFixedSize::_S_remquo): Add inline keyword (to be
            explicit about not always-inline, yet).
            (_SimdImplFixedSize::_S_isinf): Likewise.
            (_SimdImplFixedSize::_S_isfinite): Likewise.
            (_SimdImplFixedSize::_S_isnan): Likewise.
            (_SimdImplFixedSize::_S_isnormal): Likewise.
            (_SimdImplFixedSize::_S_signbit): Likewise.
    
    (cherry picked from commit e37b04328ae68f91efe1fb2c5de9122be34bc74a)

diff --git a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
index eb71a7b6295..dba6353b176 100644
--- a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
+++ b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
@@ -1284,7 +1284,8 @@ template <int _Np, typename>
 
     // broadcast {{{2
     template <typename _Tp>
-      static constexpr inline _SimdMember<_Tp> _S_broadcast(_Tp __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
+      _S_broadcast(_Tp __x) noexcept
       {
 	return _SimdMember<_Tp>::_S_generate(
 		 [&](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1294,8 +1295,8 @@ template <int _Np, typename>
 
     // _S_generator {{{2
     template <typename _Fp, typename _Tp>
-      static constexpr inline _SimdMember<_Tp> _S_generator(_Fp&& __gen,
-							    _TypeTag<_Tp>)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
+      _S_generator(_Fp&& __gen, _TypeTag<_Tp>)
       {
 	return _SimdMember<_Tp>::_S_generate(
 		 [&__gen](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1310,8 +1311,8 @@ template <int _Np, typename>
 
     // _S_load {{{2
     template <typename _Tp, typename _Up>
-      static inline _SimdMember<_Tp> _S_load(const _Up* __mem,
-					     _TypeTag<_Tp>) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static _SimdMember<_Tp>
+      _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	return _SimdMember<_Tp>::_S_generate(
 		 [&](auto __meta) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1321,7 +1322,7 @@ template <int _Np, typename>
 
     // _S_masked_load {{{2
     template <typename _Tp, typename... _As, typename _Up>
-      static inline _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static _SimdTuple<_Tp, _As...>
       _S_masked_load(const _SimdTuple<_Tp, _As...>& __old,
 		     const _MaskMember __bits, const _Up* __mem) noexcept
       {
@@ -1344,8 +1345,8 @@ template <int _Np, typename>
 
     // _S_store {{{2
     template <typename _Tp, typename _Up>
-      static inline void _S_store(const _SimdMember<_Tp>& __v, _Up* __mem,
-				  _TypeTag<_Tp>) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static void
+      _S_store(const _SimdMember<_Tp>& __v, _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	__for_each(__v, [&](auto __meta, auto __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  __meta._S_store(__native, &__mem[__meta._S_offset], _TypeTag<_Tp>());
@@ -1354,9 +1355,9 @@ template <int _Np, typename>
 
     // _S_masked_store {{{2
     template <typename _Tp, typename... _As, typename _Up>
-      static inline void _S_masked_store(const _SimdTuple<_Tp, _As...>& __v,
-					 _Up* __mem,
-					 const _MaskMember __bits) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static void
+      _S_masked_store(const _SimdTuple<_Tp, _As...>& __v, _Up* __mem,
+		      const _MaskMember __bits) noexcept
       {
 	__for_each(__v, [&](auto __meta, auto __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__meta._S_submask(__bits).any())
@@ -1464,7 +1465,7 @@ template <int _Np, typename>
 
     // _S_min, _S_max {{{2
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_min(const _SimdTuple<_Tp, _As...>& __a,
 	     const _SimdTuple<_Tp, _As...>& __b)
       {
@@ -1476,7 +1477,7 @@ template <int _Np, typename>
       }
 
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_max(const _SimdTuple<_Tp, _As...>& __a,
 	     const _SimdTuple<_Tp, _As...>& __b)
       {
@@ -1489,7 +1490,7 @@ template <int _Np, typename>
 
     // _S_complement {{{2
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_complement(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
 	return __x._M_apply_per_chunk(
@@ -1500,7 +1501,7 @@ template <int _Np, typename>
 
     // _S_unary_minus {{{2
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_unary_minus(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
 	return __x._M_apply_per_chunk(
@@ -1513,7 +1514,7 @@ template <int _Np, typename>
 
 #define _GLIBCXX_SIMD_FIXED_OP(name_, op_)                                                     \
     template <typename _Tp, typename... _As>                                                   \
-      static inline constexpr _SimdTuple<_Tp, _As...> name_(                                   \
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...> name_(                  \
 	const _SimdTuple<_Tp, _As...>& __x, const _SimdTuple<_Tp, _As...>& __y)                \
       {                                                                                        \
 	return __x._M_apply_per_chunk(                                                         \
@@ -1536,7 +1537,7 @@ template <int _Np, typename>
 #undef _GLIBCXX_SIMD_FIXED_OP
 
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_bit_shift_left(const _SimdTuple<_Tp, _As...>& __x, int __y)
       {
 	return __x._M_apply_per_chunk(
@@ -1546,7 +1547,7 @@ template <int _Np, typename>
       }
 
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_bit_shift_right(const _SimdTuple<_Tp, _As...>& __x, int __y)
       {
 	return __x._M_apply_per_chunk(
@@ -1665,10 +1666,9 @@ template <int _Np, typename>
 #undef _GLIBCXX_SIMD_APPLY_ON_TUPLE
 
     template <typename _Tp, typename... _Abis>
-      static _SimdTuple<_Tp, _Abis...> _S_remquo(
-	const _SimdTuple<_Tp, _Abis...>& __x,
-	const _SimdTuple<_Tp, _Abis...>& __y,
-	__fixed_size_storage_t<int, _SimdTuple<_Tp, _Abis...>::_S_size()>* __z)
+      static inline _SimdTuple<_Tp, _Abis...>
+      _S_remquo(const _SimdTuple<_Tp, _Abis...>& __x, const _SimdTuple<_Tp, _Abis...>& __y,
+		__fixed_size_storage_t<int, _SimdTuple<_Tp, _Abis...>::_S_size()>* __z)
       {
 	return __x._M_apply_per_chunk(
 		 [](auto __impl, const auto __xx, const auto __yy, auto& __zz)
@@ -1689,14 +1689,14 @@ template <int _Np, typename>
 		 }, __exp);
       }
 
-#define _GLIBCXX_SIMD_TEST_ON_TUPLE_(name_)                                    \
-    template <typename _Tp, typename... _As>                                   \
-      static inline _MaskMember                                                \
-	_S_##name_(const _SimdTuple<_Tp, _As...>& __x) noexcept                \
-      {                                                                        \
-	return _M_test([](auto __impl,                                         \
-			  auto __xx) { return __impl._S_##name_(__xx); },      \
-		       __x);                                                   \
+#define _GLIBCXX_SIMD_TEST_ON_TUPLE_(name_)                                              \
+    template <typename _Tp, typename... _As>                                             \
+      static inline _MaskMember                                                          \
+	_S_##name_(const _SimdTuple<_Tp, _As...>& __x) noexcept                          \
+      {                                                                                  \
+	return _M_test([] (auto __impl, auto __xx) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA  { \
+		 return __impl._S_##name_(__xx);                                         \
+	       }, __x);                                                                  \
       }
 
     _GLIBCXX_SIMD_TEST_ON_TUPLE_(isinf)

commit 26740dbf577eb8c81296dc61d5b9d9b241046fc7
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Tue Feb 21 08:48:18 2023

    libstdc++: Fix formatting
    
    Whitespace changes only.
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * include/experimental/bits/simd.h: Line breaks and indenting
            fixed to follow the libstdc++ standard.
            * include/experimental/bits/simd_builtin.h: Likewise.
            * include/experimental/bits/simd_fixed_size.h: Likewise.
            * include/experimental/bits/simd_neon.h: Likewise.
            * include/experimental/bits/simd_ppc.h: Likewise.
            * include/experimental/bits/simd_scalar.h: Likewise.
            * include/experimental/bits/simd_x86.h: Likewise.
    
    (cherry picked from commit b31186e589caee43ac5720a538d9a41ebf514e81)

diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h
index 8fcd45c6c45..ec213468f50 100644
--- a/libstdc++-v3/include/experimental/bits/simd.h
+++ b/libstdc++-v3/include/experimental/bits/simd.h
@@ -180,10 +180,7 @@ struct vector_aligned_tag
   template <typename _Tp, typename _Up>
     _GLIBCXX_SIMD_INTRINSIC static constexpr _Up*
     _S_apply(_Up* __ptr)
-    {
-      return static_cast<_Up*>(
-	__builtin_assume_aligned(__ptr, _S_alignment<_Tp, _Up>));
-    }
+    { return static_cast<_Up*>(__builtin_assume_aligned(__ptr, _S_alignment<_Tp, _Up>)); }
 };
 
 template <size_t _Np> struct overaligned_tag
@@ -288,13 +285,15 @@ namespace __detail
   // expression. math_errhandling may expand to an extern symbol, in which case a constexpr value
   // must be guessed.
   template <int = math_errhandling>
-    constexpr bool __handle_fpexcept_impl(int)
+    constexpr bool
+    __handle_fpexcept_impl(int)
     { return math_errhandling & MATH_ERREXCEPT; }
 #endif
 
   // Fallback if math_errhandling doesn't work: with fast-math assume floating-point exceptions are
   // ignored, otherwise implement correct exception behavior.
-  constexpr bool __handle_fpexcept_impl(float)
+  constexpr bool
+  __handle_fpexcept_impl(float)
   {
 #if defined __FAST_MATH__
     return false;
@@ -749,8 +748,7 @@ template <typename _Tp, typename _Up>
 // __invoke_ub{{{
 template <typename... _Args>
   [[noreturn]] _GLIBCXX_SIMD_ALWAYS_INLINE void
-  __invoke_ub([[maybe_unused]] const char* __msg,
-	      [[maybe_unused]] const _Args&... __args)
+  __invoke_ub([[maybe_unused]] const char* __msg, [[maybe_unused]] const _Args&... __args)
   {
 #ifdef _GLIBCXX_DEBUG_UB
     __builtin_fprintf(stderr, __msg, __args...);
@@ -795,11 +793,14 @@ class _ExactBool
   const bool _M_data;
 
 public:
-  _GLIBCXX_SIMD_INTRINSIC constexpr _ExactBool(bool __b) : _M_data(__b) {}
+  _GLIBCXX_SIMD_INTRINSIC constexpr
+  _ExactBool(bool __b) : _M_data(__b) {}
 
   _ExactBool(int) = delete;
 
-  _GLIBCXX_SIMD_INTRINSIC constexpr operator bool() const { return _M_data; }
+  _GLIBCXX_SIMD_INTRINSIC constexpr
+  operator bool() const
+  { return _M_data; }
 };
 
 // }}}
@@ -1488,8 +1489,7 @@ template <typename _Tp>
 
 // else, use GNU-style builtin vector types
 template <typename _Tp, size_t _Np>
-  struct __vector_type_n<_Tp, _Np,
-			 enable_if_t<__is_vectorizable_v<_Tp> && _Np >= 2>>
+  struct __vector_type_n<_Tp, _Np, enable_if_t<__is_vectorizable_v<_Tp> && _Np >= 2>>
   {
     static constexpr size_t _S_Np2 = std::__bit_ceil(_Np * sizeof(_Tp));
 
@@ -1770,8 +1770,7 @@ template <typename _To, typename _From>
 // }}}
 // __to_intrin {{{
 template <typename _Tp, typename _TVT = _VectorTraits<_Tp>,
-	  typename _R
-	  = __intrinsic_type_t<typename _TVT::value_type, _TVT::_S_full_size>>
+	  typename _R = __intrinsic_type_t<typename _TVT::value_type, _TVT::_S_full_size>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __to_intrin(_Tp __x)
   {
@@ -1792,9 +1791,7 @@ template <typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 template <typename _Tp, typename... _Args>
   _GLIBCXX_SIMD_INTRINSIC constexpr __vector_type_t<_Tp, sizeof...(_Args)>
   __make_vector(const _Args&... __args)
-  {
-    return __vector_type_t<_Tp, sizeof...(_Args)>{static_cast<_Tp>(__args)...};
-  }
+  { return __vector_type_t<_Tp, sizeof...(_Args)>{static_cast<_Tp>(__args)...}; }
 
 // }}}
 // __vector_broadcast{{{
@@ -1813,10 +1810,7 @@ template <size_t _Np, typename _Tp>
   template <typename _Tp, size_t _Np, typename _Gp, size_t... _I>
   _GLIBCXX_SIMD_INTRINSIC constexpr __vector_type_t<_Tp, _Np>
   __generate_vector_impl(_Gp&& __gen, index_sequence<_I...>)
-  {
-    return __vector_type_t<_Tp, _Np>{
-      static_cast<_Tp>(__gen(_SizeConstant<_I>()))...};
-  }
+  { return __vector_type_t<_Tp, _Np>{ static_cast<_Tp>(__gen(_SizeConstant<_I>()))...}; }
 
 template <typename _V, typename _VVT = _VectorTraits<_V>, typename _Gp>
   _GLIBCXX_SIMD_INTRINSIC constexpr _V
@@ -2029,8 +2023,7 @@ template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
 // }}}
 // __concat{{{
 template <typename _Tp, typename _TVT = _VectorTraits<_Tp>,
-	  typename _R = __vector_type_t<typename _TVT::value_type,
-					_TVT::_S_full_size * 2>>
+	  typename _R = __vector_type_t<typename _TVT::value_type, _TVT::_S_full_size * 2>>
   constexpr _R
   __concat(_Tp a_, _Tp b_)
   {
@@ -2174,8 +2167,7 @@ template <int _Offset,
 	  int _SplitBy,
 	  typename _Tp,
 	  typename _TVT = _VectorTraits<_Tp>,
-	  typename _R = __vector_type_t<typename _TVT::value_type,
-			  _TVT::_S_full_size / _SplitBy>>
+	  typename _R = __vector_type_t<typename _TVT::value_type, _TVT::_S_full_size / _SplitBy>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __extract(_Tp __in)
   {
@@ -2221,8 +2213,7 @@ template <int _Offset,
 // }}}
 // __lo/__hi64[z]{{{
 template <typename _Tp,
-	  typename _R
-	  = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
+	  typename _R = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __lo64(_Tp __x)
   {
@@ -2232,8 +2223,7 @@ template <typename _Tp,
   }
 
 template <typename _Tp,
-	  typename _R
-	  = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
+	  typename _R = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __hi64(_Tp __x)
   {
@@ -2244,8 +2234,7 @@ template <typename _Tp,
   }
 
 template <typename _Tp,
-	  typename _R
-	  = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
+	  typename _R = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __hi64z([[maybe_unused]] _Tp __x)
   {
@@ -2356,18 +2345,15 @@ template <>
 // the following excludes bool via __is_vectorizable
 #if _GLIBCXX_SIMD_HAVE_SSE
 template <typename _Tp, size_t _Bytes>
-  struct __intrinsic_type<_Tp, _Bytes,
-			  enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 64>>
+  struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 64>>
   {
     static_assert(!is_same_v<_Tp, long double>,
 		  "no __intrinsic_type support for long double on x86");
 
-    static constexpr size_t _S_VBytes = _Bytes <= 16   ? 16
-					: _Bytes <= 32 ? 32
-						       : 64;
+    static constexpr size_t _S_VBytes = _Bytes <= 16 ? 16 : _Bytes <= 32 ? 32 : 64;
 
     using type [[__gnu__::__vector_size__(_S_VBytes)]]
-    = conditional_t<is_integral_v<_Tp>, long long int, _Tp>;
+      = conditional_t<is_integral_v<_Tp>, long long int, _Tp>;
   };
 #endif // _GLIBCXX_SIMD_HAVE_SSE
 
@@ -2413,16 +2399,19 @@ _GLIBCXX_SIMD_ARM_INTRIN(64, 2);
 #undef _GLIBCXX_SIMD_ARM_INTRIN
 
 template <typename _Tp, size_t _Bytes>
-  struct __intrinsic_type<_Tp, _Bytes,
-			  enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
+  struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
   {
     static constexpr int _SVecBytes = _Bytes <= 8 ? 8 : 16;
+
     using _Ip = __int_for_sizeof_t<_Tp>;
+
     using _Up = conditional_t<
       is_floating_point_v<_Tp>, _Tp,
       conditional_t<is_unsigned_v<_Tp>, make_unsigned_t<_Ip>, _Ip>>;
+
     static_assert(!is_same_v<_Tp, _Up> || _SVecBytes != _Bytes,
 		  "should use explicit specialization above");
+
     using type = typename __intrinsic_type<_Up, _SVecBytes>::type;
   };
 #endif // _GLIBCXX_SIMD_HAVE_NEON
@@ -2457,18 +2446,20 @@ _GLIBCXX_SIMD_PPC_INTRIN(unsigned long long);
 #undef _GLIBCXX_SIMD_PPC_INTRIN
 
 template <typename _Tp, size_t _Bytes>
-  struct __intrinsic_type<_Tp, _Bytes,
-			  enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
+  struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
   {
     static constexpr bool _S_is_ldouble = is_same_v<_Tp, long double>;
+
     // allow _Tp == long double with -mlong-double-64
     static_assert(!(_S_is_ldouble && sizeof(long double) > sizeof(double)),
 		  "no __intrinsic_type support for 128-bit floating point on PowerPC");
+
 #ifndef __VSX__
     static_assert(!(is_same_v<_Tp, double>
 		    || (_S_is_ldouble && sizeof(long double) == sizeof(double))),
 		  "no __intrinsic_type support for 64-bit floating point on PowerPC w/o VSX");
 #endif
+
     using type =
       typename __intrinsic_type_impl<
 		 conditional_t<is_floating_point_v<_Tp>,
@@ -2489,22 +2480,29 @@ template <size_t _Width>
     static constexpr size_t _S_full_size = sizeof(_BuiltinType) * __CHAR_BIT__;
 
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper<bool, _S_full_size>
-    __as_full_vector() const { return _M_data; }
+    __as_full_vector() const
+    { return _M_data; }
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper() = default;
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper() = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_BuiltinType __k)
-      : _M_data(__k) {};
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(_BuiltinType __k) : _M_data(__k) {};
 
-    _GLIBCXX_SIMD_INTRINSIC operator const _BuiltinType&() const
+    _GLIBCXX_SIMD_INTRINSIC
+    operator const _BuiltinType&() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC operator _BuiltinType&()
+    _GLIBCXX_SIMD_INTRINSIC
+    operator _BuiltinType&()
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC _BuiltinType __intrin() const
+    _GLIBCXX_SIMD_INTRINSIC _BuiltinType
+    __intrin() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator[](size_t __i) const
+    _GLIBCXX_SIMD_INTRINSIC constexpr value_type
+    operator[](size_t __i) const
     { return _M_data & (_BuiltinType(1) << __i); }
 
     template <size_t __i>
@@ -2512,7 +2510,8 @@ template <size_t _Width>
       operator[](_SizeConstant<__i>) const
       { return _M_data & (_BuiltinType(1) << __i); }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr void _M_set(size_t __i, value_type __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
+    _M_set(size_t __i, value_type __x)
     {
       if (__x)
 	_M_data |= (_BuiltinType(1) << __i);
@@ -2520,11 +2519,12 @@ template <size_t _Width>
 	_M_data &= ~(_BuiltinType(1) << __i);
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop() const
     { return __builtin_constant_p(_M_data); }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_none_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_none_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2536,7 +2536,8 @@ template <size_t _Width>
       return false;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_all_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_all_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2558,10 +2559,11 @@ template <bool _MustZeroInitPadding, typename _BuiltinType>
 template <typename _BuiltinType>
   struct _SimdWrapperBase<false, _BuiltinType> // no padding or no SNaNs
   {
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase() = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase(_BuiltinType __init)
-      : _M_data(__init)
-    {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase() = default;
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase(_BuiltinType __init) : _M_data(__init) {}
 
     _BuiltinType _M_data;
   };
@@ -2570,10 +2572,11 @@ template <typename _BuiltinType>
   struct _SimdWrapperBase<true, _BuiltinType> // with padding that needs to
 					      // never become SNaN
   {
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase() : _M_data() {}
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase(_BuiltinType __init)
-      : _M_data(__init)
-    {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase() : _M_data() {}
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase(_BuiltinType __init) : _M_data(__init) {}
 
     _BuiltinType _M_data;
   };
@@ -2612,24 +2615,33 @@ template <typename _Tp, size_t _Width>
     __as_full_vector() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(initializer_list<_Tp> __init)
-      : _Base(__generate_from_n_evaluations<_Width, _BuiltinType>(
-	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __init.begin()[__i.value]; })) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(initializer_list<_Tp> __init)
+    : _Base(__generate_from_n_evaluations<_Width, _BuiltinType>(
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __init.begin()[__i.value];
+	      })) {}
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper() = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(const _SimdWrapper&)
-      = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_SimdWrapper&&) = default;
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper() = default;
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(const _SimdWrapper&) = default;
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(_SimdWrapper&&) = default;
 
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper&
     operator=(const _SimdWrapper&) = default;
+
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper&
     operator=(_SimdWrapper&&) = default;
 
     template <typename _V, typename = enable_if_t<disjunction_v<
 			     is_same<_V, __vector_type_t<_Tp, _Width>>,
 			     is_same<_V, __intrinsic_type_t<_Tp, _Width>>>>>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_V __x)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdWrapper(_V __x)
       // __vector_bitcast can convert e.g. __m128 to __vector(2) float
       : _Base(__vector_bitcast<_Tp, _Width>(__x)) {}
 
@@ -2644,27 +2656,34 @@ template <typename _Tp, size_t _Width>
 		 { return _M_data[int(__i)]; });
       }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr operator const _BuiltinType&() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    operator const _BuiltinType&() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr operator _BuiltinType&()
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    operator _BuiltinType&()
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp operator[](size_t __i) const
+    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
+    operator[](size_t __i) const
     { return _M_data[__i]; }
 
     template <size_t __i>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _Tp operator[](_SizeConstant<__i>) const
+      _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
+      operator[](_SizeConstant<__i>) const
       { return _M_data[__i]; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr void _M_set(size_t __i, _Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
+    _M_set(size_t __i, _Tp __x)
     { _M_data[__i] = __x; }
 
     _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    constexpr bool
+    _M_is_constprop() const
     { return __builtin_constant_p(_M_data); }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_none_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_none_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2685,7 +2704,8 @@ template <typename _Tp, size_t _Width>
       return false;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_all_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_all_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2883,22 +2903,14 @@ template <typename _Tp, typename _V, typename = void>
   struct rebind_simd;
 
 template <typename _Tp, typename _Up, typename _Abi>
-  struct rebind_simd<
-    _Tp, simd<_Up, _Abi>,
-    void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
-  {
-    using type
-      = simd<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>;
-  };
+  struct rebind_simd<_Tp, simd<_Up, _Abi>,
+		     void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
+  { using type = simd<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; };
 
 template <typename _Tp, typename _Up, typename _Abi>
-  struct rebind_simd<
-    _Tp, simd_mask<_Up, _Abi>,
-    void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
-  {
-    using type
-      = simd_mask<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>;
-  };
+  struct rebind_simd<_Tp, simd_mask<_Up, _Abi>,
+		     void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
+  { using type = simd_mask<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; };
 
 template <typename _Tp, typename _V>
   using rebind_simd_t = typename rebind_simd<_Tp, _V>::type;
@@ -2908,13 +2920,11 @@ template <int _Np, typename _V, typename = void>
   struct resize_simd;
 
 template <int _Np, typename _Tp, typename _Abi>
-  struct resize_simd<_Np, simd<_Tp, _Abi>,
-		     void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
+  struct resize_simd<_Np, simd<_Tp, _Abi>, void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
   { using type = simd<_Tp, simd_abi::deduce_t<_Tp, _Np, _Abi>>; };
 
 template <int _Np, typename _Tp, typename _Abi>
-  struct resize_simd<_Np, simd_mask<_Tp, _Abi>,
-		     void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
+  struct resize_simd<_Np, simd_mask<_Tp, _Abi>, void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
   { using type = simd_mask<_Tp, simd_abi::deduce_t<_Tp, _Np, _Abi>>; };
 
 template <int _Np, typename _V>
@@ -2963,13 +2973,11 @@ template <typename _Tp, size_t _Np>
 
 // casts [simd.casts] {{{1
 // static_simd_cast {{{2
-template <typename _Tp, typename _Up, typename _Ap, bool = is_simd_v<_Tp>,
-	  typename = void>
+template <typename _Tp, typename _Up, typename _Ap, bool = is_simd_v<_Tp>, typename = void>
   struct __static_simd_cast_return_type;
 
 template <typename _Tp, typename _A0, typename _Up, typename _Ap>
-  struct __static_simd_cast_return_type<simd_mask<_Tp, _A0>, _Up, _Ap, false,
-					void>
+  struct __static_simd_cast_return_type<simd_mask<_Tp, _A0>, _Up, _Ap, false, void>
   : __static_simd_cast_return_type<simd<_Tp, _A0>, _Up, _Ap> {};
 
 template <typename _Tp, typename _Up, typename _Ap>
@@ -3284,6 +3292,7 @@ template <typename _M, typename _Tp>
 
   public:
     const_where_expression(const const_where_expression&) = delete;
+
     const_where_expression& operator=(const const_where_expression&) = delete;
 
     _GLIBCXX_SIMD_INTRINSIC const_where_expression(const _M& __kk, const _Tp& dd)
@@ -3328,8 +3337,8 @@ template <typename _Tp>
     struct _Wrapper { using value_type = _V; };
 
   protected:
-    using value_type =
-      typename conditional_t<is_arithmetic_v<_V>, _Wrapper, _V>::value_type;
+    using value_type
+      = typename conditional_t<is_arithmetic_v<_V>, _Wrapper, _V>::value_type;
 
     _GLIBCXX_SIMD_INTRINSIC friend const _M&
     __get_mask(const const_where_expression& __x)
@@ -3426,32 +3435,32 @@ template <typename _M, typename _Tp>
     _GLIBCXX_SIMD_OP_(>>, _S_shift_right);
 #undef _GLIBCXX_SIMD_OP_
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++() &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator++() &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__increment>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++(int) &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator++(int) &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__increment>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--() &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator--() &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--(int) &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator--(int) &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value));
     }
 
     // intentionally hides const_where_expression::copy_from
@@ -3459,15 +3468,15 @@ template <typename _M, typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC void
       copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) &&
       {
-	__data(_M_value)
-	  = _Impl::_S_masked_load(__data(_M_value), __data(_M_k),
-				  _Flags::template _S_apply<_Tp>(__mem));
+	__data(_M_value) = _Impl::_S_masked_load(__data(_M_value), __data(_M_k),
+						 _Flags::template _S_apply<_Tp>(__mem));
       }
   };
 
 // where_expression<bool, T> {{{2
 template <typename _Tp>
-  class where_expression<bool, _Tp> : public const_where_expression<bool, _Tp>
+  class where_expression<bool, _Tp>
+  : public const_where_expression<bool, _Tp>
   {
     using _M = bool;
     using typename const_where_expression<_M, _Tp>::value_type;
@@ -3478,12 +3487,14 @@ template <typename _Tp>
     where_expression(const where_expression&) = delete;
     where_expression& operator=(const where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC where_expression(const _M& __kk, _Tp& dd)
-      : const_where_expression<_M, _Tp>(__kk, dd) {}
+    _GLIBCXX_SIMD_INTRINSIC
+    where_expression(const _M& __kk, _Tp& dd)
+    : const_where_expression<_M, _Tp>(__kk, dd) {}
 
 #define _GLIBCXX_SIMD_OP_(__op)                                                \
     template <typename _Up>                                                    \
-      _GLIBCXX_SIMD_INTRINSIC void operator __op(_Up&& __x)&&                  \
+      _GLIBCXX_SIMD_INTRINSIC void                                             \
+      operator __op(_Up&& __x)&&                                               \
       { if (_M_k) _M_value __op static_cast<_Up&&>(__x); }
 
     _GLIBCXX_SIMD_OP_(=)
@@ -3499,16 +3510,20 @@ template <typename _Tp>
     _GLIBCXX_SIMD_OP_(>>=)
   #undef _GLIBCXX_SIMD_OP_
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++() &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator++() &&
     { if (_M_k) ++_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++(int) &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator++(int) &&
     { if (_M_k) ++_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--() &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator--() &&
     { if (_M_k) --_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--(int) &&
+    _GLIBCXX_SIMD_INTRINSIC void
+    operator--(int) &&
     { if (_M_k) --_M_value; }
 
     // intentionally hides const_where_expression::copy_from
@@ -3526,23 +3541,20 @@ template <typename _Tp, typename _Ap>
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC
-    const_where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
-    where(const typename simd<_Tp, _Ap>::mask_type& __k,
-	  const simd<_Tp, _Ap>& __value)
+  const_where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
+  where(const typename simd<_Tp, _Ap>::mask_type& __k, const simd<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC
-    where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
-    where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k,
-	  simd_mask<_Tp, _Ap>& __value)
+  where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
+  where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k, simd_mask<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC
-    const_where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
-    where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k,
-	  const simd_mask<_Tp, _Ap>& __value)
+  const_where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
+  where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k, const simd_mask<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp>
@@ -3555,11 +3567,11 @@ template <typename _Tp>
   where(_ExactBool __k, const _Tp& __value)
   { return {__k, __value}; }
 
-  template <typename _Tp, typename _Ap>
-    void where(bool __k, simd<_Tp, _Ap>& __value) = delete;
+template <typename _Tp, typename _Ap>
+  void where(bool __k, simd<_Tp, _Ap>& __value) = delete;
 
-  template <typename _Tp, typename _Ap>
-    void where(bool __k, const simd<_Tp, _Ap>& __value) = delete;
+template <typename _Tp, typename _Ap>
+  void where(bool __k, const simd<_Tp, _Ap>& __value) = delete;
 
 // proposed mask iterations {{{1
 namespace __proposed {
@@ -3576,10 +3588,12 @@ template <size_t _Np>
       size_t __mask;
       size_t __bit;
 
-      _GLIBCXX_SIMD_INTRINSIC void __next_bit()
+      _GLIBCXX_SIMD_INTRINSIC void
+      __next_bit()
       { __bit = __builtin_ctzl(__mask); }
 
-      _GLIBCXX_SIMD_INTRINSIC void __reset_lsb()
+      _GLIBCXX_SIMD_INTRINSIC void
+      __reset_lsb()
       {
 	// 01100100 - 1 = 01100011
 	__mask &= (__mask - 1);
@@ -3591,20 +3605,24 @@ template <size_t _Np>
       iterator(const iterator&) = default;
       iterator(iterator&&) = default;
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE size_t operator->() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE size_t
+      operator->() const
       { return __bit; }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE size_t operator*() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE size_t
+      operator*() const
       { return __bit; }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE iterator& operator++()
+      _GLIBCXX_SIMD_ALWAYS_INLINE iterator&
+      operator++()
       {
 	__reset_lsb();
 	__next_bit();
 	return *this;
       }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE iterator operator++(int)
+      _GLIBCXX_SIMD_ALWAYS_INLINE iterator
+      operator++(int)
       {
 	iterator __tmp = *this;
 	__reset_lsb();
@@ -3612,17 +3630,21 @@ template <size_t _Np>
 	return __tmp;
       }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE bool operator==(const iterator& __rhs) const
+      _GLIBCXX_SIMD_ALWAYS_INLINE bool
+      operator==(const iterator& __rhs) const
       { return __mask == __rhs.__mask; }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE bool operator!=(const iterator& __rhs) const
+      _GLIBCXX_SIMD_ALWAYS_INLINE bool
+      operator!=(const iterator& __rhs) const
       { return __mask != __rhs.__mask; }
     };
 
-    iterator begin() const
+    iterator
+    begin() const
     { return __bits.to_ullong(); }
 
-    iterator end() const
+    iterator
+    end() const
     { return 0; }
   };
 
@@ -3637,15 +3659,13 @@ template <typename _Tp, typename _Ap>
 // reductions [simd.reductions] {{{1
 template <typename _Tp, typename _Abi, typename _BinaryOperation = plus<>>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp
-  reduce(const simd<_Tp, _Abi>& __v,
-	 _BinaryOperation __binary_op = _BinaryOperation())
+  reduce(const simd<_Tp, _Abi>& __v, _BinaryOperation __binary_op = _BinaryOperation())
   { return _Abi::_SimdImpl::_S_reduce(__v, __binary_op); }
 
 template <typename _M, typename _V, typename _BinaryOperation = plus<>>
   _GLIBCXX_SIMD_INTRINSIC typename _V::value_type
   reduce(const const_where_expression<_M, _V>& __x,
-	 typename _V::value_type __identity_element,
-	 _BinaryOperation __binary_op)
+	 typename _V::value_type __identity_element, _BinaryOperation __binary_op)
   {
     if (__builtin_expect(none_of(__get_mask(__x)), false))
       return __identity_element;
@@ -3684,16 +3704,12 @@ template <typename _M, typename _V>
 template <typename _Tp, typename _Abi>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp
   hmin(const simd<_Tp, _Abi>& __v) noexcept
-  {
-    return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Minimum());
-  }
+  { return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Minimum()); }
 
 template <typename _Tp, typename _Abi>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp
   hmax(const simd<_Tp, _Abi>& __v) noexcept
-  {
-    return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Maximum());
-  }
+  { return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Maximum()); }
 
 template <typename _M, typename _V>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
@@ -3761,8 +3777,7 @@ template <typename _Tp, typename _Ap>
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
-  clamp(const simd<_Tp, _Ap>& __v, const simd<_Tp, _Ap>& __lo,
-	const simd<_Tp, _Ap>& __hi)
+  clamp(const simd<_Tp, _Ap>& __v, const simd<_Tp, _Ap>& __lo, const simd<_Tp, _Ap>& __hi)
   {
     using _Impl = typename _Ap::_SimdImpl;
     return {__private_init,
@@ -3783,8 +3798,7 @@ template <int _Index, int _Total, int _Combine = 1, typename _Tp, size_t _Np>
   _SimdWrapper<_Tp, _Np / _Total * _Combine>
   __extract_part(const _SimdWrapper<_Tp, _Np> __x);
 
-template <int _Index, int _Parts, int _Combine = 1, typename _Tp, typename _A0,
-	  typename... _As>
+template <int _Index, int _Parts, int _Combine = 1, typename _Tp, typename _A0, typename... _As>
   _GLIBCXX_SIMD_INTRINSIC auto
   __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x);
 
@@ -3794,7 +3808,8 @@ template <size_t _V0, size_t... _Values>
   struct _SizeList
   {
     template <size_t _I>
-      static constexpr size_t _S_at(_SizeConstant<_I> = {})
+      static constexpr size_t
+      _S_at(_SizeConstant<_I> = {})
       {
 	if constexpr (_I == 0)
 	  return _V0;
@@ -3803,7 +3818,8 @@ template <size_t _V0, size_t... _Values>
       }
 
     template <size_t _I>
-      static constexpr auto _S_before(_SizeConstant<_I> = {})
+      static constexpr auto
+      _S_before(_SizeConstant<_I> = {})
       {
 	if constexpr (_I == 0)
 	  return _SizeConstant<0>();
@@ -3813,7 +3829,8 @@ template <size_t _V0, size_t... _Values>
       }
 
     template <size_t _Np>
-      static constexpr auto _S_pop_front(_SizeConstant<_Np> = {})
+      static constexpr auto
+      _S_pop_front(_SizeConstant<_Np> = {})
       {
 	if constexpr (_Np == 0)
 	  return _SizeList();
@@ -3965,8 +3982,7 @@ template <typename _V, typename _Ap,
 // }}}
 // split<simd_mask>(simd_mask) {{{
 template <typename _V, typename _Ap,
-	  size_t _Parts
-	  = simd_size_v<typename _V::simd_type::value_type, _Ap> / _V::size()>
+	  size_t _Parts = simd_size_v<typename _V::simd_type::value_type, _Ap> / _V::size()>
   enable_if_t<is_simd_mask_v<_V> && simd_size_v<typename
     _V::simd_type::value_type, _Ap> == _Parts * _V::size(), array<_V, _Parts>>
   split(const simd_mask<typename _V::simd_type::value_type, _Ap>& __x)
@@ -4131,8 +4147,7 @@ template <size_t _I, typename _Tp, typename _Ap, typename... _As>
 // __store_pack_of_simd {{{
 template <typename _Tp, typename _A0, typename... _As>
   _GLIBCXX_SIMD_INTRINSIC void
-  __store_pack_of_simd(char* __mem, const simd<_Tp, _A0>& __x0,
-		       const simd<_Tp, _As>&... __xs)
+  __store_pack_of_simd(char* __mem, const simd<_Tp, _A0>& __x0, const simd<_Tp, _As>&... __xs)
   {
     constexpr size_t __n_bytes = sizeof(_Tp) * simd_size_v<_Tp, _A0>;
     __builtin_memcpy(__mem, &__data(__x0), __n_bytes);
@@ -4188,7 +4203,8 @@ template <typename _Up, typename _Accessor = _Up,
     int _M_index;
     _Up& _M_obj;
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _ValueType _M_read() const noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr _ValueType
+    _M_read() const noexcept
     {
       if constexpr (is_arithmetic_v<_Up>)
 	return _M_obj;
@@ -4197,7 +4213,8 @@ template <typename _Up, typename _Accessor = _Up,
     }
 
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC constexpr void _M_write(_Tp&& __x) const
+      _GLIBCXX_SIMD_INTRINSIC constexpr void
+      _M_write(_Tp&& __x) const
       { _Accessor::_S_set(_M_obj, _M_index, static_cast<_Tp&&>(__x)); }
 
   public:
@@ -4207,32 +4224,32 @@ template <typename _Up, typename _Accessor = _Up,
 
     using value_type = _ValueType;
 
-    _GLIBCXX_SIMD_INTRINSIC _SmartReference(const _SmartReference&) = delete;
+    _GLIBCXX_SIMD_INTRINSIC
+    _SmartReference(const _SmartReference&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr operator value_type() const noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    operator value_type() const noexcept
     { return _M_read(); }
 
-    template <typename _Tp,
-	      typename
-	      = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, value_type>>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator=(_Tp&& __x) &&
+    template <typename _Tp, typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, value_type>>
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference
+      operator=(_Tp&& __x) &&
       {
 	_M_write(static_cast<_Tp&&>(__x));
 	return {_M_obj, _M_index};
       }
 
-#define _GLIBCXX_SIMD_OP_(__op)                                                \
-    template <typename _Tp,                                                    \
-	      typename _TT                                                     \
-	      = decltype(declval<value_type>() __op declval<_Tp>()),           \
-	      typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, _TT>,    \
-	      typename = _ValuePreservingOrInt<_TT, value_type>>               \
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference                        \
-      operator __op##=(_Tp&& __x) &&                                           \
-      {                                                                        \
-	const value_type& __lhs = _M_read();                                   \
-	_M_write(__lhs __op __x);                                              \
-	return {_M_obj, _M_index};                                             \
+#define _GLIBCXX_SIMD_OP_(__op)                                                   \
+    template <typename _Tp,                                                       \
+	      typename _TT = decltype(declval<value_type>() __op declval<_Tp>()), \
+	      typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, _TT>,       \
+	      typename = _ValuePreservingOrInt<_TT, value_type>>                  \
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference                           \
+      operator __op##=(_Tp&& __x) &&                                              \
+      {                                                                           \
+	const value_type& __lhs = _M_read();                                      \
+	_M_write(__lhs __op __x);                                                 \
+	return {_M_obj, _M_index};                                                \
       }
     _GLIBCXX_SIMD_ALL_ARITHMETICS(_GLIBCXX_SIMD_OP_);
     _GLIBCXX_SIMD_ALL_SHIFTS(_GLIBCXX_SIMD_OP_);
@@ -4240,9 +4257,9 @@ template <typename _Up, typename _Accessor = _Up,
 #undef _GLIBCXX_SIMD_OP_
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(++declval<conditional_t<true, value_type, _Tp>&>())>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator++() &&
+	      typename = decltype(++declval<conditional_t<true, value_type, _Tp>&>())>
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference
+      operator++() &&
       {
 	value_type __x = _M_read();
 	_M_write(++__x);
@@ -4250,9 +4267,9 @@ template <typename _Up, typename _Accessor = _Up,
       }
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(declval<conditional_t<true, value_type, _Tp>&>()++)>
-      _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator++(int) &&
+	      typename = decltype(declval<conditional_t<true, value_type, _Tp>&>()++)>
+      _GLIBCXX_SIMD_INTRINSIC constexpr value_type
+      operator++(int) &&
       {
 	const value_type __r = _M_read();
 	value_type __x = __r;
@@ -4261,9 +4278,9 @@ template <typename _Up, typename _Accessor = _Up,
       }
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(--declval<conditional_t<true, value_type, _Tp>&>())>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator--() &&
+	      typename = decltype(--declval<conditional_t<true, value_type, _Tp>&>())>
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference
+      operator--() &&
       {
 	value_type __x = _M_read();
 	_M_write(--__x);
@@ -4271,9 +4288,9 @@ template <typename _Up, typename _Accessor = _Up,
       }
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(declval<conditional_t<true, value_type, _Tp>&>()--)>
-      _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator--(int) &&
+	      typename = decltype(declval<conditional_t<true, value_type, _Tp>&>()--)>
+      _GLIBCXX_SIMD_INTRINSIC constexpr value_type
+      operator--(int) &&
       {
 	const value_type __r = _M_read();
 	value_type __x = __r;
@@ -4349,7 +4366,8 @@ template <int _Bytes>
 template <template <int> class _Abi, int _Bytes, typename _Tp>
   struct __find_next_valid_abi
   {
-    static constexpr auto _S_choose()
+    static constexpr auto
+    _S_choose()
     {
       constexpr int _NextBytes = std::__bit_ceil(_Bytes) / 2;
       using _NextAbi = _Abi<_NextBytes>;
@@ -4393,7 +4411,8 @@ template <template <int> class _A0, template <int> class... _Rest>
 	typename _AbiList<_Rest...>::template _FirstValidAbi<_Tp, _Np>>;
 
     template <typename _Tp, int _Np>
-      static constexpr auto _S_determine_best_abi()
+      static constexpr auto
+      _S_determine_best_abi()
       {
 	static_assert(_Np >= 1);
 	constexpr int _Bytes = sizeof(_Tp) * _Np;
@@ -4556,17 +4575,15 @@ template <typename _Tp, typename _Abi>
     template <typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE
       simd_mask(const value_type* __mem, _Flags)
-      : _M_data(_Impl::template _S_load<_Ip>(
-	_Flags::template _S_apply<simd_mask>(__mem))) {}
+      : _M_data(_Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem))) {}
 
     template <typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE
       simd_mask(const value_type* __mem, simd_mask __k, _Flags)
       : _M_data{}
       {
-	_M_data
-	  = _Impl::_S_masked_load(_M_data, __k._M_data,
-				  _Flags::template _S_apply<simd_mask>(__mem));
+	_M_data = _Impl::_S_masked_load(_M_data, __k._M_data,
+					_Flags::template _S_apply<simd_mask>(__mem));
       }
 
     // }}}
@@ -4574,10 +4591,7 @@ template <typename _Tp, typename _Abi>
     template <typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE void
       copy_from(const value_type* __mem, _Flags)
-      {
-	_M_data = _Impl::template _S_load<_Ip>(
-	  _Flags::template _S_apply<simd_mask>(__mem));
-      }
+      { _M_data = _Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem)); }
 
     // }}}
     // stores [simd_mask.store] {{{
@@ -4618,8 +4632,7 @@ template <typename _Tp, typename _Abi>
   #ifdef _GLIBCXX_SIMD_ENABLE_IMPLICIT_MASK_CAST
     // simd_mask<int> && simd_mask<uint> needs disambiguation
     template <typename _Up, typename _A2,
-	      typename
-	      = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
+	      typename = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
       _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
       operator&&(const simd_mask& __x, const simd_mask<_Up, _A2>& __y)
       {
@@ -4628,8 +4641,7 @@ template <typename _Tp, typename _Abi>
       }
 
     template <typename _Up, typename _A2,
-	      typename
-	      = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
+	      typename = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
       _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
       operator||(const simd_mask& __x, const simd_mask<_Up, _A2>& __y)
       {
@@ -4640,15 +4652,11 @@ template <typename _Tp, typename _Abi>
 
     _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
     operator&&(const simd_mask& __x, const simd_mask& __y)
-    {
-      return {__private_init, _Impl::_S_logical_and(__x._M_data, __y._M_data)};
-    }
+    { return {__private_init, _Impl::_S_logical_and(__x._M_data, __y._M_data)}; }
 
     _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
     operator||(const simd_mask& __x, const simd_mask& __y)
-    {
-      return {__private_init, _Impl::_S_logical_or(__x._M_data, __y._M_data)};
-    }
+    { return {__private_init, _Impl::_S_logical_or(__x._M_data, __y._M_data)}; }
 
     _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
     operator&(const simd_mask& __x, const simd_mask& __y)
@@ -4714,8 +4722,7 @@ template <typename _Tp, typename _Abi>
     // }}}
     // bitset_init ctor {{{
     _GLIBCXX_SIMD_INTRINSIC simd_mask(_BitsetInit, bitset<size()> __init)
-    : _M_data(
-	_Impl::_S_from_bitmask(_SanitizedBitMask<size()>(__init), _S_type_tag))
+    : _M_data(_Impl::_S_from_bitmask(_SanitizedBitMask<size()>(__init), _S_type_tag))
     {}
 
     // }}}
@@ -4727,8 +4734,7 @@ template <typename _Tp, typename _Abi>
     struct _CvtProxy
     {
       template <typename _Up, typename _A2,
-		typename
-		= enable_if_t<simd_size_v<_Up, _A2> == simd_size_v<_Tp, _Abi>>>
+		typename = enable_if_t<simd_size_v<_Up, _A2> == simd_size_v<_Tp, _Abi>>>
 	_GLIBCXX_SIMD_ALWAYS_INLINE
 	operator simd_mask<_Up, _A2>() &&
 	{
@@ -5419,26 +5425,17 @@ namespace __float_bitwise_operators { //{{{
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
   operator^(const simd<_Tp, _Ap>& __a, const simd<_Tp, _Ap>& __b)
-  {
-    return {__private_init,
-	    _Ap::_SimdImpl::_S_bit_xor(__data(__a), __data(__b))};
-  }
+  { return {__private_init, _Ap::_SimdImpl::_S_bit_xor(__data(__a), __data(__b))}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
   operator|(const simd<_Tp, _Ap>& __a, const simd<_Tp, _Ap>& __b)
-  {
-    return {__private_init,
-	    _Ap::_SimdImpl::_S_bit_or(__data(__a), __data(__b))};
-  }
+  { return {__private_init, _Ap::_SimdImpl::_S_bit_or(__data(__a), __data(__b))}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
   operator&(const simd<_Tp, _Ap>& __a, const simd<_Tp, _Ap>& __b)
-  {
-    return {__private_init,
-	    _Ap::_SimdImpl::_S_bit_and(__data(__a), __data(__b))};
-  }
+  { return {__private_init, _Ap::_SimdImpl::_S_bit_and(__data(__a), __data(__b))}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
diff --git a/libstdc++-v3/include/experimental/bits/simd_builtin.h b/libstdc++-v3/include/experimental/bits/simd_builtin.h
index 71469483276..f7a75bf28ce 100644
--- a/libstdc++-v3/include/experimental/bits/simd_builtin.h
+++ b/libstdc++-v3/include/experimental/bits/simd_builtin.h
@@ -836,22 +836,19 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     // _SimdBase / base class for simd, providing extra conversions {{{
     struct _SimdBase2
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
-      {
-	return __to_intrin(static_cast<const simd<_Tp, _Abi>*>(this)->_M_data);
-      }
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __vector_type_t<_Tp, _Np>() const
-      {
-	return static_cast<const simd<_Tp, _Abi>*>(this)->_M_data.__builtin();
-      }
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
+      { return __to_intrin(static_cast<const simd<_Tp, _Abi>*>(this)->_M_data); }
+
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __vector_type_t<_Tp, _Np>() const
+      { return static_cast<const simd<_Tp, _Abi>*>(this)->_M_data.__builtin(); }
     };
 
     struct _SimdBase1
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
       { return __data(*static_cast<const simd<_Tp, _Abi>*>(this)); }
     };
 
@@ -863,23 +860,19 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     // _MaskBase {{{
     struct _MaskBase2
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
-      {
-	return static_cast<const simd_mask<_Tp, _Abi>*>(this)
-	  ->_M_data.__intrin();
-      }
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __vector_type_t<_Tp, _Np>() const
-      {
-	return static_cast<const simd_mask<_Tp, _Abi>*>(this)->_M_data._M_data;
-      }
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
+      { return static_cast<const simd_mask<_Tp, _Abi>*>(this) ->_M_data.__intrin(); }
+
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __vector_type_t<_Tp, _Np>() const
+      { return static_cast<const simd_mask<_Tp, _Abi>*>(this)->_M_data._M_data; }
     };
 
     struct _MaskBase1
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
       { return __data(*static_cast<const simd_mask<_Tp, _Abi>*>(this)); }
     };
 
@@ -898,6 +891,7 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     public:
       _GLIBCXX_SIMD_ALWAYS_INLINE
       _MaskCastType(_Up __x) : _M_data(__x) {}
+
       _GLIBCXX_SIMD_ALWAYS_INLINE
       operator _MaskMember() const { return _M_data; }
     };
@@ -913,6 +907,7 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     public:
       _GLIBCXX_SIMD_ALWAYS_INLINE
       _SimdCastType1(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {}
+
       _GLIBCXX_SIMD_ALWAYS_INLINE
       operator _SimdMember() const { return _M_data; }
     };
@@ -926,8 +921,10 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     public:
       _GLIBCXX_SIMD_ALWAYS_INLINE
       _SimdCastType2(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {}
+
       _GLIBCXX_SIMD_ALWAYS_INLINE
       _SimdCastType2(_Bp __b) : _M_data(__b) {}
+
       _GLIBCXX_SIMD_ALWAYS_INLINE
       operator _SimdMember() const { return _M_data; }
     };
@@ -1039,16 +1036,13 @@ template <int _UsedBytes>
       }
 
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr __intrinsic_type_t<_Tp,
-								  _S_size<_Tp>>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr __intrinsic_type_t<_Tp, _S_size<_Tp>>
       _S_implicit_mask_intrin()
-      {
-	return __to_intrin(
-	  __vector_bitcast<_Tp>(_S_implicit_mask<_Tp>()._M_data));
-      }
+      { return __to_intrin(__vector_bitcast<_Tp>(_S_implicit_mask<_Tp>()._M_data)); }
 
     template <typename _TW, typename _TVT = _VectorTraits<_TW>>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr _TW _S_masked(_TW __x)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _TW
+      _S_masked(_TW __x)
       {
 	using _Tp = typename _TVT::value_type;
 	if constexpr (!_MaskMember<_Tp>::_S_is_partial)
@@ -1170,8 +1164,7 @@ template <int _UsedBytes>
       { return __implicit_mask_n<_S_size<_Tp>>(); }
 
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr __bool_storage_member_type_t<
-	_S_size<_Tp>>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr __bool_storage_member_type_t<_S_size<_Tp>>
       _S_implicit_mask_intrin()
       { return __implicit_mask_n<_S_size<_Tp>>(); }
 
@@ -1303,7 +1296,8 @@ struct _CommonImplBuiltin
   // }}}
   // _S_store {{{
   template <size_t _ReqBytes = 0, typename _TV>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_TV __x, void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_TV __x, void* __addr)
     {
       constexpr size_t _Bytes = _ReqBytes == 0 ? sizeof(__x) : _ReqBytes;
       static_assert(sizeof(__x) >= _Bytes);
@@ -1339,8 +1333,8 @@ struct _CommonImplBuiltin
     }
 
   template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __x,
-						 void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_SimdWrapper<_Tp, _Np> __x, void* __addr)
     { _S_store<_Np * sizeof(_Tp)>(__x._M_data, __addr); }
 
   // }}}
@@ -1447,8 +1441,8 @@ template <typename _Abi, typename>
 
     // _S_generator {{{2
     template <typename _Fp, typename _Tp>
-      inline static constexpr _SimdMember<_Tp> _S_generator(_Fp&& __gen,
-							    _TypeTag<_Tp>)
+      inline static constexpr _SimdMember<_Tp>
+      _S_generator(_Fp&& __gen, _TypeTag<_Tp>)
       {
 	return __generate_vector<_Tp, _S_full_size<_Tp>>(
 		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1569,8 +1563,7 @@ template <typename _Abi, typename>
     // _S_masked_store_nocvt {{{2
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem,
-			    _MaskMember<_Tp> __k)
+      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem, _MaskMember<_Tp> __k)
       {
 	_BitOps::_S_bit_iteration(
 	  _MaskImpl::_S_to_bits(__k),
@@ -1583,8 +1576,7 @@ template <typename _Abi, typename>
     template <typename _TW, typename _TVT = _VectorTraits<_TW>,
 	      typename _Tp = typename _TVT::value_type, typename _Up>
       static inline void
-      _S_masked_store(const _TW __v, _Up* __mem, const _MaskMember<_Tp> __k)
-	noexcept
+      _S_masked_store(const _TW __v, _Up* __mem, const _MaskMember<_Tp> __k) noexcept
       {
 	constexpr size_t _TV_size = _S_size<_Tp>;
 	[[maybe_unused]] const auto __vi = __to_intrin(__v);
@@ -1946,7 +1938,8 @@ template <typename _Abi, typename>
     // frexp, modf and copysign implemented in simd_math.h
 #define _GLIBCXX_SIMD_MATH_FALLBACK(__name)                                    \
     template <typename _Tp, typename... _More>                                 \
-      static _Tp _S_##__name(const _Tp& __x, const _More&... __more)           \
+      static _Tp                                                               \
+      _S_##__name(const _Tp& __x, const _More&... __more)                      \
       {                                                                        \
 	return __generate_vector<_Tp>(                                         \
 		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {            \
@@ -1956,8 +1949,8 @@ template <typename _Abi, typename>
 
 #define _GLIBCXX_SIMD_MATH_FALLBACK_MASKRET(__name)                            \
     template <typename _Tp, typename... _More>                                 \
-      static typename _Tp::mask_type _S_##__name(const _Tp& __x,               \
-						 const _More&... __more)       \
+      static typename _Tp::mask_type                                           \
+      _S_##__name(const _Tp& __x, const _More&... __more)                      \
       {                                                                        \
 	return __generate_vector<_Tp>(                                         \
 		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {            \
@@ -1967,7 +1960,8 @@ template <typename _Abi, typename>
 
 #define _GLIBCXX_SIMD_MATH_FALLBACK_FIXEDRET(_RetTp, __name)                          \
     template <typename _Tp, typename... _More>                                        \
-      static auto _S_##__name(const _Tp& __x, const _More&... __more)                 \
+      static auto                                                                     \
+      _S_##__name(const _Tp& __x, const _More&... __more)                             \
       {                                                                               \
 	return __fixed_size_storage_t<_RetTp,                                         \
 				      _VectorTraits<_Tp>::_S_partial_width>::         \
@@ -2115,22 +2109,22 @@ template <typename _Abi, typename>
 #undef _GLIBCXX_SIMD_MATH_FALLBACK_FIXEDRET
     // _S_abs {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_abs(_SimdWrapper<_Tp, _Np> __x) noexcept
-    {
-      // if (__builtin_is_constant_evaluated())
-      //  {
-      //    return __x._M_data < 0 ? -__x._M_data : __x._M_data;
-      //  }
-      if constexpr (is_floating_point_v<_Tp>)
-	// `v < 0 ? -v : v` cannot compile to the efficient implementation of
-	// masking the signbit off because it must consider v == -0
-
-	// ~(-0.) & v would be easy, but breaks with fno-signed-zeros
-	return __and(_S_absmask<__vector_type_t<_Tp, _Np>>, __x._M_data);
-      else
-	return __x._M_data < 0 ? -__x._M_data : __x._M_data;
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_abs(_SimdWrapper<_Tp, _Np> __x) noexcept
+      {
+	// if (__builtin_is_constant_evaluated())
+	//  {
+	//    return __x._M_data < 0 ? -__x._M_data : __x._M_data;
+	//  }
+	if constexpr (is_floating_point_v<_Tp>)
+	  // `v < 0 ? -v : v` cannot compile to the efficient implementation of
+	  // masking the signbit off because it must consider v == -0
+
+	  // ~(-0.) & v would be easy, but breaks with fno-signed-zeros
+	  return __and(_S_absmask<__vector_type_t<_Tp, _Np>>, __x._M_data);
+	else
+	  return __x._M_data < 0 ? -__x._M_data : __x._M_data;
+      }
 
     // }}}3
     // _S_plus_minus {{{
@@ -2138,318 +2132,316 @@ template <typename _Abi, typename>
     // - _TV must be __vector_type_t<floating-point type, N>.
     // - _UV must be _TV or floating-point type.
     template <typename _TV, typename _UV>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr _TV _S_plus_minus(_TV __x,
-							       _UV __y) noexcept
-    {
-  #if defined __i386__ && !defined __SSE_MATH__
-      if constexpr (sizeof(__x) == 8)
-	{ // operations on __x would use the FPU
-	  static_assert(is_same_v<_TV, __vector_type_t<float, 2>>);
-	  const auto __x4 = __vector_bitcast<float, 4>(__x);
-	  if constexpr (is_same_v<_TV, _UV>)
-	    return __vector_bitcast<float, 2>(
-	      _S_plus_minus(__x4, __vector_bitcast<float, 4>(__y)));
-	  else
-	    return __vector_bitcast<float, 2>(_S_plus_minus(__x4, __y));
-	}
-  #endif
-  #if !defined __clang__ && __GCC_IEC_559 == 0
-      if (__builtin_is_constant_evaluated()
-	  || (__builtin_constant_p(__x) && __builtin_constant_p(__y)))
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _TV
+      _S_plus_minus(_TV __x, _UV __y) noexcept
+      {
+#if defined __i386__ && !defined __SSE_MATH__
+	if constexpr (sizeof(__x) == 8)
+	  { // operations on __x would use the FPU
+	    static_assert(is_same_v<_TV, __vector_type_t<float, 2>>);
+	    const auto __x4 = __vector_bitcast<float, 4>(__x);
+	    if constexpr (is_same_v<_TV, _UV>)
+	      return __vector_bitcast<float, 2>(
+		       _S_plus_minus(__x4, __vector_bitcast<float, 4>(__y)));
+	    else
+	      return __vector_bitcast<float, 2>(_S_plus_minus(__x4, __y));
+	  }
+#endif
+#if !defined __clang__ && __GCC_IEC_559 == 0
+	if (__builtin_is_constant_evaluated()
+	      || (__builtin_constant_p(__x) && __builtin_constant_p(__y)))
+	  return (__x + __y) - __y;
+	else
+	  return [&] {
+	    __x += __y;
+	    if constexpr(__have_sse)
+	      {
+		if constexpr (sizeof(__x) >= 16)
+		  asm("" : "+x"(__x));
+		else if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
+		  asm("" : "+x"(__x[0]), "+x"(__x[1]));
+		else
+		  __assert_unreachable<_TV>();
+	      }
+	    else if constexpr(__have_neon)
+	      asm("" : "+w"(__x));
+	    else if constexpr (__have_power_vmx)
+	      {
+		if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
+		  asm("" : "+fgr"(__x[0]), "+fgr"(__x[1]));
+		else
+		  asm("" : "+v"(__x));
+	      }
+	    else
+	      asm("" : "+g"(__x));
+	    return __x - __y;
+	  }();
+#else
 	return (__x + __y) - __y;
-      else
-	return [&] {
-	  __x += __y;
-	  if constexpr(__have_sse)
-	    {
-	      if constexpr (sizeof(__x) >= 16)
-		asm("" : "+x"(__x));
-	      else if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
-		asm("" : "+x"(__x[0]), "+x"(__x[1]));
-	      else
-		__assert_unreachable<_TV>();
-	    }
-	  else if constexpr(__have_neon)
-	    asm("" : "+w"(__x));
-	  else if constexpr (__have_power_vmx)
-	    {
-	      if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
-		asm("" : "+fgr"(__x[0]), "+fgr"(__x[1]));
-	      else
-		asm("" : "+v"(__x));
-	    }
-	  else
-	    asm("" : "+g"(__x));
-	  return __x - __y;
-	}();
-  #else
-      return (__x + __y) - __y;
-  #endif
-    }
+#endif
+      }
 
     // }}}
     // _S_nearbyint {{{3
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nearbyint(_Tp __x_) noexcept
-    {
-      using value_type = typename _TVT::value_type;
-      using _V = typename _TVT::type;
-      const _V __x = __x_;
-      const _V __absx = __and(__x, _S_absmask<_V>);
-      static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<value_type>);
-      _GLIBCXX_SIMD_USE_CONSTEXPR _V __shifter_abs
-	= _V() + (1ull << (__digits_v<value_type> - 1));
-      const _V __shifter = __or(__and(_S_signmask<_V>, __x), __shifter_abs);
-      const _V __shifted = _S_plus_minus(__x, __shifter);
-      return __absx < __shifter_abs ? __shifted : __x;
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_nearbyint(_Tp __x_) noexcept
+      {
+	using value_type = typename _TVT::value_type;
+	using _V = typename _TVT::type;
+	const _V __x = __x_;
+	const _V __absx = __and(__x, _S_absmask<_V>);
+	static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<value_type>);
+	_GLIBCXX_SIMD_USE_CONSTEXPR _V __shifter_abs
+	  = _V() + (1ull << (__digits_v<value_type> - 1));
+	const _V __shifter = __or(__and(_S_signmask<_V>, __x), __shifter_abs);
+	const _V __shifted = _S_plus_minus(__x, __shifter);
+	return __absx < __shifter_abs ? __shifted : __x;
+      }
 
     // _S_rint {{{3
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_rint(_Tp __x) noexcept
-    {
-      return _SuperImpl::_S_nearbyint(__x);
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_rint(_Tp __x) noexcept
+      { return _SuperImpl::_S_nearbyint(__x); }
 
     // _S_trunc {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_trunc(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _V = __vector_type_t<_Tp, _Np>;
-      const _V __absx = __and(__x._M_data, _S_absmask<_V>);
-      static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<_Tp>);
-      constexpr _Tp __shifter = 1ull << (__digits_v<_Tp> - 1);
-      _V __truncated = _S_plus_minus(__absx, __shifter);
-      __truncated -= __truncated > __absx ? _V() + 1 : _V();
-      return __absx < __shifter ? __or(__xor(__absx, __x._M_data), __truncated)
-				: __x._M_data;
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_trunc(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _V = __vector_type_t<_Tp, _Np>;
+	const _V __absx = __and(__x._M_data, _S_absmask<_V>);
+	static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<_Tp>);
+	constexpr _Tp __shifter = 1ull << (__digits_v<_Tp> - 1);
+	_V __truncated = _S_plus_minus(__absx, __shifter);
+	__truncated -= __truncated > __absx ? _V() + 1 : _V();
+	return __absx < __shifter ? __or(__xor(__absx, __x._M_data), __truncated)
+				  : __x._M_data;
+      }
 
     // _S_round {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_round(_SimdWrapper<_Tp, _Np> __x)
-    {
-      const auto __abs_x = _SuperImpl::_S_abs(__x);
-      const auto __t_abs = _SuperImpl::_S_trunc(__abs_x)._M_data;
-      const auto __r_abs // round(abs(x)) =
-	= __t_abs + (__abs_x._M_data - __t_abs >= _Tp(.5) ? _Tp(1) : 0);
-      return __or(__xor(__abs_x._M_data, __x._M_data), __r_abs);
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_round(_SimdWrapper<_Tp, _Np> __x)
+      {
+	const auto __abs_x = _SuperImpl::_S_abs(__x);
+	const auto __t_abs = _SuperImpl::_S_trunc(__abs_x)._M_data;
+	const auto __r_abs // round(abs(x)) =
+	  = __t_abs + (__abs_x._M_data - __t_abs >= _Tp(.5) ? _Tp(1) : 0);
+	return __or(__xor(__abs_x._M_data, __x._M_data), __r_abs);
+      }
 
     // _S_floor {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_floor(_SimdWrapper<_Tp, _Np> __x)
-    {
-      const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
-      const auto __negative_input
-	= __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
-      const auto __mask
-	= __andnot(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
-      return __or(__andnot(__mask, __y),
-		  __and(__mask, __y - __vector_broadcast<_Np, _Tp>(1)));
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_floor(_SimdWrapper<_Tp, _Np> __x)
+      {
+	const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
+	const auto __negative_input
+	  = __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
+	const auto __mask
+	  = __andnot(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
+	return __or(__andnot(__mask, __y),
+		    __and(__mask, __y - __vector_broadcast<_Np, _Tp>(1)));
+      }
 
     // _S_ceil {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_ceil(_SimdWrapper<_Tp, _Np> __x)
-    {
-      const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
-      const auto __negative_input
-	= __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
-      const auto __inv_mask
-	= __or(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
-      return __or(__and(__inv_mask, __y),
-		  __andnot(__inv_mask, __y + __vector_broadcast<_Np, _Tp>(1)));
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_ceil(_SimdWrapper<_Tp, _Np> __x)
+      {
+	const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
+	const auto __negative_input
+	  = __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
+	const auto __inv_mask
+	  = __or(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
+	return __or(__and(__inv_mask, __y),
+		    __andnot(__inv_mask, __y + __vector_broadcast<_Np, _Tp>(1)));
+      }
 
     // _S_isnan {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isnan([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
-    {
-  #if __FINITE_MATH_ONLY__
-      return {}; // false
-  #elif !defined __SUPPORT_SNAN__
-      return ~(__x._M_data == __x._M_data);
-  #elif defined __STDC_IEC_559__
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
-      const auto __infn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__infinity_v<_Tp>));
-      return __infn < __absn;
-  #else
-  #error "Not implemented: how to support SNaN but non-IEC559 floating-point?"
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isnan([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
+      {
+#if __FINITE_MATH_ONLY__
+	return {}; // false
+#elif !defined __SUPPORT_SNAN__
+	return ~(__x._M_data == __x._M_data);
+#elif defined __STDC_IEC_559__
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
+	const auto __infn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__infinity_v<_Tp>));
+	return __infn < __absn;
+#else
+#error "Not implemented: how to support SNaN but non-IEC559 floating-point?"
+#endif
+      }
 
     // _S_isfinite {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isfinite([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
-    {
-  #if __FINITE_MATH_ONLY__
-      using _UV = typename _MaskMember<_Tp>::_BuiltinType;
-      _GLIBCXX_SIMD_USE_CONSTEXPR _UV __alltrue = ~_UV();
-      return __alltrue;
-  #else
-      // if all exponent bits are set, __x is either inf or NaN
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
-      const auto __maxn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
-      return __absn <= __maxn;
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isfinite([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
+      {
+#if __FINITE_MATH_ONLY__
+	using _UV = typename _MaskMember<_Tp>::_BuiltinType;
+	_GLIBCXX_SIMD_USE_CONSTEXPR _UV __alltrue = ~_UV();
+	return __alltrue;
+#else
+	// if all exponent bits are set, __x is either inf or NaN
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
+	const auto __maxn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
+	return __absn <= __maxn;
+#endif
+      }
 
     // _S_isunordered {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isunordered(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
-    {
-      return __or(_S_isnan(__x), _S_isnan(__y));
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isunordered(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
+      { return __or(_S_isnan(__x), _S_isnan(__y)); }
 
     // _S_signbit {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_signbit(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      return __vector_bitcast<_Ip>(__x) < 0;
-      // Arithmetic right shift (SRA) would also work (instead of compare), but
-      // 64-bit SRA isn't available on x86 before AVX512. And in general,
-      // compares are more likely to be efficient than SRA.
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_signbit(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	return __vector_bitcast<_Ip>(__x) < 0;
+	// Arithmetic right shift (SRA) would also work (instead of compare), but
+	// 64-bit SRA isn't available on x86 before AVX512. And in general,
+	// compares are more likely to be efficient than SRA.
+      }
 
     // _S_isinf {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isinf([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
-    {
-  #if __FINITE_MATH_ONLY__
-      return {}; // false
-  #else
-      return _SuperImpl::template _S_equal_to<_Tp, _Np>(_SuperImpl::_S_abs(__x),
-							__vector_broadcast<_Np>(
-							  __infinity_v<_Tp>));
-      // alternative:
-      // compare to inf using the corresponding integer type
-      /*
-	 return
-	 __vector_bitcast<_Tp>(__vector_bitcast<__int_for_sizeof_t<_Tp>>(
-			       _S_abs(__x)._M_data)
-	 ==
-	 __vector_bitcast<__int_for_sizeof_t<_Tp>>(__vector_broadcast<_Np>(
-	 __infinity_v<_Tp>)));
-	 */
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isinf([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
+      {
+#if __FINITE_MATH_ONLY__
+	return {}; // false
+#else
+	return _SuperImpl::template _S_equal_to<_Tp, _Np>(_SuperImpl::_S_abs(__x),
+							  __vector_broadcast<_Np>(
+							    __infinity_v<_Tp>));
+	// alternative:
+	// compare to inf using the corresponding integer type
+	/*
+	   return
+	   __vector_bitcast<_Tp>(__vector_bitcast<__int_for_sizeof_t<_Tp>>(
+				 _S_abs(__x)._M_data)
+	   ==
+	   __vector_bitcast<__int_for_sizeof_t<_Tp>>(__vector_broadcast<_Np>(
+	   __infinity_v<_Tp>)));
+	   */
+#endif
+      }
 
     // _S_isnormal {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isnormal(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
-      const auto __minn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__norm_min_v<_Tp>));
-  #if __FINITE_MATH_ONLY__
-      return __absn >= __minn;
-  #else
-      const auto __maxn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
-      return __minn <= __absn && __absn <= __maxn;
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isnormal(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
+	const auto __minn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__norm_min_v<_Tp>));
+#if __FINITE_MATH_ONLY__
+	return __absn >= __minn;
+#else
+	const auto __maxn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
+	return __minn <= __absn && __absn <= __maxn;
+#endif
+      }
 
     // _S_fpclassify {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static __fixed_size_storage_t<int, _Np>
-    _S_fpclassify(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _I = __int_for_sizeof_t<_Tp>;
-      const auto __xn
-	= __vector_bitcast<_I>(__to_intrin(_SuperImpl::_S_abs(__x)));
-      constexpr size_t _NI = sizeof(__xn) / sizeof(_I);
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __minn
-	= __vector_bitcast<_I>(__vector_broadcast<_NI>(__norm_min_v<_Tp>));
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __infn
-	= __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>));
-
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_normal
-	= __vector_broadcast<_NI, _I>(FP_NORMAL);
-  #if !__FINITE_MATH_ONLY__
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_nan
-	= __vector_broadcast<_NI, _I>(FP_NAN);
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_infinite
-	= __vector_broadcast<_NI, _I>(FP_INFINITE);
-  #endif
-  #ifndef __FAST_MATH__
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_subnormal
-	= __vector_broadcast<_NI, _I>(FP_SUBNORMAL);
-  #endif
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_zero
-	= __vector_broadcast<_NI, _I>(FP_ZERO);
+      _GLIBCXX_SIMD_INTRINSIC static __fixed_size_storage_t<int, _Np>
+      _S_fpclassify(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _I = __int_for_sizeof_t<_Tp>;
+	const auto __xn
+	  = __vector_bitcast<_I>(__to_intrin(_SuperImpl::_S_abs(__x)));
+	constexpr size_t _NI = sizeof(__xn) / sizeof(_I);
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __minn
+	  = __vector_bitcast<_I>(__vector_broadcast<_NI>(__norm_min_v<_Tp>));
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __infn
+	  = __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>));
+
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_normal
+	  = __vector_broadcast<_NI, _I>(FP_NORMAL);
+#if !__FINITE_MATH_ONLY__
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_nan
+	  = __vector_broadcast<_NI, _I>(FP_NAN);
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_infinite
+	  = __vector_broadcast<_NI, _I>(FP_INFINITE);
+#endif
+#ifndef __FAST_MATH__
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_subnormal
+	  = __vector_broadcast<_NI, _I>(FP_SUBNORMAL);
+#endif
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_zero
+	  = __vector_broadcast<_NI, _I>(FP_ZERO);
 
-      __vector_type_t<_I, _NI>
-	__tmp = __xn < __minn
+	__vector_type_t<_I, _NI>
+	  __tmp = __xn < __minn
   #ifdef __FAST_MATH__
-		  ? __fp_zero
+		    ? __fp_zero
   #else
-		  ? (__xn == 0 ? __fp_zero : __fp_subnormal)
+		    ? (__xn == 0 ? __fp_zero : __fp_subnormal)
   #endif
   #if __FINITE_MATH_ONLY__
-		  : __fp_normal;
+		    : __fp_normal;
   #else
-		  : (__xn < __infn ? __fp_normal
-				   : (__xn == __infn ? __fp_infinite : __fp_nan));
+		    : (__xn < __infn ? __fp_normal
+				     : (__xn == __infn ? __fp_infinite : __fp_nan));
   #endif
 
-      if constexpr (sizeof(_I) == sizeof(int))
-	{
-	  using _FixedInt = __fixed_size_storage_t<int, _Np>;
-	  const auto __as_int = __vector_bitcast<int, _Np>(__tmp);
-	  if constexpr (_FixedInt::_S_tuple_size == 1)
-	    return {__as_int};
-	  else if constexpr (_FixedInt::_S_tuple_size == 2
-			     && is_same_v<
-			       typename _FixedInt::_SecondType::_FirstAbi,
-			       simd_abi::scalar>)
-	    return {__extract<0, 2>(__as_int), __as_int[_Np - 1]};
-	  else if constexpr (_FixedInt::_S_tuple_size == 2)
-	    return {__extract<0, 2>(__as_int),
-		    __auto_bitcast(__extract<1, 2>(__as_int))};
-	  else
-	    __assert_unreachable<_Tp>();
-	}
-      else if constexpr (_Np == 2 && sizeof(_I) == 8
-			 && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 2)
-	{
-	  const auto __aslong = __vector_bitcast<_LLong>(__tmp);
-	  return {int(__aslong[0]), {int(__aslong[1])}};
-	}
-  #if _GLIBCXX_SIMD_X86INTRIN
-      else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 32
-			 && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
-	return {_mm_packs_epi32(__to_intrin(__lo128(__tmp)),
-				__to_intrin(__hi128(__tmp)))};
-      else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 64
-			 && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
-	return {_mm512_cvtepi64_epi32(__to_intrin(__tmp))};
-  #endif // _GLIBCXX_SIMD_X86INTRIN
-      else if constexpr (__fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
-	return {__call_with_subscripts<_Np>(__vector_bitcast<_LLong>(__tmp),
-					    [](auto... __l) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
-					      return __make_wrapper<int>(__l...);
-					    })};
-      else
-	__assert_unreachable<_Tp>();
-    }
+	if constexpr (sizeof(_I) == sizeof(int))
+	  {
+	    using _FixedInt = __fixed_size_storage_t<int, _Np>;
+	    const auto __as_int = __vector_bitcast<int, _Np>(__tmp);
+	    if constexpr (_FixedInt::_S_tuple_size == 1)
+	      return {__as_int};
+	    else if constexpr (_FixedInt::_S_tuple_size == 2
+				 && is_same_v<
+				      typename _FixedInt::_SecondType::_FirstAbi,
+				      simd_abi::scalar>)
+	      return {__extract<0, 2>(__as_int), __as_int[_Np - 1]};
+	    else if constexpr (_FixedInt::_S_tuple_size == 2)
+	      return {__extract<0, 2>(__as_int),
+		      __auto_bitcast(__extract<1, 2>(__as_int))};
+	    else
+	      __assert_unreachable<_Tp>();
+	  }
+	else if constexpr (_Np == 2 && sizeof(_I) == 8
+			     && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 2)
+	  {
+	    const auto __aslong = __vector_bitcast<_LLong>(__tmp);
+	    return {int(__aslong[0]), {int(__aslong[1])}};
+	  }
+#if _GLIBCXX_SIMD_X86INTRIN
+	else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 32
+			     && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
+	  return {_mm_packs_epi32(__to_intrin(__lo128(__tmp)),
+				  __to_intrin(__hi128(__tmp)))};
+	else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 64
+			     && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
+	  return {_mm512_cvtepi64_epi32(__to_intrin(__tmp))};
+#endif // _GLIBCXX_SIMD_X86INTRIN
+	else if constexpr (__fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
+	  return {__call_with_subscripts<_Np>(__vector_bitcast<_LLong>(__tmp),
+					      [](auto... __l) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+						return __make_wrapper<int>(__l...);
+					      })};
+	else
+	  __assert_unreachable<_Tp>();
+      }
 
     // _S_increment & _S_decrement{{{2
     template <typename _Tp, size_t _Np>
@@ -2703,10 +2695,7 @@ template <typename _Abi, typename>
     template <typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember<_Tp>
       _S_broadcast(bool __x)
-      {
-	return __x ? _Abi::template _S_implicit_mask<_Tp>()
-		   : _MaskMember<_Tp>();
-      }
+      { return __x ? _Abi::template _S_implicit_mask<_Tp>() : _MaskMember<_Tp>(); }
 
     // }}}
     // _S_load {{{
@@ -2808,8 +2797,8 @@ template <typename _Abi, typename>
 
     // _S_store {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __v,
-						   bool* __mem) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static void
+      _S_store(_SimdWrapper<_Tp, _Np> __v, bool* __mem) noexcept
       {
 	__execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  __mem[__i] = __v[__i];
@@ -2832,21 +2821,17 @@ template <typename _Abi, typename>
     template <size_t _Np, typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
       _S_from_bitmask(_SanitizedBitMask<_Np> __bits, _TypeTag<_Tp>)
-      {
-	return _SuperImpl::template _S_to_maskvector<_Tp, _S_size<_Tp>>(__bits);
-      }
+      { return _SuperImpl::template _S_to_maskvector<_Tp, _S_size<_Tp>>(__bits); }
 
     // logical and bitwise operators {{{2
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x,
-		     const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __and(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x,
-		    const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __or(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
@@ -2862,26 +2847,23 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __and(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x,
-		const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __or(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __xor(__x._M_data, __y._M_data); }
 
     // smart_reference access {{{2
     template <typename _Tp, size_t _Np>
-      static constexpr void _S_set(_SimdWrapper<_Tp, _Np>& __k, int __i,
-				   bool __x) noexcept
+      static constexpr void
+      _S_set(_SimdWrapper<_Tp, _Np>& __k, int __i, bool __x) noexcept
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  __k._M_set(__i, __x);
@@ -2907,15 +2889,13 @@ template <typename _Abi, typename>
     // _S_masked_assign{{{2
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k,
-		       _SimdWrapper<_Tp, _Np>& __lhs,
+      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs,
 		       __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs)
       { __lhs = _CommonImpl::_S_blend(__k, __lhs, __rhs); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k,
-		       _SimdWrapper<_Tp, _Np>& __lhs, bool __rhs)
+      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs, bool __rhs)
       {
 	if (__builtin_constant_p(__rhs))
 	  {
@@ -2995,20 +2975,14 @@ template <typename _Abi, typename>
     template <typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static int
       _S_find_first_set(simd_mask<_Tp, _Abi> __k)
-      {
-	return std::__countr_zero(
-	  _SuperImpl::_S_to_bits(__data(__k))._M_to_bits());
-      }
+      { return std::__countr_zero(_SuperImpl::_S_to_bits(__data(__k))._M_to_bits()); }
 
     // }}}
     // _S_find_last_set {{{
     template <typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static int
       _S_find_last_set(simd_mask<_Tp, _Abi> __k)
-      {
-	return std::__bit_width(
-	  _SuperImpl::_S_to_bits(__data(__k))._M_to_bits()) - 1;
-      }
+      { return std::__bit_width(_SuperImpl::_S_to_bits(__data(__k))._M_to_bits()) - 1; }
 
     // }}}
   };
diff --git a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
index dba6353b176..9a2c699eae0 100644
--- a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
+++ b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
@@ -55,10 +55,7 @@ template <typename _Tp, typename _A0, typename... _As>
 
 template <size_t _I, typename _Tp, typename _A0, typename... _As>
   struct __simd_tuple_element<_I, _SimdTuple<_Tp, _A0, _As...>>
-  {
-    using type =
-      typename __simd_tuple_element<_I - 1, _SimdTuple<_Tp, _As...>>::type;
-  };
+  { using type = typename __simd_tuple_element<_I - 1, _SimdTuple<_Tp, _As...>>::type; };
 
 template <size_t _I, typename _Tp>
   using __simd_tuple_element_t = typename __simd_tuple_element<_I, _Tp>::type;
@@ -80,10 +77,8 @@ template <typename _Tp, typename... _A0s, typename... _A1s>
   }
 
 template <typename _Tp, typename _A10, typename... _A1s>
-  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, simd_abi::scalar, _A10,
-					       _A1s...>
-  __simd_tuple_concat(const _Tp& __left,
-		      const _SimdTuple<_Tp, _A10, _A1s...>& __right)
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, simd_abi::scalar, _A10, _A1s...>
+  __simd_tuple_concat(const _Tp& __left, const _SimdTuple<_Tp, _A10, _A1s...>& __right)
   { return {__left, __right}; }
 
 // }}}
@@ -112,37 +107,29 @@ struct __as_simd_tuple {};
 
 template <typename _Tp, typename _A0, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr simd<_Tp, _A0>
-  __simd_tuple_get_impl(__as_simd, const _SimdTuple<_Tp, _A0, _Abis...>& __t,
-			_SizeConstant<0>)
+  __simd_tuple_get_impl(__as_simd, const _SimdTuple<_Tp, _A0, _Abis...>& __t, _SizeConstant<0>)
   { return {__private_init, __t.first}; }
 
 template <typename _Tp, typename _A0, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr const auto&
-  __simd_tuple_get_impl(__as_simd_tuple,
-			const _SimdTuple<_Tp, _A0, _Abis...>& __t,
+  __simd_tuple_get_impl(__as_simd_tuple, const _SimdTuple<_Tp, _A0, _Abis...>& __t,
 			_SizeConstant<0>)
   { return __t.first; }
 
 template <typename _Tp, typename _A0, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto&
-  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _A0, _Abis...>& __t,
-			_SizeConstant<0>)
+  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _A0, _Abis...>& __t, _SizeConstant<0>)
   { return __t.first; }
 
 template <typename _R, size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto
-  __simd_tuple_get_impl(_R, const _SimdTuple<_Tp, _Abis...>& __t,
-			_SizeConstant<_Np>)
+  __simd_tuple_get_impl(_R, const _SimdTuple<_Tp, _Abis...>& __t, _SizeConstant<_Np>)
   { return __simd_tuple_get_impl(_R(), __t.second, _SizeConstant<_Np - 1>()); }
 
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto&
-  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _Abis...>& __t,
-			_SizeConstant<_Np>)
-  {
-    return __simd_tuple_get_impl(__as_simd_tuple(), __t.second,
-				 _SizeConstant<_Np - 1>());
-  }
+  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _Abis...>& __t, _SizeConstant<_Np>)
+  { return __simd_tuple_get_impl(__as_simd_tuple(), __t.second, _SizeConstant<_Np - 1>()); }
 
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto
@@ -154,16 +141,12 @@ template <size_t _Np, typename _Tp, typename... _Abis>
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto
   __get_tuple_at(const _SimdTuple<_Tp, _Abis...>& __t)
-  {
-    return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>());
-  }
+  { return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>()); }
 
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto&
   __get_tuple_at(_SimdTuple<_Tp, _Abis...>& __t)
-  {
-    return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>());
-  }
+  { return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>()); }
 
 // __tuple_element_meta {{{1
 template <typename _Tp, typename _Abi, size_t _Offset>
@@ -213,17 +196,13 @@ template <size_t _Offset, typename _Base>
   {
     static inline constexpr size_t _S_offset = _Offset;
 
-    _GLIBCXX_SIMD_INTRINSIC char* _M_as_charptr()
-    {
-      return reinterpret_cast<char*>(this)
-	     + _S_offset * sizeof(typename _Base::value_type);
-    }
+    _GLIBCXX_SIMD_INTRINSIC char*
+    _M_as_charptr()
+    { return reinterpret_cast<char*>(this) + _S_offset * sizeof(typename _Base::value_type); }
 
-    _GLIBCXX_SIMD_INTRINSIC const char* _M_as_charptr() const
-    {
-      return reinterpret_cast<const char*>(this)
-	     + _S_offset * sizeof(typename _Base::value_type);
-    }
+    _GLIBCXX_SIMD_INTRINSIC const char*
+    _M_as_charptr() const
+    { return reinterpret_cast<const char*>(this) + _S_offset * sizeof(typename _Base::value_type); }
   };
 
 // make _WithOffset<_WithOffset> ill-formed to use:
@@ -240,19 +219,13 @@ template <size_t _Offset, typename _Tp>
   _GLIBCXX_SIMD_INTRINSIC
   decltype(auto)
   __add_offset(const _Tp& __base)
-  {
-    return static_cast<const _WithOffset<_Offset, __remove_cvref_t<_Tp>>&>(
-      __base);
-  }
+  { return static_cast<const _WithOffset<_Offset, __remove_cvref_t<_Tp>>&>(__base); }
 
 template <size_t _Offset, size_t _ExistingOffset, typename _Tp>
   _GLIBCXX_SIMD_INTRINSIC
   decltype(auto)
   __add_offset(_WithOffset<_ExistingOffset, _Tp>& __base)
-  {
-    return static_cast<_WithOffset<_Offset + _ExistingOffset, _Tp>&>(
-      static_cast<_Tp&>(__base));
-  }
+  { return static_cast<_WithOffset<_Offset + _ExistingOffset, _Tp>&>(static_cast<_Tp&>(__base)); }
 
 template <size_t _Offset, size_t _ExistingOffset, typename _Tp>
   _GLIBCXX_SIMD_INTRINSIC
@@ -298,7 +271,8 @@ template <typename _FirstType, typename _SecondType>
     _SecondType second;
 
     _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    constexpr bool
+    _M_is_constprop() const
     {
       if constexpr (is_class_v<_FirstType>)
 	return first._M_is_constprop() && second._M_is_constprop();
@@ -314,7 +288,8 @@ template <typename _FirstType, typename _Tp>
     static constexpr _SimdTuple<_Tp> second = {};
 
     _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    constexpr bool
+    _M_is_constprop() const
     {
       if constexpr (is_class_v<_FirstType>)
 	return first._M_is_constprop();
@@ -353,25 +328,31 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       = default;
 
     template <typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple(_Up&& __x)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdTuple(_Up&& __x)
       : _Base{static_cast<_Up&&>(__x)} {}
 
     template <typename _Up, typename _Up2>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple(_Up&& __x, _Up2&& __y)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdTuple(_Up&& __x, _Up2&& __y)
       : _Base{static_cast<_Up&&>(__x), static_cast<_Up2&&>(__y)} {}
 
     template <typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple(_Up&& __x, _SimdTuple<_Tp>)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdTuple(_Up&& __x, _SimdTuple<_Tp>)
       : _Base{static_cast<_Up&&>(__x)} {}
 
-    _GLIBCXX_SIMD_INTRINSIC char* _M_as_charptr()
+    _GLIBCXX_SIMD_INTRINSIC char*
+    _M_as_charptr()
     { return reinterpret_cast<char*>(this); }
 
-    _GLIBCXX_SIMD_INTRINSIC const char* _M_as_charptr() const
+    _GLIBCXX_SIMD_INTRINSIC const char*
+    _M_as_charptr() const
     { return reinterpret_cast<const char*>(this); }
 
     template <size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC constexpr auto& _M_at()
+      _GLIBCXX_SIMD_INTRINSIC constexpr auto&
+      _M_at()
       {
 	if constexpr (_Np == 0)
 	  return first;
@@ -380,7 +361,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       }
 
     template <size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC constexpr const auto& _M_at() const
+      _GLIBCXX_SIMD_INTRINSIC constexpr const auto&
+      _M_at() const
       {
 	if constexpr (_Np == 0)
 	  return first;
@@ -389,7 +371,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       }
 
     template <size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC constexpr auto _M_simd_at() const
+      _GLIBCXX_SIMD_INTRINSIC constexpr auto
+      _M_simd_at() const
       {
 	if constexpr (_Np == 0)
 	  return simd<_Tp, _Abi0>(__private_init, first);
@@ -552,8 +535,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       }
 
     template <typename _R = _Tp, typename _Fp, typename... _More>
-      _GLIBCXX_SIMD_INTRINSIC auto _M_apply_r(_Fp&& __fun,
-					      const _More&... __more) const
+      _GLIBCXX_SIMD_INTRINSIC auto
+      _M_apply_r(_Fp&& __fun, const _More&... __more) const
       {
 	auto&& __first = __fun(__tuple_element_meta<_Tp, _Abi0, 0>(), first,
 			       __more.first...);
@@ -590,8 +573,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	  return second[integral_constant<_Up, _I - simd_size_v<_Tp, _Abi0>>()];
       }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    _Tp operator[](size_t __i) const noexcept
+    _GLIBCXX_SIMD_INTRINSIC _Tp
+    operator[](size_t __i) const noexcept
     {
       if constexpr (_S_tuple_size == 1)
 	return _M_subscript_read(__i);
@@ -613,8 +596,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	}
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    void _M_set(size_t __i, _Tp __val) noexcept
+    _GLIBCXX_SIMD_INTRINSIC void
+    _M_set(size_t __i, _Tp __val) noexcept
     {
       if constexpr (_S_tuple_size == 1)
 	return _M_subscript_write(__i, __val);
@@ -633,8 +616,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 
   private:
     // _M_subscript_read/_write {{{
-    _GLIBCXX_SIMD_INTRINSIC
-    _Tp _M_subscript_read([[maybe_unused]] size_t __i) const noexcept
+    _GLIBCXX_SIMD_INTRINSIC _Tp
+    _M_subscript_read([[maybe_unused]] size_t __i) const noexcept
     {
       if constexpr (__is_vectorizable_v<_FirstType>)
 	return first;
@@ -642,8 +625,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	return first[__i];
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    void _M_subscript_write([[maybe_unused]] size_t __i, _Tp __y) noexcept
+    _GLIBCXX_SIMD_INTRINSIC void
+    _M_subscript_write([[maybe_unused]] size_t __i, _Tp __y) noexcept
     {
       if constexpr (__is_vectorizable_v<_FirstType>)
 	first = __y;
@@ -687,8 +670,7 @@ template <typename _Tp, size_t _Np,
 	  size_t _Offset = 0, // skip this many elements in __from0
 	  typename _R = __fixed_size_storage_t<_Tp, _Np>, typename _V0,
 	  typename _V0VT = _VectorTraits<_V0>, typename... _VX>
-  _GLIBCXX_SIMD_INTRINSIC _R constexpr __to_simd_tuple(const _V0 __from0,
-						       const _VX... __fromX)
+  _GLIBCXX_SIMD_INTRINSIC _R constexpr __to_simd_tuple(const _V0 __from0, const _VX... __fromX)
   {
     static_assert(is_same_v<typename _V0VT::value_type, _Tp>);
     static_assert(_Offset < _V0VT::_S_full_size);
@@ -900,11 +882,8 @@ template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 // __for_each(_SimdTuple &, const _SimdTuple &, Fun) {{{1
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _Fp>
   _GLIBCXX_SIMD_INTRINSIC constexpr void
-  __for_each(_SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b,
-	     _Fp&& __fun)
-  {
-    static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first);
-  }
+  __for_each(_SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b, _Fp&& __fun)
+  { static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first); }
 
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 	  typename... _As, typename _Fp>
@@ -920,11 +899,8 @@ template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 // __for_each(const _SimdTuple &, const _SimdTuple &, Fun) {{{1
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _Fp>
   _GLIBCXX_SIMD_INTRINSIC constexpr void
-  __for_each(const _SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b,
-	     _Fp&& __fun)
-  {
-    static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first);
-  }
+  __for_each(const _SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b, _Fp&& __fun)
+  { static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first); }
 
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 	  typename... _As, typename _Fp>
@@ -939,8 +915,7 @@ template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 
 // }}}1
 // __extract_part(_SimdTuple) {{{
-template <int _Index, int _Total, int _Combine, typename _Tp, typename _A0,
-	  typename... _As>
+template <int _Index, int _Total, int _Combine, typename _Tp, typename _A0, typename... _As>
   _GLIBCXX_SIMD_INTRINSIC auto // __vector_type_t or _SimdTuple
   __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x)
   {
@@ -1062,8 +1037,8 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
       return &_M_data;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr __autocvt_to_simd(_Tp dd) : _M_data(dd) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    __autocvt_to_simd(_Tp dd) : _M_data(dd) {}
 
     template <typename _Abi>
       _GLIBCXX_SIMD_INTRINSIC
@@ -1073,18 +1048,12 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
     template <typename _Abi>
       _GLIBCXX_SIMD_INTRINSIC
       operator simd<typename _TT::value_type, _Abi>&()
-      {
-	return *reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(
-	  &_M_data);
-      }
+      { return *reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(&_M_data); }
 
     template <typename _Abi>
       _GLIBCXX_SIMD_INTRINSIC
       operator simd<typename _TT::value_type, _Abi>*()
-      {
-	return reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(
-	  &_M_data);
-      }
+      { return reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(&_M_data); }
   };
 
 template <typename _Tp>
@@ -1197,12 +1166,12 @@ template <int _Np>
 	  _SimdBase(const _SimdBase&) {}
 	  _SimdBase() = default;
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
-	  explicit operator const _SimdMember &() const
+	  _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+	  operator const _SimdMember &() const
 	  { return static_cast<const simd<_Tp, _Fixed>*>(this)->_M_data; }
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
-	  explicit operator array<_Tp, _Np>() const
+	  _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+	  operator array<_Tp, _Np>() const
 	  {
 	    array<_Tp, _Np> __r;
 	    // _SimdMember can be larger because of higher alignment
@@ -1224,10 +1193,12 @@ template <int _Np>
 	{
 	  _GLIBCXX_SIMD_ALWAYS_INLINE
 	  _SimdCastType(const array<_Tp, _Np>&);
+
 	  _GLIBCXX_SIMD_ALWAYS_INLINE
 	  _SimdCastType(const _SimdMember& dd) : _M_data(dd) {}
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
-	  explicit operator const _SimdMember &() const { return _M_data; }
+
+	  _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+	  operator const _SimdMember &() const { return _M_data; }
 
 	private:
 	  const _SimdMember& _M_data;
@@ -1466,8 +1437,7 @@ template <int _Np, typename>
     // _S_min, _S_max {{{2
     template <typename _Tp, typename... _As>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
-      _S_min(const _SimdTuple<_Tp, _As...>& __a,
-	     const _SimdTuple<_Tp, _As...>& __b)
+      _S_min(const _SimdTuple<_Tp, _As...>& __a, const _SimdTuple<_Tp, _As...>& __b)
       {
 	return __a._M_apply_per_chunk(
 	  [](auto __impl, auto __aa, auto __bb) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1478,8 +1448,7 @@ template <int _Np, typename>
 
     template <typename _Tp, typename... _As>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
-      _S_max(const _SimdTuple<_Tp, _As...>& __a,
-	     const _SimdTuple<_Tp, _As...>& __b)
+      _S_max(const _SimdTuple<_Tp, _As...>& __a, const _SimdTuple<_Tp, _As...>& __b)
       {
 	return __a._M_apply_per_chunk(
 	  [](auto __impl, auto __aa, auto __bb) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1692,7 +1661,7 @@ template <int _Np, typename>
 #define _GLIBCXX_SIMD_TEST_ON_TUPLE_(name_)                                              \
     template <typename _Tp, typename... _As>                                             \
       static inline _MaskMember                                                          \
-	_S_##name_(const _SimdTuple<_Tp, _As...>& __x) noexcept                          \
+      _S_##name_(const _SimdTuple<_Tp, _As...>& __x) noexcept                            \
       {                                                                                  \
 	return _M_test([] (auto __impl, auto __xx) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA  { \
 		 return __impl._S_##name_(__xx);                                         \
@@ -1754,8 +1723,8 @@ template <int _Np, typename>
 
     // smart_reference access {{{2
     template <typename _Tp, typename... _As, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static void _S_set(_SimdTuple<_Tp, _As...>& __v,
-						 int __i, _Up&& __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static void
+      _S_set(_SimdTuple<_Tp, _As...>& __v, int __i, _Up&& __x) noexcept
       { __v._M_set(__i, static_cast<_Up&&>(__x)); }
 
     // _S_masked_assign {{{2
@@ -1789,10 +1758,9 @@ template <int _Np, typename>
 
     // _S_masked_cassign {{{2
     template <typename _Op, typename _Tp, typename... _As>
-      static inline void _S_masked_cassign(const _MaskMember __bits,
-					   _SimdTuple<_Tp, _As...>& __lhs,
-					   const _SimdTuple<_Tp, _As...>& __rhs,
-					   _Op __op)
+      static inline void
+      _S_masked_cassign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
+			const _SimdTuple<_Tp, _As...>& __rhs, _Op __op)
       {
 	__for_each(__lhs, __rhs,
 		   [&](auto __meta, auto& __native_lhs, auto __native_rhs)
@@ -1806,9 +1774,9 @@ template <int _Np, typename>
     // Optimization for the case where the RHS is a scalar. No need to broadcast
     // the scalar to a simd first.
     template <typename _Op, typename _Tp, typename... _As>
-      static inline void _S_masked_cassign(const _MaskMember __bits,
-					   _SimdTuple<_Tp, _As...>& __lhs,
-					   const _Tp& __rhs, _Op __op)
+      static inline void
+      _S_masked_cassign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
+			const _Tp& __rhs, _Op __op)
       {
 	__for_each(
 	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1906,7 +1874,8 @@ template <int _Np, typename>
       { return __bits; }
 
     // _S_load {{{2
-    static inline _MaskMember _S_load(const bool* __mem) noexcept
+    static inline _MaskMember
+    _S_load(const bool* __mem) noexcept
     {
       // TODO: _UChar is not necessarily the best type to use here. For smaller
       // _Np _UShort, _UInt, _ULLong, float, and double can be more efficient.
@@ -1921,9 +1890,8 @@ template <int _Np, typename>
     }
 
     // _S_masked_load {{{2
-    static inline _MaskMember _S_masked_load(_MaskMember __merge,
-					     _MaskMember __mask,
-					     const bool* __mem) noexcept
+    static inline _MaskMember
+    _S_masked_load(_MaskMember __merge, _MaskMember __mask, const bool* __mem) noexcept
     {
       _BitOps::_S_bit_iteration(__mask.to_ullong(),
 				[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1933,8 +1901,8 @@ template <int _Np, typename>
     }
 
     // _S_store {{{2
-    static inline void _S_store(const _MaskMember __bitmask,
-				bool* __mem) noexcept
+    static inline void
+    _S_store(const _MaskMember __bitmask, bool* __mem) noexcept
     {
       if constexpr (_Np == 1)
 	__mem[0] = __bitmask[0];
@@ -1943,8 +1911,8 @@ template <int _Np, typename>
     }
 
     // _S_masked_store {{{2
-    static inline void _S_masked_store(const _MaskMember __v, bool* __mem,
-				       const _MaskMember __k) noexcept
+    static inline void
+    _S_masked_store(const _MaskMember __v, bool* __mem, const _MaskMember __k) noexcept
     {
       _BitOps::_S_bit_iteration(
 	__k, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { __mem[__i] = __v[__i]; });
@@ -1976,20 +1944,18 @@ template <int _Np, typename>
     { return __x ^ __y; }
 
     // smart_reference access {{{2
-    _GLIBCXX_SIMD_INTRINSIC static void _S_set(_MaskMember& __k, int __i,
-					       bool __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_set(_MaskMember& __k, int __i, bool __x) noexcept
     { __k.set(__i, __x); }
 
     // _S_masked_assign {{{2
     _GLIBCXX_SIMD_INTRINSIC static void
-    _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs,
-		     const _MaskMember __rhs)
+    _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs, const _MaskMember __rhs)
     { __lhs = (__lhs & ~__k) | (__rhs & __k); }
 
     // Optimization for the case where the RHS is a scalar.
-    _GLIBCXX_SIMD_INTRINSIC static void _S_masked_assign(const _MaskMember __k,
-							 _MaskMember& __lhs,
-							 const bool __rhs)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs, const bool __rhs)
     {
       if (__rhs)
 	__lhs |= __k;
@@ -2000,19 +1966,22 @@ template <int _Np, typename>
     // }}}2
     // _S_all_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_all_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_all_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).all(); }
 
     // }}}
     // _S_any_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_any_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_any_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).any(); }
 
     // }}}
     // _S_none_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_none_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_none_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).none(); }
 
     // }}}
@@ -2030,7 +1999,8 @@ template <int _Np, typename>
     // }}}
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).count(); }
 
     // }}}
diff --git a/libstdc++-v3/include/experimental/bits/simd_neon.h b/libstdc++-v3/include/experimental/bits/simd_neon.h
index c809addd2af..5eb5b9655f9 100644
--- a/libstdc++-v3/include/experimental/bits/simd_neon.h
+++ b/libstdc++-v3/include/experimental/bits/simd_neon.h
@@ -134,7 +134,8 @@ template <typename _Abi, typename>
     // math {{{
     // _S_sqrt {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sqrt(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_sqrt(_Tp __x)
       {
 	if constexpr (__have_neon_a64)
 	  {
@@ -157,7 +158,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_trunc {{{
     template <typename _TW, typename _TVT = _VectorTraits<_TW>>
-      _GLIBCXX_SIMD_INTRINSIC static _TW _S_trunc(_TW __x)
+      _GLIBCXX_SIMD_INTRINSIC static _TW
+      _S_trunc(_TW __x)
       {
 	using _Tp = typename _TVT::value_type;
 	if constexpr (__have_neon_a32)
@@ -216,7 +218,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_floor {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_floor(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_floor(_Tp __x)
       {
 	if constexpr (__have_neon_a32)
 	  {
@@ -239,7 +242,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_ceil {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_ceil(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_ceil(_Tp __x)
       {
 	if constexpr (__have_neon_a32)
 	  {
@@ -400,7 +404,8 @@ template <typename _Abi, typename>
 
     // _S_all_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_all_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_all_of(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kk
 	  = __vector_bitcast<char>(__k._M_data)
@@ -419,7 +424,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_any_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_any_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_any_of(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kk
 	  = __vector_bitcast<char>(__k._M_data)
@@ -438,7 +444,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_none_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_none_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_none_of(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kk = _Abi::_S_masked(__k._M_data);
 	if constexpr (sizeof(__k) == 16)
@@ -472,7 +479,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (sizeof(_Tp) == 1)
 	  {
diff --git a/libstdc++-v3/include/experimental/bits/simd_ppc.h b/libstdc++-v3/include/experimental/bits/simd_ppc.h
index a83d970a457..40ad48bcec1 100644
--- a/libstdc++-v3/include/experimental/bits/simd_ppc.h
+++ b/libstdc++-v3/include/experimental/bits/simd_ppc.h
@@ -124,7 +124,8 @@ template <typename _Abi, typename>
 
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kv = __as_vector(__k);
 	if constexpr (__have_power10vec)
diff --git a/libstdc++-v3/include/experimental/bits/simd_scalar.h b/libstdc++-v3/include/experimental/bits/simd_scalar.h
index 33c3cefc88d..aeccedfbc8b 100644
--- a/libstdc++-v3/include/experimental/bits/simd_scalar.h
+++ b/libstdc++-v3/include/experimental/bits/simd_scalar.h
@@ -74,7 +74,8 @@ struct simd_abi::_Scalar
   template <typename _Tp>
     static constexpr bool _S_is_valid_v = _IsValid<_Tp>::value;
 
-  _GLIBCXX_SIMD_INTRINSIC static constexpr bool _S_masked(bool __x)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_masked(bool __x)
   { return __x; }
 
   using _CommonImpl = _CommonImplScalar;
@@ -110,7 +111,8 @@ struct _CommonImplScalar
 {
   // _S_store {{{
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_Tp __x, void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_Tp __x, void* __addr)
     { __builtin_memcpy(__addr, &__x, sizeof(_Tp)); }
 
   // }}}
@@ -138,26 +140,26 @@ struct _SimdImplScalar
 
   // _S_broadcast {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp _S_broadcast(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_broadcast(_Tp __x) noexcept
     { return __x; }
 
   // _S_generator {{{2
   template <typename _Fp, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp _S_generator(_Fp&& __gen,
-							      _TypeTag<_Tp>)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_generator(_Fp&& __gen, _TypeTag<_Tp>)
     { return __gen(_SizeConstant<0>()); }
 
   // _S_load {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_load(const _Up* __mem,
-					       _TypeTag<_Tp>) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
     { return static_cast<_Tp>(__mem[0]); }
 
   // _S_masked_load {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    static _Tp _S_masked_load(_Tp __merge, bool __k,
-				     const _Up* __mem) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_masked_load(_Tp __merge, bool __k, const _Up* __mem) noexcept
     {
       if (__k)
 	__merge = static_cast<_Tp>(__mem[0]);
@@ -166,97 +168,95 @@ struct _SimdImplScalar
 
   // _S_store {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    static void _S_store(_Tp __v, _Up* __mem, _TypeTag<_Tp>) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_Tp __v, _Up* __mem, _TypeTag<_Tp>) noexcept
     { __mem[0] = static_cast<_Up>(__v); }
 
   // _S_masked_store {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    static void _S_masked_store(const _Tp __v, _Up* __mem,
-				       const bool __k) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_masked_store(const _Tp __v, _Up* __mem, const bool __k) noexcept
     { if (__k) __mem[0] = __v; }
 
   // _S_negate {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr bool _S_negate(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_negate(_Tp __x) noexcept
     { return !__x; }
 
   // _S_reduce {{{2
   template <typename _Tp, typename _BinaryOperation>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
     _S_reduce(const simd<_Tp, simd_abi::scalar>& __x, const _BinaryOperation&)
     { return __x._M_data; }
 
   // _S_min, _S_max {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_min(const _Tp __a, const _Tp __b)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_min(const _Tp __a, const _Tp __b)
     { return std::min(__a, __b); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_max(const _Tp __a, const _Tp __b)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_max(const _Tp __a, const _Tp __b)
     { return std::max(__a, __b); }
 
   // _S_complement {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_complement(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_complement(_Tp __x) noexcept
     { return static_cast<_Tp>(~__x); }
 
   // _S_unary_minus {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_unary_minus(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_unary_minus(_Tp __x) noexcept
     { return static_cast<_Tp>(-__x); }
 
   // arithmetic operators {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_plus(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_plus(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      + __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_minus(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_minus(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      - __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_multiplies(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_multiplies(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      * __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_divides(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_divides(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      / __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_modulus(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_modulus(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      % __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_and(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_and(_Tp __x, _Tp __y)
     {
       if constexpr (is_floating_point_v<_Tp>)
 	{
@@ -269,8 +269,8 @@ struct _SimdImplScalar
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_or(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_or(_Tp __x, _Tp __y)
     {
       if constexpr (is_floating_point_v<_Tp>)
 	{
@@ -283,8 +283,8 @@ struct _SimdImplScalar
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_xor(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_xor(_Tp __x, _Tp __y)
     {
       if constexpr (is_floating_point_v<_Tp>)
 	{
@@ -297,13 +297,13 @@ struct _SimdImplScalar
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_shift_left(_Tp __x, int __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_shift_left(_Tp __x, int __y)
     { return static_cast<_Tp>(__promote_preserving_unsigned(__x) << __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_shift_right(_Tp __x, int __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_shift_right(_Tp __x, int __y)
     { return static_cast<_Tp>(__promote_preserving_unsigned(__x) >> __y); }
 
   // math {{{2
@@ -312,300 +312,362 @@ struct _SimdImplScalar
     using _ST = _SimdTuple<_Tp, simd_abi::scalar>;
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_acos(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_acos(_Tp __x)
     { return std::acos(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_asin(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_asin(_Tp __x)
     { return std::asin(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_atan(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_atan(_Tp __x)
     { return std::atan(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_cos(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_cos(_Tp __x)
     { return std::cos(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sin(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_sin(_Tp __x)
     { return std::sin(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_tan(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_tan(_Tp __x)
     { return std::tan(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_acosh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_acosh(_Tp __x)
     { return std::acosh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_asinh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_asinh(_Tp __x)
     { return std::asinh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_atanh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_atanh(_Tp __x)
     { return std::atanh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_cosh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_cosh(_Tp __x)
     { return std::cosh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sinh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_sinh(_Tp __x)
     { return std::sinh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_tanh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_tanh(_Tp __x)
     { return std::tanh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_atan2(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_atan2(_Tp __x, _Tp __y)
     { return std::atan2(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_exp(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_exp(_Tp __x)
     { return std::exp(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_exp2(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_exp2(_Tp __x)
     { return std::exp2(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_expm1(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_expm1(_Tp __x)
     { return std::expm1(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log(_Tp __x)
     { return std::log(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log10(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log10(_Tp __x)
     { return std::log10(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log1p(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log1p(_Tp __x)
     { return std::log1p(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log2(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log2(_Tp __x)
     { return std::log2(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_logb(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_logb(_Tp __x)
     { return std::logb(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<int> _S_ilogb(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<int>
+    _S_ilogb(_Tp __x)
     { return {std::ilogb(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_pow(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_pow(_Tp __x, _Tp __y)
     { return std::pow(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_abs(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_abs(_Tp __x)
     { return std::abs(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fabs(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fabs(_Tp __x)
     { return std::fabs(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sqrt(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_sqrt(_Tp __x)
     { return std::sqrt(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_cbrt(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_cbrt(_Tp __x)
     { return std::cbrt(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_erf(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_erf(_Tp __x)
     { return std::erf(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_erfc(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_erfc(_Tp __x)
     { return std::erfc(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_lgamma(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_lgamma(_Tp __x)
     { return std::lgamma(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_tgamma(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_tgamma(_Tp __x)
     { return std::tgamma(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_trunc(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_trunc(_Tp __x)
     { return std::trunc(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_floor(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_floor(_Tp __x)
     { return std::floor(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_ceil(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_ceil(_Tp __x)
     { return std::ceil(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nearbyint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_nearbyint(_Tp __x)
     { return std::nearbyint(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_rint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_rint(_Tp __x)
     { return std::rint(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long> _S_lrint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long>
+    _S_lrint(_Tp __x)
     { return {std::lrint(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long long> _S_llrint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long long>
+    _S_llrint(_Tp __x)
     { return {std::llrint(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_round(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_round(_Tp __x)
     { return std::round(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long> _S_lround(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long>
+    _S_lround(_Tp __x)
     { return {std::lround(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long long> _S_llround(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long long>
+    _S_llround(_Tp __x)
     { return {std::llround(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_ldexp(_Tp __x, _ST<int> __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_ldexp(_Tp __x, _ST<int> __y)
     { return std::ldexp(__x, __y.first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_scalbn(_Tp __x, _ST<int> __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_scalbn(_Tp __x, _ST<int> __y)
     { return std::scalbn(__x, __y.first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_scalbln(_Tp __x, _ST<long> __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_scalbln(_Tp __x, _ST<long> __y)
     { return std::scalbln(__x, __y.first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fmod(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fmod(_Tp __x, _Tp __y)
     { return std::fmod(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_remainder(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_remainder(_Tp __x, _Tp __y)
     { return std::remainder(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nextafter(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_nextafter(_Tp __x, _Tp __y)
     { return std::nextafter(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fdim(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fdim(_Tp __x, _Tp __y)
     { return std::fdim(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fmax(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fmax(_Tp __x, _Tp __y)
     { return std::fmax(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fmin(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fmin(_Tp __x, _Tp __y)
     { return std::fmin(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fma(_Tp __x, _Tp __y, _Tp __z)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fma(_Tp __x, _Tp __y, _Tp __z)
     { return std::fma(__x, __y, __z); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_remquo(_Tp __x, _Tp __y, _ST<int>* __z)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_remquo(_Tp __x, _Tp __y, _ST<int>* __z)
     { return std::remquo(__x, __y, &__z->first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static _ST<int> _S_fpclassify(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static _ST<int>
+    _S_fpclassify(_Tp __x)
     { return {std::fpclassify(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isfinite(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isfinite(_Tp __x)
     { return std::isfinite(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isinf(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isinf(_Tp __x)
     { return std::isinf(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isnan(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isnan(_Tp __x)
     { return std::isnan(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isnormal(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isnormal(_Tp __x)
     { return std::isnormal(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_signbit(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_signbit(_Tp __x)
     { return std::signbit(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isgreater(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isgreater(_Tp __x, _Tp __y)
     { return std::isgreater(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isgreaterequal(_Tp __x,
-								    _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isgreaterequal(_Tp __x, _Tp __y)
     { return std::isgreaterequal(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isless(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isless(_Tp __x, _Tp __y)
     { return std::isless(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_islessequal(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_islessequal(_Tp __x, _Tp __y)
     { return std::islessequal(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_islessgreater(_Tp __x,
-								   _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_islessgreater(_Tp __x, _Tp __y)
     { return std::islessgreater(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isunordered(_Tp __x,
-								 _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_isunordered(_Tp __x, _Tp __y)
     { return std::isunordered(__x, __y); }
 
   // _S_increment & _S_decrement{{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr static void _S_increment(_Tp& __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _S_increment(_Tp& __x)
     { ++__x; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr static void _S_decrement(_Tp& __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _S_decrement(_Tp& __x)
     { --__x; }
 
 
   // compares {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_equal_to(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_equal_to(_Tp __x, _Tp __y)
     { return __x == __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_not_equal_to(_Tp __x,
-								  _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_not_equal_to(_Tp __x, _Tp __y)
     { return __x != __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_less(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_less(_Tp __x, _Tp __y)
     { return __x < __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_less_equal(_Tp __x,
-								_Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _S_less_equal(_Tp __x, _Tp __y)
     { return __x <= __y; }
 
   // smart_reference access {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr static void _S_set(_Tp& __v, [[maybe_unused]] int __i,
-				 _Up&& __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _S_set(_Tp& __v, [[maybe_unused]] int __i, _Up&& __x) noexcept
     {
       _GLIBCXX_DEBUG_ASSERT(__i == 0);
       __v = static_cast<_Up&&>(__x);
@@ -625,8 +687,8 @@ struct _SimdImplScalar
 
   // _S_masked_unary {{{2
   template <template <typename> class _Op, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static _Tp _S_masked_unary(const bool __k,
-								 const _Tp __v)
+    _GLIBCXX_SIMD_INTRINSIC constexpr static _Tp
+    _S_masked_unary(const bool __k, const _Tp __v)
     { return static_cast<_Tp>(__k ? _Op<_Tp>{}(__v) : __v); }
 
   // }}}2
@@ -643,13 +705,15 @@ struct _MaskImplScalar
   // }}}
   // _S_broadcast {{{
   template <typename>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr bool _S_broadcast(bool __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_broadcast(bool __x)
     { return __x; }
 
   // }}}
   // _S_load {{{
   template <typename>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr bool _S_load(const bool* __mem)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_load(const bool* __mem)
     { return __mem[0]; }
 
   // }}}
@@ -687,7 +751,8 @@ struct _MaskImplScalar
   }
 
   // _S_store {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void _S_store(bool __v, bool* __mem) noexcept
+  _GLIBCXX_SIMD_INTRINSIC static void
+  _S_store(bool __v, bool* __mem) noexcept
   { __mem[0] = __v; }
 
   // _S_masked_store {{{2
@@ -699,42 +764,41 @@ struct _MaskImplScalar
   }
 
   // logical and bitwise operators {{{2
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_logical_and(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_logical_and(bool __x, bool __y)
   { return __x && __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_logical_or(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_logical_or(bool __x, bool __y)
   { return __x || __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_not(bool __x)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_not(bool __x)
   { return !__x; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_and(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_and(bool __x, bool __y)
   { return __x && __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_or(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_or(bool __x, bool __y)
   { return __x || __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_xor(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_xor(bool __x, bool __y)
   { return __x != __y; }
 
   // smart_reference access {{{2
-  _GLIBCXX_SIMD_INTRINSIC
-  constexpr static void _S_set(bool& __k, [[maybe_unused]] int __i,
-			       bool __x) noexcept
+  _GLIBCXX_SIMD_INTRINSIC constexpr static void
+  _S_set(bool& __k, [[maybe_unused]] int __i, bool __x) noexcept
   {
     _GLIBCXX_DEBUG_ASSERT(__i == 0);
     __k = __x;
   }
 
   // _S_masked_assign {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void _S_masked_assign(bool __k, bool& __lhs,
-						       bool __rhs)
+  _GLIBCXX_SIMD_INTRINSIC static void
+  _S_masked_assign(bool __k, bool& __lhs, bool __rhs)
   {
     if (__k)
       __lhs = __rhs;
diff --git a/libstdc++-v3/include/experimental/bits/simd_x86.h b/libstdc++-v3/include/experimental/bits/simd_x86.h
index a9ec5c6f9d8..f8fcf3abe4d 100644
--- a/libstdc++-v3/include/experimental/bits/simd_x86.h
+++ b/libstdc++-v3/include/experimental/bits/simd_x86.h
@@ -40,10 +40,7 @@ _GLIBCXX_SIMD_BEGIN_NAMESPACE
 template <typename _Tp, size_t _Np>
   _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper<__int_for_sizeof_t<_Tp>, _Np>
   __to_masktype(_SimdWrapper<_Tp, _Np> __x)
-  {
-    return reinterpret_cast<__vector_type_t<__int_for_sizeof_t<_Tp>, _Np>>(
-      __x._M_data);
-  }
+  { return reinterpret_cast<__vector_type_t<__int_for_sizeof_t<_Tp>, _Np>>(__x._M_data); }
 
 template <typename _TV,
 	  typename _TVT
@@ -434,7 +431,8 @@ struct _CommonImplX86 : _CommonImplBuiltin
 #ifdef _GLIBCXX_SIMD_WORKAROUND_PR85048
   // _S_converts_via_decomposition {{{
   template <typename _From, typename _To, size_t _ToSize>
-    static constexpr bool _S_converts_via_decomposition()
+    static constexpr bool
+    _S_converts_via_decomposition()
     {
       if constexpr (is_integral_v<
 		      _From> && is_integral_v<_To> && sizeof(_From) == 8
@@ -465,8 +463,8 @@ struct _CommonImplX86 : _CommonImplBuiltin
   using _CommonImplBuiltin::_S_store;
 
   template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __x,
-						 void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_SimdWrapper<_Tp, _Np> __x, void* __addr)
     {
       constexpr size_t _Bytes = _Np * sizeof(_Tp);
 
@@ -702,8 +700,8 @@ struct _CommonImplX86 : _CommonImplBuiltin
   // Requires: _Tp to be an intrinsic type (integers blend per byte) and 16/32
   //           Bytes wide
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_blend_intrin(_Tp __k, _Tp __a,
-						       _Tp __b) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_blend_intrin(_Tp __k, _Tp __a, _Tp __b) noexcept
     {
       static_assert(is_same_v<decltype(__to_intrin(__a)), _Tp>);
       constexpr struct
@@ -843,6 +841,7 @@ template <typename _Abi, typename>
 	= (sizeof(_Tp) >= 4 && __have_avx512f) || __have_avx512bw  ? 64
 	  : (is_floating_point_v<_Tp>&& __have_avx) || __have_avx2 ? 32
 								   : 16;
+
     using _MaskImpl = typename _Abi::_MaskImpl;
 
     // _S_masked_load {{{
@@ -1033,8 +1032,7 @@ template <typename _Abi, typename>
     // _S_masked_store_nocvt {{{
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem,
-			    _SimdWrapper<bool, _Np> __k)
+      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem, _SimdWrapper<bool, _Np> __k)
       {
 	[[maybe_unused]] const auto __vi = __to_intrin(__v);
 	if constexpr (sizeof(__vi) == 64)
@@ -1301,7 +1299,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_multiplies {{{
     template <typename _V, typename _VVT = _VectorTraits<_V>>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr _V _S_multiplies(_V __x, _V __y)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _V
+      _S_multiplies(_V __x, _V __y)
       {
 	using _Tp = typename _VVT::value_type;
 	if (__builtin_is_constant_evaluated() || __x._M_is_constprop()
@@ -2739,7 +2738,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_nearbyint {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nearbyint(_Tp __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_nearbyint(_Tp __x) noexcept
       {
 	if constexpr (_TVT::template _S_is<float, 16>)
 	  return _mm512_roundscale_ps(__x, 0x0c);
@@ -2764,7 +2764,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_rint {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_rint(_Tp __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_rint(_Tp __x) noexcept
       {
 	if constexpr (_TVT::template _S_is<float, 16>)
 	  return _mm512_roundscale_ps(__x, 0x04);
@@ -2912,7 +2913,8 @@ template <typename _Abi, typename>
     // _S_isnonzerovalue_mask {{{
     // (isnormal | is subnormal == !isinf & !isnan & !is zero)
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static auto _S_isnonzerovalue_mask(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static auto
+      _S_isnonzerovalue_mask(_Tp __x)
       {
 	using _Traits = _VectorTraits<_Tp>;
 	if constexpr (__have_avx512dq_vl)
@@ -3179,8 +3181,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_isgreater {{{
     template <typename _Tp, size_t _Np>
-      static constexpr _MaskMember<_Tp> _S_isgreater(_SimdWrapper<_Tp, _Np> __x,
-						     _SimdWrapper<_Tp, _Np> __y)
+      static constexpr _MaskMember<_Tp>
+      _S_isgreater(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
       {
 	const auto __xi = __to_intrin(__x);
 	const auto __yi = __to_intrin(__y);
@@ -3297,8 +3299,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_isless {{{
     template <typename _Tp, size_t _Np>
-      static constexpr _MaskMember<_Tp> _S_isless(_SimdWrapper<_Tp, _Np> __x,
-						  _SimdWrapper<_Tp, _Np> __y)
+      static constexpr _MaskMember<_Tp>
+      _S_isless(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
       {
 	const auto __xi = __to_intrin(__x);
 	const auto __yi = __to_intrin(__y);
@@ -3462,11 +3464,9 @@ template <typename _Abi, typename>
       }
 
     //}}} }}}
-    template <template <typename> class _Op, typename _Tp, typename _K,
-	      size_t _Np>
+    template <template <typename> class _Op, typename _Tp, typename _K, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-      _S_masked_unary(const _SimdWrapper<_K, _Np> __k,
-		      const _SimdWrapper<_Tp, _Np> __v)
+      _S_masked_unary(const _SimdWrapper<_K, _Np> __k, const _SimdWrapper<_Tp, _Np> __v)
       {
 	if (__k._M_is_constprop_none_of())
 	  return __v;
@@ -3543,8 +3543,8 @@ struct _MaskImplX86Mixin
 
   // _S_to_maskvector(bool) {{{
   template <typename _Up, size_t _ToN = 1, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr enable_if_t<
-      is_same_v<_Tp, bool>, _SimdWrapper<_Up, _ToN>>
+    _GLIBCXX_SIMD_INTRINSIC static constexpr
+    enable_if_t<is_same_v<_Tp, bool>, _SimdWrapper<_Up, _ToN>>
     _S_to_maskvector(_Tp __x)
     {
       static_assert(is_same_v<_Up, __int_for_sizeof_t<_Up>>);
@@ -3554,8 +3554,7 @@ struct _MaskImplX86Mixin
 
   // }}}
   // _S_to_maskvector(_SanitizedBitMask) {{{
-  template <typename _Up, size_t _UpN = 0, size_t _Np,
-	    size_t _ToN = _UpN == 0 ? _Np : _UpN>
+  template <typename _Up, size_t _UpN = 0, size_t _Np, size_t _ToN = _UpN == 0 ? _Np : _UpN>
     _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Up, _ToN>
     _S_to_maskvector(_SanitizedBitMask<_Np> __x)
     {
@@ -4626,8 +4625,8 @@ template <typename _Abi, typename>
 
     // _S_store {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __v,
-						   bool* __mem) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static void
+      _S_store(_SimdWrapper<_Tp, _Np> __v, bool* __mem) noexcept
       {
 	if constexpr (__is_avx512_abi<_Abi>())
 	  {
@@ -4791,8 +4790,7 @@ template <typename _Abi, typename>
     // logical and bitwise operators {{{2
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x,
-		     const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
@@ -4813,8 +4811,7 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x,
-		    const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
@@ -4860,8 +4857,7 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
@@ -4882,8 +4878,7 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x,
-		const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
@@ -4904,8 +4899,7 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
@@ -4929,8 +4923,7 @@ template <typename _Abi, typename>
     template <size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
       _S_masked_assign(_SimdWrapper<bool, _Np> __k,
-		       _SimdWrapper<bool, _Np>& __lhs,
-		       _SimdWrapper<bool, _Np> __rhs)
+		       _SimdWrapper<bool, _Np>& __lhs, _SimdWrapper<bool, _Np> __rhs)
       {
 	__lhs._M_data
 	  = (~__k._M_data & __lhs._M_data) | (__k._M_data & __rhs._M_data);
@@ -4952,7 +4945,8 @@ template <typename _Abi, typename>
     //}}}
     // _S_all_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_all_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_all_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -5008,7 +5002,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_any_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_any_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_any_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -5043,7 +5038,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_none_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_none_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_none_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -5078,7 +5074,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_some_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_some_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_some_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -5119,7 +5116,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       {
 	constexpr size_t _Np = simd_size_v<_Tp, _Abi>;
 	const auto __kk = _Abi::_S_masked(__k._M_data)._M_data;

commit 425637cb8f2ddc3f53a9b531899f265c0650e7ed
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Thu Feb 23 14:55:08 2023

    libstdc++: Fix simd compilation with Clang
    
    Clang fails to compile some constant expressions involving simd.
    Therefore, just disable this non-conforming extension for clang.
    
    Fix AVX512 blend implementation for Clang. It was converting the bitmask
    to bool before, which is obviously wrong. Instead use a Clang builtin to
    convert the bitmask to vector-mask before using a vector blend ?:. A
    similar change is required for the masked unary implementation, because
    the GCC builtins do not exist on Clang.
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * include/experimental/bits/simd_detail.h: Don't declare the
            simd API as constexpr with Clang.
            * include/experimental/bits/simd_x86.h (__movm): New.
            (_S_blend_avx512): Resolve FIXME. Implement blend using __movm
            and ?:.
            (_SimdImplX86::_S_masked_unary): Clang does not implement the
            same builtins. Implement the function using __movm, ?:, and -
            operators on vector_size types instead.
    
    (cherry picked from commit 8ff3ca2d94721fab78f167d435d4ea4fa4fdca6a)

diff --git a/libstdc++-v3/include/experimental/bits/simd_detail.h b/libstdc++-v3/include/experimental/bits/simd_detail.h
index fee7f871176..dc2712dee9a 100644
--- a/libstdc++-v3/include/experimental/bits/simd_detail.h
+++ b/libstdc++-v3/include/experimental/bits/simd_detail.h
@@ -267,7 +267,7 @@
 #define _GLIBCXX_SIMD_IS_UNLIKELY(__x) __builtin_expect(__x, 0)
 #define _GLIBCXX_SIMD_IS_LIKELY(__x) __builtin_expect(__x, 1)
 
-#if defined __STRICT_ANSI__ && __STRICT_ANSI__
+#if __STRICT_ANSI__ || defined __clang__
 #define _GLIBCXX_SIMD_CONSTEXPR
 #define _GLIBCXX_SIMD_USE_CONSTEXPR_API const
 #else
diff --git a/libstdc++-v3/include/experimental/bits/simd_x86.h b/libstdc++-v3/include/experimental/bits/simd_x86.h
index f8fcf3abe4d..cb5ec1aa86e 100644
--- a/libstdc++-v3/include/experimental/bits/simd_x86.h
+++ b/libstdc++-v3/include/experimental/bits/simd_x86.h
@@ -363,6 +363,53 @@ template <typename _Tp>
 
 // }}}
 
+#ifdef __clang__
+template <size_t _Np, typename _Tp, typename _Kp>
+  _GLIBCXX_SIMD_INTRINSIC constexpr auto
+  __movm(_Kp __k) noexcept
+  {
+    static_assert(is_unsigned_v<_Kp>);
+    if constexpr (sizeof(_Tp) == 1 && __have_avx512bw)
+      {
+	if constexpr (_Np <= 16 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2b128(__k);
+	else if constexpr (_Np <= 32 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2b256(__k);
+	else
+	  return __builtin_ia32_cvtmask2b512(__k);
+      }
+    else if constexpr (sizeof(_Tp) == 2 && __have_avx512bw)
+      {
+	if constexpr (_Np <= 8 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2w128(__k);
+	else if constexpr (_Np <= 16 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2w256(__k);
+	else
+	  return __builtin_ia32_cvtmask2w512(__k);
+      }
+    else if constexpr (sizeof(_Tp) == 4 && __have_avx512dq)
+      {
+	if constexpr (_Np <= 4 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2d128(__k);
+	else if constexpr (_Np <= 8 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2d256(__k);
+	else
+	  return __builtin_ia32_cvtmask2d512(__k);
+      }
+    else if constexpr (sizeof(_Tp) == 8 && __have_avx512dq)
+      {
+	if constexpr (_Np <= 2 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2q128(__k);
+	else if constexpr (_Np <= 4 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2q256(__k);
+	else
+	  return __builtin_ia32_cvtmask2q512(__k);
+      }
+    else
+      __assert_unreachable<_Tp>();
+  }
+#endif // __clang__
+
 #ifdef _GLIBCXX_SIMD_WORKAROUND_PR85048
 #include "simd_x86_conversions.h"
 #endif
@@ -619,14 +666,13 @@ struct _CommonImplX86 : _CommonImplBuiltin
     _GLIBCXX_SIMD_INTRINSIC static _TV
     _S_blend_avx512(const _Kp __k, const _TV __a, const _TV __b) noexcept
     {
-#ifdef __clang__
-      // FIXME: this does a boolean choice, not a blend
-      return __k ? __a : __b;
-#else
       static_assert(__is_vector_type_v<_TV>);
       using _Tp = typename _VectorTraits<_TV>::value_type;
       static_assert(sizeof(_TV) >= 16);
       static_assert(sizeof(_Tp) <= 8);
+#ifdef __clang__
+      return __movm<_VectorTraits<_TV>::_S_full_size, _Tp>(__k) ? __b : __a;
+#else
       using _IntT
 	= conditional_t<(sizeof(_Tp) > 2),
 			conditional_t<sizeof(_Tp) == 4, int, long long>,
@@ -3483,6 +3529,9 @@ template <typename _Abi, typename>
 	    // optimize masked unary increment and decrement as masked sub +/-1
 	    constexpr int __pm_one
 	      = is_same_v<_Op<void>, __increment<void>> ? -1 : 1;
+#ifdef __clang__
+	    return __movm<_Np, _Tp>(__k._M_data) ? __v._M_data - __pm_one : __v._M_data;
+#else // __clang__
 	    if constexpr (is_integral_v<_Tp>)
 	      {
 		constexpr bool __lp64 = sizeof(long) == sizeof(long long);
@@ -3526,6 +3575,7 @@ template <typename _Abi, typename>
 		_GLIBCXX_SIMD_MASK_SUB(8, 16, subpd128);
 #undef _GLIBCXX_SIMD_MASK_SUB
 	      }
+#endif // __clang__
 	  }
 	else
 	  return _Base::template _S_masked_unary<_Op>(__k, __v);

commit 336c91bf7f611d04b5fbcb5f6fa39bfa258a16e2
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Wed Mar 22 08:12:08 2023

    libstdc++: Fix operator% implementation for Clang
    
    This resolves a regression of my previous fix where Clang would ICE on
    _S_divides.
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * include/experimental/bits/simd_x86.h (_SimdImplX86): Use
            _Base::_S_divides if the optimized _S_divides function is hidden
            via the preprocessor.
    
    (cherry picked from commit 1a62008123694b2ac07f28e25fc6e5ff371925f5)

diff --git a/libstdc++-v3/include/experimental/bits/simd_x86.h b/libstdc++-v3/include/experimental/bits/simd_x86.h
index cb5ec1aa86e..7fd1d958c08 100644
--- a/libstdc++-v3/include/experimental/bits/simd_x86.h
+++ b/libstdc++-v3/include/experimental/bits/simd_x86.h
@@ -1524,6 +1524,8 @@ template <typename _Abi, typename>
 	  */
 	return _Base::_S_divides(__x, __y);
       }
+#else
+    using _Base::_S_divides;
 #endif // _GLIBCXX_SIMD_WORKAROUND_PR90993
 
     // }}}

commit 36a02f8ce382c0ed40f22180da2d0c039324cc9f
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Wed Mar 22 08:12:08 2023

    libstdc++: Add missing trait is_simd_flag_type
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * include/experimental/bits/simd.h (is_simd_flag_type): New.
            (_IsSimdFlagType): New.
            (copy_from, copy_to, load ctors): Constrain _Flags using
            _IsSimdFlagType.
    
    (cherry picked from commit 97383b4116ea63486eb5bfb0a7140871bed75fb4)

diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h
index ec213468f50..2ce6950b163 100644
--- a/libstdc++-v3/include/experimental/bits/simd.h
+++ b/libstdc++-v3/include/experimental/bits/simd.h
@@ -2837,6 +2837,32 @@ template <typename _Tp>
 } // namespace simd_abi
 
 // traits {{{1
+template <typename _Tp>
+  struct is_simd_flag_type
+  : false_type
+  {};
+
+template <>
+  struct is_simd_flag_type<element_aligned_tag>
+  : true_type
+  {};
+
+template <>
+  struct is_simd_flag_type<vector_aligned_tag>
+  : true_type
+  {};
+
+template <size_t _Np>
+  struct is_simd_flag_type<overaligned_tag<_Np>>
+  : __bool_constant<(_Np > 0) and __has_single_bit(_Np)>
+  {};
+
+template <typename _Tp>
+  inline constexpr bool is_simd_flag_type_v = is_simd_flag_type<_Tp>::value;
+
+template <typename _Tp, typename = enable_if_t<is_simd_flag_type_v<_Tp>>>
+  using _IsSimdFlagType = _Tp;
+
 // is_abi_tag {{{2
 template <typename _Tp, typename = void_t<>>
   struct is_abi_tag : false_type {};
@@ -3308,7 +3334,7 @@ template <typename _M, typename _Tp>
 
     template <typename _Up, typename _Flags>
       [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	return {__private_init,
 		_Impl::_S_masked_load(__data(_M_value), __data(_M_k),
@@ -3317,7 +3343,7 @@ template <typename _M, typename _Tp>
 
     template <typename _Up, typename _Flags>
       _GLIBCXX_SIMD_INTRINSIC void
-      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	_Impl::_S_masked_store(__data(_M_value),
 			       _Flags::template _S_apply<_V>(__mem),
@@ -3363,12 +3389,12 @@ template <typename _Tp>
 
     template <typename _Up, typename _Flags>
       [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       { return _M_k ? static_cast<_V>(__mem[0]) : _M_value; }
 
     template <typename _Up, typename _Flags>
       _GLIBCXX_SIMD_INTRINSIC void
-      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	if (_M_k)
 	  __mem[0] = _M_value;
@@ -3466,7 +3492,7 @@ template <typename _M, typename _Tp>
     // intentionally hides const_where_expression::copy_from
     template <typename _Up, typename _Flags>
       _GLIBCXX_SIMD_INTRINSIC void
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) &&
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) &&
       {
 	__data(_M_value) = _Impl::_S_masked_load(__data(_M_value), __data(_M_k),
 						 _Flags::template _S_apply<_Tp>(__mem));
@@ -3529,7 +3555,7 @@ template <typename _Tp>
     // intentionally hides const_where_expression::copy_from
     template <typename _Up, typename _Flags>
       _GLIBCXX_SIMD_INTRINSIC void
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) &&
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) &&
       { if (_M_k) _M_value = __mem[0]; }
   };
 
@@ -4574,12 +4600,12 @@ template <typename _Tp, typename _Abi>
     // load constructor {{{
     template <typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE
-      simd_mask(const value_type* __mem, _Flags)
+      simd_mask(const value_type* __mem, _IsSimdFlagType<_Flags>)
       : _M_data(_Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem))) {}
 
     template <typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE
-      simd_mask(const value_type* __mem, simd_mask __k, _Flags)
+      simd_mask(const value_type* __mem, simd_mask __k, _IsSimdFlagType<_Flags>)
       : _M_data{}
       {
 	_M_data = _Impl::_S_masked_load(_M_data, __k._M_data,
@@ -4590,14 +4616,14 @@ template <typename _Tp, typename _Abi>
     // loads [simd_mask.load] {{{
     template <typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_from(const value_type* __mem, _Flags)
+      copy_from(const value_type* __mem, _IsSimdFlagType<_Flags>)
       { _M_data = _Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem)); }
 
     // }}}
     // stores [simd_mask.store] {{{
     template <typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_to(value_type* __mem, _Flags) const
+      copy_to(value_type* __mem, _IsSimdFlagType<_Flags>) const
       { _Impl::_S_store(_M_data, _Flags::template _S_apply<simd_mask>(__mem)); }
 
     // }}}
@@ -5210,7 +5236,7 @@ template <typename _Tp, typename _Abi>
     // load constructor
     template <typename _Up, typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE
-      simd(const _Up* __mem, _Flags)
+      simd(const _Up* __mem, _IsSimdFlagType<_Flags>)
       : _M_data(
 	  _Impl::_S_load(_Flags::template _S_apply<simd>(__mem), _S_type_tag))
       {}
@@ -5218,7 +5244,7 @@ template <typename _Tp, typename _Abi>
     // loads [simd.load]
     template <typename _Up, typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_from(const _Vectorizable<_Up>* __mem, _Flags)
+      copy_from(const _Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>)
       {
 	_M_data = static_cast<decltype(_M_data)>(
 	  _Impl::_S_load(_Flags::template _S_apply<simd>(__mem), _S_type_tag));
@@ -5227,7 +5253,7 @@ template <typename _Tp, typename _Abi>
     // stores [simd.store]
     template <typename _Up, typename _Flags>
       _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_to(_Vectorizable<_Up>* __mem, _Flags) const
+      copy_to(_Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>) const
       {
 	_Impl::_S_store(_M_data, _Flags::template _S_apply<simd>(__mem),
 			_S_type_tag);

commit 8d23bf575e12c0e7dd57fe409916402d354416e9
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Mon May 22 16:58:30 2023

    libstdc++: Resolve -Wunused-variable warnings in stdx::simd and tests
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * include/experimental/bits/simd_builtin.h (_S_fpclassify): Move
            __infn into #ifdef'ed block.
            * testsuite/experimental/simd/tests/fpclassify.cc: Declare
            constants only when used.
            * testsuite/experimental/simd/tests/frexp.cc: Likewise.
            * testsuite/experimental/simd/tests/logarithm.cc: Likewise.
            * testsuite/experimental/simd/tests/trunc_ceil_floor.cc:
            Likewise.
            * testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc:
            Move totest and expect1 into #ifdef'ed block.
    
    (cherry picked from commit a7129e82bed1bd4f513fc3c3f401721e2c96a865)

diff --git a/libstdc++-v3/include/experimental/bits/simd_builtin.h b/libstdc++-v3/include/experimental/bits/simd_builtin.h
index f7a75bf28ce..bccca5420e6 100644
--- a/libstdc++-v3/include/experimental/bits/simd_builtin.h
+++ b/libstdc++-v3/include/experimental/bits/simd_builtin.h
@@ -2370,12 +2370,12 @@ template <typename _Abi, typename>
 	constexpr size_t _NI = sizeof(__xn) / sizeof(_I);
 	_GLIBCXX_SIMD_USE_CONSTEXPR auto __minn
 	  = __vector_bitcast<_I>(__vector_broadcast<_NI>(__norm_min_v<_Tp>));
-	_GLIBCXX_SIMD_USE_CONSTEXPR auto __infn
-	  = __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>));
 
 	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_normal
 	  = __vector_broadcast<_NI, _I>(FP_NORMAL);
 #if !__FINITE_MATH_ONLY__
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __infn
+	  = __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>));
 	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_nan
 	  = __vector_broadcast<_NI, _I>(FP_NAN);
 	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_infinite
diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/fpclassify.cc b/libstdc++-v3/testsuite/experimental/simd/tests/fpclassify.cc
index b7224b0d6e9..8ac28ef8ecb 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/fpclassify.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/fpclassify.cc
@@ -40,9 +40,11 @@ template <typename V>
   {
     using T = typename V::value_type;
     using intv = std::experimental::fixed_size_simd<int, V::size()>;
+#if __GCC_IEC_559 >= 2
     constexpr T inf = std::__infinity_v<T>;
     constexpr T denorm_min = std::__infinity_v<T>;
     constexpr T nan = std::__quiet_NaN_v<T>;
+#endif
     constexpr T max = std::__finite_max_v<T>;
     constexpr T norm_min = std::__norm_min_v<T>;
     test_values<V>(
diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/frexp.cc b/libstdc++-v3/testsuite/experimental/simd/tests/frexp.cc
index eecc5afd619..b3e03ec070c 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/frexp.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/frexp.cc
@@ -27,11 +27,17 @@ template <typename V>
   {
     using int_v = std::experimental::fixed_size_simd<int, V::size()>;
     using T = typename V::value_type;
+#if __GCC_IEC_559 >= 2 || defined __STDC_IEC_559__
     constexpr auto denorm_min = std::__denorm_min_v<T>;
+#endif
+#if __GCC_IEC_559 >= 2
     constexpr auto norm_min = std::__norm_min_v<T>;
+#endif
     constexpr auto max = std::__finite_max_v<T>;
+#if defined __STDC_IEC_559__
     constexpr auto nan = std::__quiet_NaN_v<T>;
     constexpr auto inf = std::__infinity_v<T>;
+#endif
     test_values<V>(
       {0, 0.25, 0.5, 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
        20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 32, 31, -0., -0.25, -0.5, -1,
diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc b/libstdc++-v3/testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc
index 451214f56e5..8c4daec4c14 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc
@@ -139,7 +139,6 @@ template <typename V>
 	if (modf_is_broken)
 	  return;
 	V integral = {};
-	const V totest = modf(input, &integral);
 	auto&& expected = [&](const auto& v) -> std::pair<const V, const V> {
 	  std::pair<V, V> tmp = {};
 	  using std::modf;
@@ -151,8 +150,9 @@ template <typename V>
 	    }
 	  return tmp;
 	};
-	const auto expect1 = expected(input);
 #ifdef __STDC_IEC_559__
+	const V totest = modf(input, &integral);
+	const auto expect1 = expected(input);
 	COMPARE(isnan(totest), isnan(expect1.first))
 	  << "modf(" << input << ", iptr) = " << totest << " != " << expect1;
 	COMPARE(isnan(integral), isnan(expect1.second))
diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/logarithm.cc b/libstdc++-v3/testsuite/experimental/simd/tests/logarithm.cc
index df066fd7297..a56f764177c 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/logarithm.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/logarithm.cc
@@ -30,11 +30,13 @@ template <typename V>
     vir::test::setFuzzyness<double>(1);
 
     using T = typename V::value_type;
+#ifdef __STDC_IEC_559__
     constexpr T nan = std::__quiet_NaN_v<T>;
     constexpr T inf = std::__infinity_v<T>;
     constexpr T denorm_min = std::__denorm_min_v<T>;
-    constexpr T norm_min = std::__norm_min_v<T>;
     constexpr T min = std::__finite_min_v<T>;
+#endif
+    constexpr T norm_min = std::__norm_min_v<T>;
     constexpr T max = std::__finite_max_v<T>;
     test_values<V>({1,
 		    2,
diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/trunc_ceil_floor.cc b/libstdc++-v3/testsuite/experimental/simd/tests/trunc_ceil_floor.cc
index c5c08d494e8..31aebfd03ca 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/trunc_ceil_floor.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/trunc_ceil_floor.cc
@@ -25,8 +25,10 @@ template <typename V>
   test()
   {
     using T = typename V::value_type;
+#ifdef __STDC_IEC_559__
     constexpr T inf = std::__infinity_v<T>;
     constexpr T denorm_min = std::__denorm_min_v<T>;
+#endif
     constexpr T norm_min = std::__norm_min_v<T>;
     constexpr T max = std::__finite_max_v<T>;
     constexpr T min = std::__finite_min_v<T>;

commit 3acbaf1b25321508d780a8220b772fc9cd871b13
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Thu Mar 23 09:32:58 2023

    libstdc++: Add missing constexpr to simd
    
    The constexpr API is only available with -std=gnu++XX (and proposed for
    C++26). The proposal is to have the complete simd API usable in constant
    expressions.
    
    This patch resolves several issues with using simd in constant
    expressions.
    
    Issues why constant_evaluated branches are necessary:
    * subscripting vector builtins is not allowed in constant expressions
    * if the implementation needs/uses memcpy
    * if the implementation would otherwise call SIMD intrinsics/builtins
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/109261
            * include/experimental/bits/simd.h (_SimdWrapper::_M_set):
            Avoid vector builtin subscripting in constant expressions.
            (resizing_simd_cast): Avoid memcpy if constant_evaluated.
            (const_where_expression, where_expression, where)
            (__extract_part, simd_mask, _SimdIntOperators, simd): Add either
            _GLIBCXX_SIMD_CONSTEXPR (on public APIs), or constexpr (on
            internal APIs).
            * include/experimental/bits/simd_builtin.h (__vector_permute)
            (__vector_shuffle, __extract_part, _GnuTraits::_SimdCastType1)
            (_GnuTraits::_SimdCastType2, _SimdImplBuiltin)
            (_MaskImplBuiltin::_S_store): Add constexpr.
            (_CommonImplBuiltin::_S_store_bool_array)
            (_SimdImplBuiltin::_S_load, _SimdImplBuiltin::_S_store)
            (_SimdImplBuiltin::_S_reduce, _MaskImplBuiltin::_S_load): Add
            constant_evaluated case.
            * include/experimental/bits/simd_fixed_size.h
            (_S_masked_load): Reword comment.
            (__tuple_element_meta, __make_meta, _SimdTuple::_M_apply_r)
            (_SimdTuple::_M_subscript_read, _SimdTuple::_M_subscript_write)
            (__make_simd_tuple, __optimize_simd_tuple, __extract_part)
            (__autocvt_to_simd, _Fixed::__traits::_SimdBase)
            (_Fixed::__traits::_SimdCastType, _SimdImplFixedSize): Add
            constexpr.
            (_SimdTuple::operator[], _M_set): Add constexpr and add
            constant_evaluated case.
            (_MaskImplFixedSize::_S_load): Add constant_evaluated case.
            * include/experimental/bits/simd_scalar.h: Add constexpr.
    
            * include/experimental/bits/simd_x86.h (_CommonImplX86): Add
            constexpr and add constant_evaluated case.
            (_SimdImplX86::_S_equal_to, _S_not_equal_to, _S_less)
            (_S_less_equal): Value-initialize to satisfy constexpr
            evaluation.
            (_MaskImplX86::_S_load): Add constant_evaluated case.
            (_MaskImplX86::_S_store): Add constexpr and constant_evaluated
            case. Value-initialize local variables.
            (_MaskImplX86::_S_logical_and, _S_logical_or, _S_bit_not)
            (_S_bit_and, _S_bit_or, _S_bit_xor): Add constant_evaluated
            case.
            * testsuite/experimental/simd/pr109261_constexpr_simd.cc: New
            test.
    
    (cherry picked from commit da579188807ede4ee9466d0b5bf51559c96a0b51)

diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h
index 2ce6950b163..c8419156ece 100644
--- a/libstdc++-v3/include/experimental/bits/simd.h
+++ b/libstdc++-v3/include/experimental/bits/simd.h
@@ -2675,7 +2675,14 @@ template <typename _Tp, size_t _Width>
 
     _GLIBCXX_SIMD_INTRINSIC constexpr void
     _M_set(size_t __i, _Tp __x)
-    { _M_data[__i] = __x; }
+    {
+      if (__builtin_is_constant_evaluated())
+	_M_data = __generate_from_n_evaluations<_Width, _BuiltinType>([&](auto __j) {
+		    return __j == __i ? __x : _M_data[__j()];
+		  });
+      else
+	_M_data[__i] = __x;
+    }
 
     _GLIBCXX_SIMD_INTRINSIC
     constexpr bool
@@ -3186,6 +3193,10 @@ template <typename _Tp, typename _Up, typename _Ap>
   {
     if constexpr (is_same_v<typename _Tp::abi_type, _Ap>)
       return __x;
+    else if (__builtin_is_constant_evaluated())
+      return _Tp([&](auto __i) constexpr {
+	       return __i < simd_size_v<_Up, _Ap> ? __x[__i] : _Up();
+	     });
     else if constexpr (simd_size_v<_Up, _Ap> == 1)
       {
 	_Tp __r{};
@@ -3321,10 +3332,11 @@ template <typename _M, typename _Tp>
 
     const_where_expression& operator=(const const_where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC const_where_expression(const _M& __kk, const _Tp& dd)
-      : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    const_where_expression(const _M& __kk, const _Tp& dd)
+    : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
 
-    _GLIBCXX_SIMD_INTRINSIC _V
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
     operator-() const&&
     {
       return {__private_init,
@@ -3333,7 +3345,7 @@ template <typename _M, typename _Tp>
     }
 
     template <typename _Up, typename _Flags>
-      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V
+      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
       copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	return {__private_init,
@@ -3342,7 +3354,7 @@ template <typename _M, typename _Tp>
       }
 
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
       copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	_Impl::_S_masked_store(__data(_M_value),
@@ -3381,19 +3393,21 @@ template <typename _Tp>
     const_where_expression(const const_where_expression&) = delete;
     const_where_expression& operator=(const const_where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC const_where_expression(const bool __kk, const _Tp& dd)
-      : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    const_where_expression(const bool __kk, const _Tp& dd)
+    : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
 
-    _GLIBCXX_SIMD_INTRINSIC _V operator-() const&&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
+    operator-() const&&
     { return _M_k ? -_M_value : _M_value; }
 
     template <typename _Up, typename _Flags>
-      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V
+      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
       copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       { return _M_k ? static_cast<_V>(__mem[0]) : _M_value; }
 
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
       copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	if (_M_k)
@@ -3419,18 +3433,21 @@ template <typename _M, typename _Tp>
       is_same<typename _M::abi_type, typename _Tp::abi_type>::value, "");
     static_assert(_M::size() == _Tp::size(), "");
 
-    _GLIBCXX_SIMD_INTRINSIC friend _Tp& __get_lvalue(where_expression& __x)
+    _GLIBCXX_SIMD_INTRINSIC friend constexpr _Tp&
+    __get_lvalue(where_expression& __x)
     { return __x._M_value; }
 
   public:
     where_expression(const where_expression&) = delete;
     where_expression& operator=(const where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC where_expression(const _M& __kk, _Tp& dd)
-      : const_where_expression<_M, _Tp>(__kk, dd) {}
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+    where_expression(const _M& __kk, _Tp& dd)
+    : const_where_expression<_M, _Tp>(__kk, dd) {}
 
     template <typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC void operator=(_Up&& __x) &&
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+      operator=(_Up&& __x) &&
       {
 	_Impl::_S_masked_assign(__data(_M_k), __data(_M_value),
 				__to_value_type_or_member_type<_Tp>(
@@ -3439,7 +3456,8 @@ template <typename _M, typename _Tp>
 
 #define _GLIBCXX_SIMD_OP_(__op, __name)                                        \
   template <typename _Up>                                                      \
-    _GLIBCXX_SIMD_INTRINSIC void operator __op##=(_Up&& __x)&&                 \
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void                       \
+    operator __op##=(_Up&& __x)&&                                              \
     {                                                                          \
       _Impl::template _S_masked_cassign(                                       \
 	__data(_M_k), __data(_M_value),                                        \
@@ -3461,28 +3479,28 @@ template <typename _M, typename _Tp>
     _GLIBCXX_SIMD_OP_(>>, _S_shift_right);
 #undef _GLIBCXX_SIMD_OP_
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator++() &&
     {
       __data(_M_value)
 	= _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator++(int) &&
     {
       __data(_M_value)
 	= _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator--() &&
     {
       __data(_M_value)
 	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator--(int) &&
     {
       __data(_M_value)
@@ -3491,7 +3509,7 @@ template <typename _M, typename _Tp>
 
     // intentionally hides const_where_expression::copy_from
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
       copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) &&
       {
 	__data(_M_value) = _Impl::_S_masked_load(__data(_M_value), __data(_M_k),
@@ -3513,13 +3531,13 @@ template <typename _Tp>
     where_expression(const where_expression&) = delete;
     where_expression& operator=(const where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
     where_expression(const _M& __kk, _Tp& dd)
     : const_where_expression<_M, _Tp>(__kk, dd) {}
 
 #define _GLIBCXX_SIMD_OP_(__op)                                                \
     template <typename _Up>                                                    \
-      _GLIBCXX_SIMD_INTRINSIC void                                             \
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void                     \
       operator __op(_Up&& __x)&&                                               \
       { if (_M_k) _M_value __op static_cast<_Up&&>(__x); }
 
@@ -3536,68 +3554,71 @@ template <typename _Tp>
     _GLIBCXX_SIMD_OP_(>>=)
   #undef _GLIBCXX_SIMD_OP_
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator++() &&
     { if (_M_k) ++_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator++(int) &&
     { if (_M_k) ++_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator--() &&
     { if (_M_k) --_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
     operator--(int) &&
     { if (_M_k) --_M_value; }
 
     // intentionally hides const_where_expression::copy_from
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
       copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) &&
       { if (_M_k) _M_value = __mem[0]; }
   };
 
 // where {{{1
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+  where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
   where(const typename simd<_Tp, _Ap>::mask_type& __k, simd<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
   const_where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
   where(const typename simd<_Tp, _Ap>::mask_type& __k, const simd<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
   where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
   where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k, simd_mask<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
   const_where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
   where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k, const simd_mask<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp>
-  _GLIBCXX_SIMD_INTRINSIC where_expression<bool, _Tp>
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR where_expression<bool, _Tp>
   where(_ExactBool __k, _Tp& __value)
   { return {__k, __value}; }
 
 template <typename _Tp>
-  _GLIBCXX_SIMD_INTRINSIC const_where_expression<bool, _Tp>
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR const_where_expression<bool, _Tp>
   where(_ExactBool __k, const _Tp& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
-  void where(bool __k, simd<_Tp, _Ap>& __value) = delete;
+  _GLIBCXX_SIMD_CONSTEXPR void
+  where(bool __k, simd<_Tp, _Ap>& __value) = delete;
 
 template <typename _Tp, typename _Ap>
-  void where(bool __k, const simd<_Tp, _Ap>& __value) = delete;
+  _GLIBCXX_SIMD_CONSTEXPR void
+  where(bool __k, const simd<_Tp, _Ap>& __value) = delete;
 
 // proposed mask iterations {{{1
 namespace __proposed {
@@ -3820,12 +3841,12 @@ template <size_t... _Sizes, typename _Tp, typename _Ap,
 
 // __extract_part {{{
 template <int _Index, int _Total, int _Combine = 1, typename _Tp, size_t _Np>
-  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST constexpr
   _SimdWrapper<_Tp, _Np / _Total * _Combine>
   __extract_part(const _SimdWrapper<_Tp, _Np> __x);
 
 template <int _Index, int _Parts, int _Combine = 1, typename _Tp, typename _A0, typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC auto
+  _GLIBCXX_SIMD_INTRINSIC constexpr auto
   __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x);
 
 // }}}
@@ -4551,7 +4572,7 @@ template <typename _Tp, typename _Abi>
 
     // }}}
     // access to internal representation (optional feature) {{{
-    _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR explicit
     simd_mask(typename _Traits::_MaskCastType __init)
     : _M_data{__init} {}
     // conversions to internal type is done in _MaskBase
@@ -4562,11 +4583,11 @@ template <typename _Tp, typename _Abi>
     // Conversion of simd_mask to and from bitset makes it much easier to
     // interface with other facilities. I suggest adding `static
     // simd_mask::from_bitset` and `simd_mask::to_bitset`.
-    _GLIBCXX_SIMD_ALWAYS_INLINE static simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR static simd_mask
     __from_bitset(bitset<size()> bs)
     { return {__bitset_init, bs}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE bitset<size()>
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR bitset<size()>
     __to_bitset() const
     { return _Impl::_S_to_bits(_M_data)._M_to_bitset(); }
 
@@ -4591,7 +4612,7 @@ template <typename _Tp, typename _Abi>
     template <typename _Up, typename = enable_if_t<conjunction<
 			      is_same<abi_type, simd_abi::fixed_size<size()>>,
 			      is_same<_Up, _Up>>::value>>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
       simd_mask(const simd_mask<_Up, simd_abi::fixed_size<size()>>& __x)
       : _M_data(_Impl::_S_from_bitmask(__data(__x), _S_type_tag)) {}
   #endif
@@ -4599,12 +4620,12 @@ template <typename _Tp, typename _Abi>
     // }}}
     // load constructor {{{
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
       simd_mask(const value_type* __mem, _IsSimdFlagType<_Flags>)
       : _M_data(_Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem))) {}
 
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
       simd_mask(const value_type* __mem, simd_mask __k, _IsSimdFlagType<_Flags>)
       : _M_data{}
       {
@@ -4615,20 +4636,20 @@ template <typename _Tp, typename _Abi>
     // }}}
     // loads [simd_mask.load] {{{
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
       copy_from(const value_type* __mem, _IsSimdFlagType<_Flags>)
       { _M_data = _Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem)); }
 
     // }}}
     // stores [simd_mask.store] {{{
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
       copy_to(value_type* __mem, _IsSimdFlagType<_Flags>) const
       { _Impl::_S_store(_M_data, _Flags::template _S_apply<simd_mask>(__mem)); }
 
     // }}}
     // scalar access {{{
-    _GLIBCXX_SIMD_ALWAYS_INLINE reference
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR reference
     operator[](size_t __i)
     {
       if (__i >= size())
@@ -4636,7 +4657,7 @@ template <typename _Tp, typename _Abi>
       return {_M_data, int(__i)};
     }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE value_type
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR value_type
     operator[](size_t __i) const
     {
       if (__i >= size())
@@ -4649,7 +4670,7 @@ template <typename _Tp, typename _Abi>
 
     // }}}
     // negation {{{
-    _GLIBCXX_SIMD_ALWAYS_INLINE simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR simd_mask
     operator!() const
     { return {__private_init, _Impl::_S_bit_not(_M_data)}; }
 
@@ -4659,7 +4680,7 @@ template <typename _Tp, typename _Abi>
     // simd_mask<int> && simd_mask<uint> needs disambiguation
     template <typename _Up, typename _A2,
 	      typename = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
-      _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
       operator&&(const simd_mask& __x, const simd_mask<_Up, _A2>& __y)
       {
 	return {__private_init,
@@ -4668,7 +4689,7 @@ template <typename _Tp, typename _Abi>
 
     template <typename _Up, typename _A2,
 	      typename = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
-      _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
       operator||(const simd_mask& __x, const simd_mask<_Up, _A2>& __y)
       {
 	return {__private_init,
@@ -4676,41 +4697,41 @@ template <typename _Tp, typename _Abi>
       }
   #endif // _GLIBCXX_SIMD_ENABLE_IMPLICIT_MASK_CAST
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator&&(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_logical_and(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator||(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_logical_or(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator&(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_bit_and(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator|(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_bit_or(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator^(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_bit_xor(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask&
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask&
     operator&=(simd_mask& __x, const simd_mask& __y)
     {
       __x._M_data = _Impl::_S_bit_and(__x._M_data, __y._M_data);
       return __x;
     }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask&
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask&
     operator|=(simd_mask& __x, const simd_mask& __y)
     {
       __x._M_data = _Impl::_S_bit_or(__x._M_data, __y._M_data);
       return __x;
     }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask&
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask&
     operator^=(simd_mask& __x, const simd_mask& __y)
     {
       __x._M_data = _Impl::_S_bit_xor(__x._M_data, __y._M_data);
@@ -4747,7 +4768,8 @@ template <typename _Tp, typename _Abi>
 
     // }}}
     // bitset_init ctor {{{
-    _GLIBCXX_SIMD_INTRINSIC simd_mask(_BitsetInit, bitset<size()> __init)
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    simd_mask(_BitsetInit, bitset<size()> __init)
     : _M_data(_Impl::_S_from_bitmask(_SanitizedBitMask<size()>(__init), _S_type_tag))
     {}
 
@@ -5015,7 +5037,8 @@ template <typename _V, typename _Tp, typename _Abi>
   {
     using _Impl = typename _SimdTraits<_Tp, _Abi>::_SimdImpl;
 
-    _GLIBCXX_SIMD_INTRINSIC const _V& __derived() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr const _V&
+    __derived() const
     { return *static_cast<const _V*>(this); }
 
     template <typename _Up>
@@ -5235,7 +5258,7 @@ template <typename _Tp, typename _Abi>
 
     // load constructor
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
       simd(const _Up* __mem, _IsSimdFlagType<_Flags>)
       : _M_data(
 	  _Impl::_S_load(_Flags::template _S_apply<simd>(__mem), _S_type_tag))
@@ -5243,7 +5266,7 @@ template <typename _Tp, typename _Abi>
 
     // loads [simd.load]
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
       copy_from(const _Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>)
       {
 	_M_data = static_cast<decltype(_M_data)>(
@@ -5252,7 +5275,7 @@ template <typename _Tp, typename _Abi>
 
     // stores [simd.store]
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
       copy_to(_Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>) const
       {
 	_Impl::_S_store(_M_data, _Flags::template _S_apply<simd>(__mem),
@@ -5424,7 +5447,7 @@ template <typename _Tp, typename _Abi>
     }
 
   private:
-    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR static mask_type
+    _GLIBCXX_SIMD_INTRINSIC static constexpr mask_type
     _S_make_mask(typename mask_type::_MemberType __k)
     { return {__private_init, __k}; }
 
diff --git a/libstdc++-v3/include/experimental/bits/simd_builtin.h b/libstdc++-v3/include/experimental/bits/simd_builtin.h
index bccca5420e6..9ea6259bfda 100644
--- a/libstdc++-v3/include/experimental/bits/simd_builtin.h
+++ b/libstdc++-v3/include/experimental/bits/simd_builtin.h
@@ -52,7 +52,7 @@ template <typename _V, typename = _VectorTraits<_V>>
 // Index == -1 requests zeroing of the output element
 template <int... _Indices, typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 	  typename = __detail::__odr_helper>
-  _Tp
+  constexpr _Tp
   __vector_permute(_Tp __x)
   {
     static_assert(sizeof...(_Indices) == _TVT::_S_full_size);
@@ -65,7 +65,7 @@ template <int... _Indices, typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 // Index == -1 requests zeroing of the output element
 template <int... _Indices, typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 	  typename = __detail::__odr_helper>
-  _Tp
+  constexpr _Tp
   __vector_shuffle(_Tp __x, _Tp __y)
   {
     return _Tp{(_Indices == -1 ? 0
@@ -205,7 +205,7 @@ template <unsigned __shift, typename _Tp, typename _TVT = _VectorTraits<_Tp>>
 // }}}
 // __extract_part(_SimdWrapper<_Tp, _Np>) {{{
 template <int _Index, int _Total, int _Combine, typename _Tp, size_t _Np>
-  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST constexpr
   _SimdWrapper<_Tp, _Np / _Total * _Combine>
   __extract_part(const _SimdWrapper<_Tp, _Np> __x)
   {
@@ -905,10 +905,10 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
       _SimdMember _M_data;
 
     public:
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       _SimdCastType1(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {}
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       operator _SimdMember() const { return _M_data; }
     };
 
@@ -919,13 +919,13 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
       _SimdMember _M_data;
 
     public:
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       _SimdCastType2(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {}
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       _SimdCastType2(_Bp __b) : _M_data(__b) {}
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       operator _SimdMember() const { return _M_data; }
     };
 
@@ -1345,6 +1345,11 @@ struct _CommonImplBuiltin
     {
       if constexpr (_Np == 1)
 	__mem[0] = __x[0];
+      else if (__builtin_is_constant_evaluated())
+	{
+	  for (size_t __i = 0; __i < _Np; ++__i)
+	    __mem[__i] = __x[__i];
+	}
       else if constexpr (_Np == 2)
 	{
 	  short __bool2 = (__x._M_to_bits() * 0x81) & 0x0101;
@@ -1424,12 +1429,12 @@ template <typename _Abi, typename>
 
     // _M_make_simd(_SimdWrapper/__intrinsic_type_t) {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static simd<_Tp, _Abi>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr simd<_Tp, _Abi>
       _M_make_simd(_SimdWrapper<_Tp, _Np> __x)
       { return {__private_init, __x}; }
 
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static simd<_Tp, _Abi>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr simd<_Tp, _Abi>
       _M_make_simd(__intrinsic_type_t<_Tp, _Np> __x)
       { return {__private_init, __vector_bitcast<_Tp>(__x)}; }
 
@@ -1455,7 +1460,7 @@ template <typename _Abi, typename>
 
     // _S_load {{{2
     template <typename _Tp, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static _SimdMember<_Tp>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
       _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	constexpr size_t _Np = _S_size<_Tp>;
@@ -1464,7 +1469,12 @@ template <typename _Abi, typename>
 	    : (is_floating_point_v<_Up> && __have_avx) || __have_avx2 ? 32
 								      : 16;
 	constexpr size_t __bytes_to_load = sizeof(_Up) * _Np;
-	if constexpr (sizeof(_Up) > 8)
+	if (__builtin_is_constant_evaluated())
+	  return __generate_vector<_Tp, _S_full_size<_Tp>>(
+		   [&](auto __i) constexpr {
+		     return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0);
+		   });
+	else if constexpr (sizeof(_Up) > 8)
 	  return __generate_vector<_Tp, _SimdMember<_Tp>::_S_full_size>(
 		   [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		     return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0);
@@ -1511,7 +1521,7 @@ template <typename _Abi, typename>
 
     // _S_masked_load {{{2
     template <typename _Tp, size_t _Np, typename _Up>
-      static inline _SimdWrapper<_Tp, _Np>
+      static constexpr inline _SimdWrapper<_Tp, _Np>
       _S_masked_load(_SimdWrapper<_Tp, _Np> __merge, _MaskMember<_Tp> __k,
 		     const _Up* __mem) noexcept
       {
@@ -1524,14 +1534,19 @@ template <typename _Abi, typename>
 
     // _S_store {{{2
     template <typename _Tp, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_store(_SimdMember<_Tp> __v, _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	// TODO: converting int -> "smaller int" can be optimized with AVX512
 	constexpr size_t _Np = _S_size<_Tp>;
 	constexpr size_t __max_store_size
 	  = _SuperImpl::template _S_max_store_size<_Up>;
-	if constexpr (sizeof(_Up) > 8)
+	if (__builtin_is_constant_evaluated())
+	  {
+	    for (size_t __i = 0; __i < _Np; ++__i)
+	      __mem[__i] = __v[__i];
+	  }
+	else if constexpr (sizeof(_Up) > 8)
 	  __execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __mem[__i] = __v[__i];
 	  });
@@ -1562,7 +1577,7 @@ template <typename _Abi, typename>
 
     // _S_masked_store_nocvt {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem, _MaskMember<_Tp> __k)
       {
 	_BitOps::_S_bit_iteration(
@@ -1575,7 +1590,7 @@ template <typename _Abi, typename>
     // _S_masked_store {{{2
     template <typename _TW, typename _TVT = _VectorTraits<_TW>,
 	      typename _Tp = typename _TVT::value_type, typename _Up>
-      static inline void
+      static constexpr inline void
       _S_masked_store(const _TW __v, _Up* __mem, const _MaskMember<_Tp> __k) noexcept
       {
 	constexpr size_t _TV_size = _S_size<_Tp>;
@@ -1803,7 +1818,7 @@ template <typename _Abi, typename>
     // reductions {{{2
     template <size_t _Np, size_t... _Is, size_t... _Zeros, typename _Tp,
 	      typename _BinaryOperation>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
       _S_reduce_partial(index_sequence<_Is...>, index_sequence<_Zeros...>,
 			simd<_Tp, _Abi> __x, _BinaryOperation&& __binary_op)
       {
@@ -1833,6 +1848,13 @@ template <typename _Abi, typename>
 	else if constexpr (_Np == 2)
 	  return __binary_op(simd<_Tp, simd_abi::scalar>(__x[0]),
 			     simd<_Tp, simd_abi::scalar>(__x[1]))[0];
+	else if (__builtin_is_constant_evaluated())
+	  {
+	    simd<_Tp, simd_abi::scalar> __acc = __x[0];
+	    for (size_t __i = 1; __i < _Np; ++__i)
+	      __acc = __binary_op(__acc, simd<_Tp, simd_abi::scalar>(__x[__i]));
+	    return __acc[0];
+	  }
 	else if constexpr (_Abi::template _S_is_partial<_Tp>) //{{{
 	  {
 	    [[maybe_unused]] constexpr auto __full_size
@@ -2445,24 +2467,24 @@ template <typename _Abi, typename>
 
     // _S_increment & _S_decrement{{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_increment(_SimdWrapper<_Tp, _Np>& __x)
       { __x = __x._M_data + 1; }
 
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_decrement(_SimdWrapper<_Tp, _Np>& __x)
       { __x = __x._M_data - 1; }
 
     // smart_reference access {{{2
     template <typename _Tp, size_t _Np, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC constexpr static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_set(_SimdWrapper<_Tp, _Np>& __v, int __i, _Up&& __x) noexcept
       { __v._M_set(__i, static_cast<_Up&&>(__x)); }
 
     // _S_masked_assign{{{2
     template <typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(_SimdWrapper<_K, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs,
 		       __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs)
       {
@@ -2475,7 +2497,7 @@ template <typename _Abi, typename>
       }
 
     template <typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(_SimdWrapper<_K, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs,
 		       __type_identity_t<_Tp> __rhs)
       {
@@ -2503,7 +2525,7 @@ template <typename _Abi, typename>
 
     // _S_masked_cassign {{{2
     template <typename _Op, typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_cassign(const _SimdWrapper<_K, _Np> __k,
 			_SimdWrapper<_Tp, _Np>& __lhs,
 			const __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs,
@@ -2519,7 +2541,7 @@ template <typename _Abi, typename>
       }
 
     template <typename _Op, typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_cassign(const _SimdWrapper<_K, _Np> __k,
 			_SimdWrapper<_Tp, _Np>& __lhs,
 			const __type_identity_t<_Tp> __rhs, _Op __op)
@@ -2528,7 +2550,7 @@ template <typename _Abi, typename>
     // _S_masked_unary {{{2
     template <template <typename> class _Op, typename _Tp, typename _K,
 	      size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
       _S_masked_unary(const _SimdWrapper<_K, _Np> __k,
 		      const _SimdWrapper<_Tp, _Np> __v)
       {
@@ -2704,18 +2726,18 @@ template <typename _Abi, typename>
       _S_load(const bool* __mem)
       {
 	using _I = __int_for_sizeof_t<_Tp>;
-	if constexpr (sizeof(_Tp) == sizeof(bool))
-	  {
-	    const auto __bools
-	      = _CommonImpl::template _S_load<_I, _S_size<_Tp>>(__mem);
-	    // bool is {0, 1}, everything else is UB
-	    return __bools > 0;
-	  }
-	else
-	  return __generate_vector<_I, _S_size<_Tp>>(
-		   [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
-		     return __mem[__i] ? ~_I() : _I();
-		   });
+	if (not __builtin_is_constant_evaluated())
+	  if constexpr (sizeof(_Tp) == sizeof(bool))
+	    {
+	      const auto __bools
+		= _CommonImpl::template _S_load<_I, _S_size<_Tp>>(__mem);
+	      // bool is {0, 1}, everything else is UB
+	      return __bools > 0;
+	    }
+	return __generate_vector<_I, _S_size<_Tp>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __mem[__i] ? ~_I() : _I();
+		 });
       }
 
     // }}}
@@ -2797,7 +2819,7 @@ template <typename _Abi, typename>
 
     // _S_store {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_store(_SimdWrapper<_Tp, _Np> __v, bool* __mem) noexcept
       {
 	__execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
diff --git a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
index 9a2c699eae0..9df82802ae7 100644
--- a/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
+++ b/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
@@ -166,25 +166,25 @@ template <typename _Tp, typename _Abi, size_t _Offset>
     static constexpr _MaskImpl _S_mask_impl = {};
 
     template <size_t _Np, bool _Sanitized>
-      _GLIBCXX_SIMD_INTRINSIC static auto
+      _GLIBCXX_SIMD_INTRINSIC static constexpr auto
       _S_submask(_BitMask<_Np, _Sanitized> __bits)
       { return __bits.template _M_extract<_Offset, _S_size()>(); }
 
     template <size_t _Np, bool _Sanitized>
-      _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
       _S_make_mask(_BitMask<_Np, _Sanitized> __bits)
       {
 	return _MaskImpl::template _S_convert<_Tp>(
 	  __bits.template _M_extract<_Offset, _S_size()>()._M_sanitized());
       }
 
-    _GLIBCXX_SIMD_INTRINSIC static _ULLong
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _ULLong
     _S_mask_to_shifted_ullong(_MaskMember __k)
     { return _MaskImpl::_S_to_bits(__k).to_ullong() << _Offset; }
   };
 
 template <size_t _Offset, typename _Tp, typename _Abi, typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC
+  _GLIBCXX_SIMD_INTRINSIC constexpr
   __tuple_element_meta<_Tp, _Abi, _Offset>
   __make_meta(const _SimdTuple<_Tp, _Abi, _As...>&)
   { return {}; }
@@ -535,7 +535,7 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       }
 
     template <typename _R = _Tp, typename _Fp, typename... _More>
-      _GLIBCXX_SIMD_INTRINSIC auto
+      _GLIBCXX_SIMD_INTRINSIC constexpr auto
       _M_apply_r(_Fp&& __fun, const _More&... __more) const
       {
 	auto&& __first = __fun(__tuple_element_meta<_Tp, _Abi0, 0>(), first,
@@ -573,50 +573,43 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	  return second[integral_constant<_Up, _I - simd_size_v<_Tp, _Abi0>>()];
       }
 
-    _GLIBCXX_SIMD_INTRINSIC _Tp
+    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
     operator[](size_t __i) const noexcept
     {
       if constexpr (_S_tuple_size == 1)
 	return _M_subscript_read(__i);
-      else
-	{
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
-	  return reinterpret_cast<const __may_alias<_Tp>*>(this)[__i];
-#else
-	  if constexpr (__is_scalar_abi<_Abi0>())
-	    {
-	      const _Tp* ptr = &first;
-	      return ptr[__i];
-	    }
-	  else
-	    return __i < simd_size_v<_Tp, _Abi0>
-		     ? _M_subscript_read(__i)
-		     : second[__i - simd_size_v<_Tp, _Abi0>];
+      else if (not __builtin_is_constant_evaluated())
+	return reinterpret_cast<const __may_alias<_Tp>*>(this)[__i];
 #endif
+      else if constexpr (__is_scalar_abi<_Abi0>())
+	{
+	  const _Tp* ptr = &first;
+	  return ptr[__i];
 	}
+      else
+	return __i < simd_size_v<_Tp, _Abi0> ? _M_subscript_read(__i)
+					     : second[__i - simd_size_v<_Tp, _Abi0>];
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
     _M_set(size_t __i, _Tp __val) noexcept
     {
       if constexpr (_S_tuple_size == 1)
 	return _M_subscript_write(__i, __val);
-      else
-	{
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
-	  reinterpret_cast<__may_alias<_Tp>*>(this)[__i] = __val;
-#else
-	  if (__i < simd_size_v<_Tp, _Abi0>)
-	    _M_subscript_write(__i, __val);
-	  else
-	    second._M_set(__i - simd_size_v<_Tp, _Abi0>, __val);
+      else if (not __builtin_is_constant_evaluated())
+	reinterpret_cast<__may_alias<_Tp>*>(this)[__i] = __val;
 #endif
-	}
+      else if (__i < simd_size_v<_Tp, _Abi0>)
+	_M_subscript_write(__i, __val);
+      else
+	second._M_set(__i - simd_size_v<_Tp, _Abi0>, __val);
     }
 
   private:
     // _M_subscript_read/_write {{{
-    _GLIBCXX_SIMD_INTRINSIC _Tp
+    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
     _M_subscript_read([[maybe_unused]] size_t __i) const noexcept
     {
       if constexpr (__is_vectorizable_v<_FirstType>)
@@ -625,7 +618,7 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	return first[__i];
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
     _M_subscript_write([[maybe_unused]] size_t __i, _Tp __y) noexcept
     {
       if constexpr (__is_vectorizable_v<_FirstType>)
@@ -639,22 +632,22 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 
 // __make_simd_tuple {{{1
 template <typename _Tp, typename _A0>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0>
   __make_simd_tuple(simd<_Tp, _A0> __x0)
   { return {__data(__x0)}; }
 
 template <typename _Tp, typename _A0, typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0, _As...>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0, _As...>
   __make_simd_tuple(const simd<_Tp, _A0>& __x0, const simd<_Tp, _As>&... __xs)
   { return {__data(__x0), __make_simd_tuple(__xs...)}; }
 
 template <typename _Tp, typename _A0>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0>
   __make_simd_tuple(const typename _SimdTraits<_Tp, _A0>::_SimdMember& __arg0)
   { return {__arg0}; }
 
 template <typename _Tp, typename _A0, typename _A1, typename... _Abis>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0, _A1, _Abis...>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0, _A1, _Abis...>
   __make_simd_tuple(
     const typename _SimdTraits<_Tp, _A0>::_SimdMember& __arg0,
     const typename _SimdTraits<_Tp, _A1>::_SimdMember& __arg1,
@@ -797,19 +790,19 @@ template <typename _Tp, typename _A0, size_t _NOut, size_t _Np,
 
 // __optimize_simd_tuple {{{1
 template <typename _Tp>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp>
   __optimize_simd_tuple(const _SimdTuple<_Tp>)
   { return {}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC const _SimdTuple<_Tp, _Ap>&
+  _GLIBCXX_SIMD_INTRINSIC constexpr const _SimdTuple<_Tp, _Ap>&
   __optimize_simd_tuple(const _SimdTuple<_Tp, _Ap>& __x)
   { return __x; }
 
 template <typename _Tp, typename _A0, typename _A1, typename... _Abis,
 	  typename _R = __fixed_size_storage_t<
 	    _Tp, _SimdTuple<_Tp, _A0, _A1, _Abis...>::_S_size()>>
-  _GLIBCXX_SIMD_INTRINSIC _R
+  _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __optimize_simd_tuple(const _SimdTuple<_Tp, _A0, _A1, _Abis...>& __x)
   {
     using _Tup = _SimdTuple<_Tp, _A0, _A1, _Abis...>;
@@ -916,7 +909,7 @@ template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 // }}}1
 // __extract_part(_SimdTuple) {{{
 template <int _Index, int _Total, int _Combine, typename _Tp, typename _A0, typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC auto // __vector_type_t or _SimdTuple
+  _GLIBCXX_SIMD_INTRINSIC constexpr auto // __vector_type_t or _SimdTuple
   __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x)
   {
     // worst cases:
@@ -1017,11 +1010,11 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
     _Tp _M_data;
     using _TT = __remove_cvref_t<_Tp>;
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator _TT()
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator _TT&()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1029,7 +1022,7 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
       return _M_data;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator _TT*()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1041,17 +1034,17 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
     __autocvt_to_simd(_Tp dd) : _M_data(dd) {}
 
     template <typename _Abi>
-      _GLIBCXX_SIMD_INTRINSIC
+      _GLIBCXX_SIMD_INTRINSIC constexpr
       operator simd<typename _TT::value_type, _Abi>()
       { return {__private_init, _M_data}; }
 
     template <typename _Abi>
-      _GLIBCXX_SIMD_INTRINSIC
+      _GLIBCXX_SIMD_INTRINSIC constexpr
       operator simd<typename _TT::value_type, _Abi>&()
       { return *reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(&_M_data); }
 
     template <typename _Abi>
-      _GLIBCXX_SIMD_INTRINSIC
+      _GLIBCXX_SIMD_INTRINSIC constexpr
       operator simd<typename _TT::value_type, _Abi>*()
       { return reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(&_M_data); }
   };
@@ -1073,11 +1066,11 @@ template <typename _Tp>
     ~__autocvt_to_simd()
     { _M_data = __data(_M_fd).first; }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator fixed_size_simd<_TT, 1>()
     { return _M_fd; }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator fixed_size_simd<_TT, 1> &()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1085,7 +1078,7 @@ template <typename _Tp>
       return _M_fd;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator fixed_size_simd<_TT, 1> *()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1162,15 +1155,16 @@ template <int _Np>
 	{
 	  // The following ensures, function arguments are passed via the stack.
 	  // This is important for ABI compatibility across TU boundaries
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
 	  _SimdBase(const _SimdBase&) {}
+
 	  _SimdBase() = default;
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr explicit
 	  operator const _SimdMember &() const
 	  { return static_cast<const simd<_Tp, _Fixed>*>(this)->_M_data; }
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr explicit
 	  operator array<_Tp, _Np>() const
 	  {
 	    array<_Tp, _Np> __r;
@@ -1191,13 +1185,13 @@ template <int _Np>
 	// _SimdCastType {{{
 	struct _SimdCastType
 	{
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
 	  _SimdCastType(const array<_Tp, _Np>&);
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
 	  _SimdCastType(const _SimdMember& dd) : _M_data(dd) {}
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr explicit
 	  operator const _SimdMember &() const { return _M_data; }
 
 	private:
@@ -1282,7 +1276,7 @@ template <int _Np, typename>
 
     // _S_load {{{2
     template <typename _Tp, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static _SimdMember<_Tp>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
       _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	return _SimdMember<_Tp>::_S_generate(
@@ -1301,10 +1295,10 @@ template <int _Np, typename>
 	__for_each(__merge, [&](auto __meta, auto& __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__meta._S_submask(__bits).any())
 #pragma GCC diagnostic push
-	  // __mem + __mem._S_offset could be UB ([expr.add]/4.3, but it punts
-	  // the responsibility for avoiding UB to the caller of the masked load
-	  // via the mask. Consequently, the compiler may assume this branch is
-	  // unreachable, if the pointer arithmetic is UB.
+	    // Dereferencing __mem + __meta._S_offset could be UB ([expr.add]/4.3).
+	    // It is the responsibility of the caller of the masked load (via the mask's value) to
+	    // avoid UB. Consequently, the compiler may assume this branch is unreachable, if the
+	    // pointer arithmetic is UB.
 #pragma GCC diagnostic ignored "-Warray-bounds"
 	    __native
 	      = __meta._S_masked_load(__native, __meta._S_make_mask(__bits),
@@ -1316,7 +1310,7 @@ template <int _Np, typename>
 
     // _S_store {{{2
     template <typename _Tp, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_store(const _SimdMember<_Tp>& __v, _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	__for_each(__v, [&](auto __meta, auto __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
@@ -1346,7 +1340,7 @@ template <int _Np, typename>
 
     // negation {{{2
     template <typename _Tp, typename... _As>
-      static inline _MaskMember
+      static constexpr inline _MaskMember
       _S_negate(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
 	_MaskMember __bits = 0;
@@ -1699,7 +1693,7 @@ template <int _Np, typename>
     // compares {{{2
 #define _GLIBCXX_SIMD_CMP_OPERATIONS(__cmp)                                    \
     template <typename _Tp, typename... _As>                                   \
-      _GLIBCXX_SIMD_INTRINSIC constexpr static _MaskMember                     \
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember                     \
       __cmp(const _SimdTuple<_Tp, _As...>& __x,                                \
 	    const _SimdTuple<_Tp, _As...>& __y)                                \
       {                                                                        \
@@ -1723,13 +1717,13 @@ template <int _Np, typename>
 
     // smart_reference access {{{2
     template <typename _Tp, typename... _As, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_set(_SimdTuple<_Tp, _As...>& __v, int __i, _Up&& __x) noexcept
       { __v._M_set(__i, static_cast<_Up&&>(__x)); }
 
     // _S_masked_assign {{{2
     template <typename _Tp, typename... _As>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
 		       const __type_identity_t<_SimdTuple<_Tp, _As...>>& __rhs)
       {
@@ -1745,7 +1739,7 @@ template <int _Np, typename>
     // Optimization for the case where the RHS is a scalar. No need to broadcast
     // the scalar to a simd first.
     template <typename _Tp, typename... _As>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
 		       const __type_identity_t<_Tp> __rhs)
       {
@@ -1758,7 +1752,7 @@ template <int _Np, typename>
 
     // _S_masked_cassign {{{2
     template <typename _Op, typename _Tp, typename... _As>
-      static inline void
+      static constexpr inline void
       _S_masked_cassign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
 			const _SimdTuple<_Tp, _As...>& __rhs, _Op __op)
       {
@@ -1774,7 +1768,7 @@ template <int _Np, typename>
     // Optimization for the case where the RHS is a scalar. No need to broadcast
     // the scalar to a simd first.
     template <typename _Op, typename _Tp, typename... _As>
-      static inline void
+      static constexpr inline void
       _S_masked_cassign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
 			const _Tp& __rhs, _Op __op)
       {
@@ -1787,7 +1781,7 @@ template <int _Np, typename>
 
     // _S_masked_unary {{{2
     template <template <typename> class _Op, typename _Tp, typename... _As>
-      static inline _SimdTuple<_Tp, _As...>
+      static constexpr inline _SimdTuple<_Tp, _As...>
       _S_masked_unary(const _MaskMember __bits, const _SimdTuple<_Tp, _As...>& __v)
       {
 	return __v._M_apply_wrapped([&__bits](auto __meta,
@@ -1834,6 +1828,13 @@ template <int _Np, typename>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
       _S_load(const bool* __mem)
       {
+	if (__builtin_is_constant_evaluated())
+	  {
+	    _MaskMember __r{};
+	    for (size_t __i = 0; __i < _Np; ++__i)
+	      __r.set(__i, __mem[__i]);
+	    return __r;
+	  }
 	using _Ip = __int_for_sizeof_t<bool>;
 	// the following load uses element_aligned and relies on __mem already
 	// carrying alignment information from when this load function was
@@ -1869,12 +1870,12 @@ template <int _Np, typename>
     // }}}
     // _S_from_bitmask {{{2
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
       _S_from_bitmask(_MaskMember __bits, _TypeTag<_Tp>) noexcept
       { return __bits; }
 
     // _S_load {{{2
-    static inline _MaskMember
+    static constexpr inline _MaskMember
     _S_load(const bool* __mem) noexcept
     {
       // TODO: _UChar is not necessarily the best type to use here. For smaller
@@ -1890,7 +1891,7 @@ template <int _Np, typename>
     }
 
     // _S_masked_load {{{2
-    static inline _MaskMember
+    static constexpr inline _MaskMember
     _S_masked_load(_MaskMember __merge, _MaskMember __mask, const bool* __mem) noexcept
     {
       _BitOps::_S_bit_iteration(__mask.to_ullong(),
@@ -1901,7 +1902,7 @@ template <int _Np, typename>
     }
 
     // _S_store {{{2
-    static inline void
+    static constexpr inline void
     _S_store(const _MaskMember __bitmask, bool* __mem) noexcept
     {
       if constexpr (_Np == 1)
@@ -1911,7 +1912,7 @@ template <int _Np, typename>
     }
 
     // _S_masked_store {{{2
-    static inline void
+    static constexpr inline void
     _S_masked_store(const _MaskMember __v, bool* __mem, const _MaskMember __k) noexcept
     {
       _BitOps::_S_bit_iteration(
@@ -1919,11 +1920,11 @@ template <int _Np, typename>
     }
 
     // logical and bitwise operators {{{2
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_logical_and(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x & __y; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_logical_or(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x | __y; }
 
@@ -1931,30 +1932,30 @@ template <int _Np, typename>
     _S_bit_not(const _MaskMember& __x) noexcept
     { return ~__x; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_bit_and(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x & __y; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_bit_or(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x | __y; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_bit_xor(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x ^ __y; }
 
     // smart_reference access {{{2
-    _GLIBCXX_SIMD_INTRINSIC static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_set(_MaskMember& __k, int __i, bool __x) noexcept
     { __k.set(__i, __x); }
 
     // _S_masked_assign {{{2
-    _GLIBCXX_SIMD_INTRINSIC static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs, const _MaskMember __rhs)
     { __lhs = (__lhs & ~__k) | (__rhs & __k); }
 
     // Optimization for the case where the RHS is a scalar.
-    _GLIBCXX_SIMD_INTRINSIC static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs, const bool __rhs)
     {
       if (__rhs)
@@ -1966,28 +1967,28 @@ template <int _Np, typename>
     // }}}2
     // _S_all_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
       _S_all_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).all(); }
 
     // }}}
     // _S_any_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
       _S_any_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).any(); }
 
     // }}}
     // _S_none_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
       _S_none_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).none(); }
 
     // }}}
     // _S_some_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
       _S_some_of([[maybe_unused]] simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (_Np == 1)
@@ -1999,21 +2000,21 @@ template <int _Np, typename>
     // }}}
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int
+      _GLIBCXX_SIMD_INTRINSIC static constexpr int
       _S_popcount(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).count(); }
 
     // }}}
     // _S_find_first_set {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int
+      _GLIBCXX_SIMD_INTRINSIC static constexpr int
       _S_find_first_set(simd_mask<_Tp, _Abi> __k)
       { return std::__countr_zero(__data(__k).to_ullong()); }
 
     // }}}
     // _S_find_last_set {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int
+      _GLIBCXX_SIMD_INTRINSIC static constexpr int
       _S_find_last_set(simd_mask<_Tp, _Abi> __k)
       { return std::__bit_width(__data(__k).to_ullong()) - 1; }
 
diff --git a/libstdc++-v3/include/experimental/bits/simd_scalar.h b/libstdc++-v3/include/experimental/bits/simd_scalar.h
index aeccedfbc8b..bd1119451c4 100644
--- a/libstdc++-v3/include/experimental/bits/simd_scalar.h
+++ b/libstdc++-v3/include/experimental/bits/simd_scalar.h
@@ -152,13 +152,13 @@ struct _SimdImplScalar
 
   // _S_load {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
     _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
     { return static_cast<_Tp>(__mem[0]); }
 
   // _S_masked_load {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
     _S_masked_load(_Tp __merge, bool __k, const _Up* __mem) noexcept
     {
       if (__k)
@@ -168,13 +168,13 @@ struct _SimdImplScalar
 
   // _S_store {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_store(_Tp __v, _Up* __mem, _TypeTag<_Tp>) noexcept
     { __mem[0] = static_cast<_Up>(__v); }
 
   // _S_masked_store {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_masked_store(const _Tp __v, _Up* __mem, const bool __k) noexcept
     { if (__k) __mem[0] = __v; }
 
@@ -572,101 +572,101 @@ struct _SimdImplScalar
     { return std::remquo(__x, __y, &__z->first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static _ST<int>
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _ST<int>
     _S_fpclassify(_Tp __x)
     { return {std::fpclassify(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isfinite(_Tp __x)
     { return std::isfinite(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isinf(_Tp __x)
     { return std::isinf(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isnan(_Tp __x)
     { return std::isnan(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isnormal(_Tp __x)
     { return std::isnormal(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_signbit(_Tp __x)
     { return std::signbit(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isgreater(_Tp __x, _Tp __y)
     { return std::isgreater(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isgreaterequal(_Tp __x, _Tp __y)
     { return std::isgreaterequal(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isless(_Tp __x, _Tp __y)
     { return std::isless(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_islessequal(_Tp __x, _Tp __y)
     { return std::islessequal(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_islessgreater(_Tp __x, _Tp __y)
     { return std::islessgreater(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_isunordered(_Tp __x, _Tp __y)
     { return std::isunordered(__x, __y); }
 
   // _S_increment & _S_decrement{{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_increment(_Tp& __x)
     { ++__x; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_decrement(_Tp& __x)
     { --__x; }
 
 
   // compares {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_equal_to(_Tp __x, _Tp __y)
     { return __x == __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_not_equal_to(_Tp __x, _Tp __y)
     { return __x != __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_less(_Tp __x, _Tp __y)
     { return __x < __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_less_equal(_Tp __x, _Tp __y)
     { return __x <= __y; }
 
   // smart_reference access {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_set(_Tp& __v, [[maybe_unused]] int __i, _Up&& __x) noexcept
     {
       _GLIBCXX_DEBUG_ASSERT(__i == 0);
@@ -675,19 +675,19 @@ struct _SimdImplScalar
 
   // _S_masked_assign {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_masked_assign(bool __k, _Tp& __lhs, _Tp __rhs)
     { if (__k) __lhs = __rhs; }
 
   // _S_masked_cassign {{{2
   template <typename _Op, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_masked_cassign(const bool __k, _Tp& __lhs, const _Tp __rhs, _Op __op)
     { if (__k) __lhs = __op(_SimdImplScalar{}, __lhs, __rhs); }
 
   // _S_masked_unary {{{2
   template <template <typename> class _Op, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static _Tp
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
     _S_masked_unary(const bool __k, const _Tp __v)
     { return static_cast<_Tp>(__k ? _Op<_Tp>{}(__v) : __v); }
 
@@ -737,12 +737,12 @@ struct _MaskImplScalar
   // }}}
   // _S_from_bitmask {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_from_bitmask(_SanitizedBitMask<1> __bits, _TypeTag<_Tp>) noexcept
     { return __bits[0]; }
 
   // _S_masked_load {{{2
-  _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
   _S_masked_load(bool __merge, bool __mask, const bool* __mem) noexcept
   {
     if (__mask)
@@ -751,12 +751,12 @@ struct _MaskImplScalar
   }
 
   // _S_store {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
   _S_store(bool __v, bool* __mem) noexcept
   { __mem[0] = __v; }
 
   // _S_masked_store {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
   _S_masked_store(const bool __v, bool* __mem, const bool __k) noexcept
   {
     if (__k)
@@ -789,7 +789,7 @@ struct _MaskImplScalar
   { return __x != __y; }
 
   // smart_reference access {{{2
-  _GLIBCXX_SIMD_INTRINSIC constexpr static void
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
   _S_set(bool& __k, [[maybe_unused]] int __i, bool __x) noexcept
   {
     _GLIBCXX_DEBUG_ASSERT(__i == 0);
@@ -797,7 +797,7 @@ struct _MaskImplScalar
   }
 
   // _S_masked_assign {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
   _S_masked_assign(bool __k, bool& __lhs, bool __rhs)
   {
     if (__k)
@@ -807,49 +807,49 @@ struct _MaskImplScalar
   // }}}2
   // _S_all_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_all_of(simd_mask<_Tp, _Abi> __k)
     { return __k._M_data; }
 
   // }}}
   // _S_any_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_any_of(simd_mask<_Tp, _Abi> __k)
     { return __k._M_data; }
 
   // }}}
   // _S_none_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_none_of(simd_mask<_Tp, _Abi> __k)
     { return !__k._M_data; }
 
   // }}}
   // _S_some_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_some_of(simd_mask<_Tp, _Abi>)
     { return false; }
 
   // }}}
   // _S_popcount {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static int
+    _GLIBCXX_SIMD_INTRINSIC static constexpr int
     _S_popcount(simd_mask<_Tp, _Abi> __k)
     { return __k._M_data; }
 
   // }}}
   // _S_find_first_set {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static int
+    _GLIBCXX_SIMD_INTRINSIC static constexpr int
     _S_find_first_set(simd_mask<_Tp, _Abi>)
     { return 0; }
 
   // }}}
   // _S_find_last_set {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static int
+    _GLIBCXX_SIMD_INTRINSIC static constexpr int
     _S_find_last_set(simd_mask<_Tp, _Abi>)
     { return 0; }
 
diff --git a/libstdc++-v3/include/experimental/bits/simd_x86.h b/libstdc++-v3/include/experimental/bits/simd_x86.h
index 7fd1d958c08..55746289396 100644
--- a/libstdc++-v3/include/experimental/bits/simd_x86.h
+++ b/libstdc++-v3/include/experimental/bits/simd_x86.h
@@ -510,12 +510,14 @@ struct _CommonImplX86 : _CommonImplBuiltin
   using _CommonImplBuiltin::_S_store;
 
   template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_store(_SimdWrapper<_Tp, _Np> __x, void* __addr)
     {
       constexpr size_t _Bytes = _Np * sizeof(_Tp);
 
-      if constexpr ((_Bytes & (_Bytes - 1)) != 0 && __have_avx512bw_vl)
+      if (__builtin_is_constant_evaluated())
+	_CommonImplBuiltin::_S_store(__x, __addr);
+      else if constexpr ((_Bytes & (_Bytes - 1)) != 0 && __have_avx512bw_vl)
 	{
 	  const auto __v = __to_intrin(__x);
 
@@ -581,7 +583,9 @@ struct _CommonImplX86 : _CommonImplBuiltin
     _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_store_bool_array(const _BitMask<_Np, _Sanitized> __x, bool* __mem)
     {
-      if constexpr (__have_avx512bw_vl) // don't care for BW w/o VL
+      if (__builtin_is_constant_evaluated())
+	_CommonImplBuiltin::_S_store_bool_array(__x, __mem);
+      else if constexpr (__have_avx512bw_vl) // don't care for BW w/o VL
 	_S_store<_Np>(1 & __vector_bitcast<_UChar, _Np>(
 			    [=]() constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 			      if constexpr (_Np <= 16)
@@ -2319,14 +2323,14 @@ template <typename _Abi, typename>
 	  } // }}}
 	else if (__builtin_is_constant_evaluated())
 	  return _Base::_S_equal_to(__x, __y);
-	else if constexpr (sizeof(__x) == 8) // {{{
+	else if constexpr (sizeof(__x) == 8)
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				== __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
-	  } // }}}
+	  }
 	else
 	  return _Base::_S_equal_to(__x, __y);
       }
@@ -2397,7 +2401,7 @@ template <typename _Abi, typename>
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				!= __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
 	  }
@@ -2505,7 +2509,7 @@ template <typename _Abi, typename>
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				< __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
 	  }
@@ -2613,7 +2617,7 @@ template <typename _Abi, typename>
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				<= __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
 	  }
@@ -4409,7 +4413,19 @@ template <typename _Abi, typename>
       _S_load(const bool* __mem)
       {
 	static_assert(is_same_v<_Tp, __int_for_sizeof_t<_Tp>>);
-	if constexpr (__have_avx512bw)
+	if (__builtin_is_constant_evaluated())
+	  {
+	    if constexpr (__is_avx512_abi<_Abi>())
+	      {
+		_MaskMember<_Tp> __r{};
+		for (size_t __i = 0; __i < _S_size<_Tp>; ++__i)
+		  __r._M_data |= _ULLong(__mem[__i]) << __i;
+		return __r;
+	      }
+	    else
+	      return _Base::template _S_load<_Tp>(__mem);
+	  }
+	else if constexpr (__have_avx512bw)
 	  {
 	    const auto __to_vec_or_bits
 	      = [](auto __bits) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> decltype(auto) {
@@ -4677,10 +4693,12 @@ template <typename _Abi, typename>
 
     // _S_store {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_store(_SimdWrapper<_Tp, _Np> __v, bool* __mem) noexcept
       {
-	if constexpr (__is_avx512_abi<_Abi>())
+	if (__builtin_is_constant_evaluated())
+	  _Base::_S_store(__v, __mem);
+	else if constexpr (__is_avx512_abi<_Abi>())
 	  {
 	    if constexpr (__have_avx512bw_vl)
 	      _CommonImplX86::_S_store<_Np>(
@@ -4762,7 +4780,7 @@ template <typename _Abi, typename>
 	    if constexpr (_Np <= 4 && sizeof(_Tp) == 8)
 	      {
 		auto __k = __intrin_bitcast<__m256i>(__to_intrin(__v));
-		int __bool4;
+		int __bool4{};
 		if constexpr (__have_avx2)
 		  __bool4 = _mm256_movemask_epi8(__k);
 		else
@@ -4846,7 +4864,9 @@ template <typename _Abi, typename>
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data & __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kand_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kand_mask16(__x._M_data, __y._M_data);
@@ -4867,7 +4887,9 @@ template <typename _Abi, typename>
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data | __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kor_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kor_mask16(__x._M_data, __y._M_data);
@@ -4888,7 +4910,9 @@ template <typename _Abi, typename>
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data ^ _Abi::template __implicit_mask_n<_Np>();
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kandn_mask8(__x._M_data,
 				  _Abi::template __implicit_mask_n<_Np>());
 	    else if constexpr (_Np <= 16)
@@ -4913,7 +4937,9 @@ template <typename _Abi, typename>
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data & __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kand_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kand_mask16(__x._M_data, __y._M_data);
@@ -4934,7 +4960,9 @@ template <typename _Abi, typename>
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data | __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kor_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kor_mask16(__x._M_data, __y._M_data);
@@ -4955,7 +4983,9 @@ template <typename _Abi, typename>
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data ^ __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kxor_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kxor_mask16(__x._M_data, __y._M_data);
diff --git a/libstdc++-v3/testsuite/experimental/simd/pr109261_constexpr_simd.cc b/libstdc++-v3/testsuite/experimental/simd/pr109261_constexpr_simd.cc
new file mode 100644
index 00000000000..d1bfea7a794
--- /dev/null
+++ b/libstdc++-v3/testsuite/experimental/simd/pr109261_constexpr_simd.cc
@@ -0,0 +1,92 @@
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+// { dg-require-cmath "" }
+
+#include <experimental/simd>
+
+namespace stdx = std::experimental;
+
+template <typename T, typename V>
+  void
+  test01()
+  {
+    constexpr T data[V::size()] = {};
+    constexpr auto a = V(data, stdx::element_aligned);
+
+    constexpr auto b = []() constexpr {
+      V x = T(1);
+      where(x > T(), x) = T();
+      where(x < T(), x) += T();
+      where(x >= T(), x) -= T();
+      where(x <= T(), x) *= T();
+      where(x == T(), x) /= T(1);
+      where(x != T(), x) += T(1);
+      return x;
+    }();
+
+    constexpr T c = V()[0];
+
+    constexpr auto d = !V() && !!V() || !V() & !V() | !V() ^ !V();
+
+    constexpr auto e = []() constexpr {
+      T data[V::size()] = {};
+      V(T(1)).copy_to(data, stdx::element_aligned);
+      V x = T();
+      x[0] = T(1);
+      x.copy_from(data, stdx::element_aligned);
+      bool mask[V::size()] = {};
+      auto k = hmin(x + x - x * x) == x / x;
+      k.copy_to(mask, stdx::element_aligned);
+      mask[0] = false;
+      using M = typename V::mask_type;
+      return M(mask, stdx::element_aligned);
+    }();
+
+    static_assert(not e[0]);
+    static_assert(popcount(e) == V::size() - 1);
+
+    static_assert(all_of(V(T(1)) == []() constexpr {
+      float data[V::size()] = {};
+      V(T(1)).copy_to(data, stdx::element_aligned);
+      V x = T();
+      x.copy_from(data, stdx::element_aligned);
+      return x;
+    }()));
+
+    static_assert(hmin(V()) == T());
+    static_assert(hmax(V()) == T());
+    static_assert(reduce(V(1)) == T(V::size()));
+  }
+
+template <typename T>
+  void
+  iterate_abis()
+  {
+    test01<T, stdx::simd<T, stdx::simd_abi::scalar>>();
+    test01<T, stdx::simd<T>>();
+    test01<T, stdx::native_simd<T>>();
+    test01<T, stdx::fixed_size_simd<T, 3>>();
+    test01<T, stdx::fixed_size_simd<T, stdx::simd_abi::max_fixed_size<T> - 4>>();
+  }
+
+int main()
+{
+  iterate_abis<char>();
+  iterate_abis<wchar_t>();
+  iterate_abis<char16_t>();
+  iterate_abis<char32_t>();
+
+  iterate_abis<signed char>();
+  iterate_abis<unsigned char>();
+  iterate_abis<short>();
+  iterate_abis<unsigned short>();
+  iterate_abis<int>();
+  iterate_abis<unsigned int>();
+  iterate_abis<long>();
+  iterate_abis<unsigned long>();
+  iterate_abis<long long>();
+  iterate_abis<unsigned long long>();
+  iterate_abis<float>();
+  iterate_abis<double>();
+  iterate_abis<long double>();
+}

commit 2fb4dfb35a5eefca4df7814511aa7ba6840cc2a7
Author: Georg-Johann Lay <avr@gjlay.de>
Date:   Tue May 23 18:49:19 2023

    Improve cost computation for single-bit bit insertions.
    
    Some miscomputation of rtx_costs lead to sub-optimal code for
    single-bit bit insertions.  This patch implements TARGET_INSN_COST,
    which has a chance to see the whole insn during insn combination;
    in particular the SET_DEST of (set (zero_extract (...) ...)).
    
    gcc/
            * config/avr/avr.cc (avr_insn_cost): New static function.
            (TARGET_INSN_COST): Define to that function.

diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 4ed390e4cf9..406b2cbcef5 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -11515,6 +11515,52 @@ avr_rtx_costs (rtx x, machine_mode mode, int outer_code,
 }
 
 
+/* Implement `TARGET_INSN_COST'.  */
+/* For some insns, it is not enough to look at the cost of the SET_SRC.
+   In that case, have a look at the entire insn, e.g. during insn combine.  */
+
+static int
+avr_insn_cost (rtx_insn *insn, bool speed)
+{
+  const int unknown_cost = -1;
+  int cost = unknown_cost;
+
+  rtx set = single_set (insn);
+
+  if (set
+      && ZERO_EXTRACT == GET_CODE (SET_DEST (set)))
+    {
+      // Try find anything that would flip the extracted bit.
+      bool not_bit_p = false;
+
+      subrtx_iterator::array_type array;
+      FOR_EACH_SUBRTX (iter, array, SET_SRC (set), NONCONST)
+	{
+	  enum rtx_code code = GET_CODE (*iter);
+	  not_bit_p |= code == NOT || code == XOR || code == GE;
+	}
+
+      // Don't go too deep into the analysis.  In almost all cases,
+      // using BLD/BST is the best we can do for single-bit moves,
+      // even considering CSE.
+      cost = COSTS_N_INSNS (2 + not_bit_p);
+    }
+
+  if (cost != unknown_cost)
+    {
+      if (avr_log.rtx_costs)
+	avr_edump ("\n%? (%s) insn_cost=%d\n%r\n",
+		   speed ? "speed" : "size", cost, insn);
+      return cost;
+    }
+
+  // Resort to what rtlanal.cc::insn_cost() implements as a default
+  // when targetm.insn_cost() is not implemented.
+
+  return pattern_cost (PATTERN (insn), speed);
+}
+
+
 /* Implement `TARGET_ADDRESS_COST'.  */
 
 static int
@@ -14572,6 +14618,8 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #undef  TARGET_ASM_FINAL_POSTSCAN_INSN
 #define TARGET_ASM_FINAL_POSTSCAN_INSN avr_asm_final_postscan_insn
 
+#undef  TARGET_INSN_COST
+#define TARGET_INSN_COST avr_insn_cost
 #undef  TARGET_REGISTER_MOVE_COST
 #define TARGET_REGISTER_MOVE_COST avr_register_move_cost
 #undef  TARGET_MEMORY_MOVE_COST

commit 387618b72e1c26962d4454bbdad0a536dcfe0391
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 24 02:21:23 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5fe69aaf2d0..42ccb6c2a5e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2023-05-23  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.cc (avr_insn_cost): New static function.
+	(TARGET_INSN_COST): Define to that function.
+
 2023-05-22   Michael Meissner  <meissner@linux.ibm.com>
 
 	PR target/70243
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b7d9ba7ed1a..5b2cd0ee4d1 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230523
+20230524
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 2d1423be22f..beef8d6c8e7 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,198 @@
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109261
+	* include/experimental/bits/simd.h (_SimdWrapper::_M_set):
+	Avoid vector builtin subscripting in constant expressions.
+	(resizing_simd_cast): Avoid memcpy if constant_evaluated.
+	(const_where_expression, where_expression, where)
+	(__extract_part, simd_mask, _SimdIntOperators, simd): Add either
+	_GLIBCXX_SIMD_CONSTEXPR (on public APIs), or constexpr (on
+	internal APIs).
+	* include/experimental/bits/simd_builtin.h (__vector_permute)
+	(__vector_shuffle, __extract_part, _GnuTraits::_SimdCastType1)
+	(_GnuTraits::_SimdCastType2, _SimdImplBuiltin)
+	(_MaskImplBuiltin::_S_store): Add constexpr.
+	(_CommonImplBuiltin::_S_store_bool_array)
+	(_SimdImplBuiltin::_S_load, _SimdImplBuiltin::_S_store)
+	(_SimdImplBuiltin::_S_reduce, _MaskImplBuiltin::_S_load): Add
+	constant_evaluated case.
+	* include/experimental/bits/simd_fixed_size.h
+	(_S_masked_load): Reword comment.
+	(__tuple_element_meta, __make_meta, _SimdTuple::_M_apply_r)
+	(_SimdTuple::_M_subscript_read, _SimdTuple::_M_subscript_write)
+	(__make_simd_tuple, __optimize_simd_tuple, __extract_part)
+	(__autocvt_to_simd, _Fixed::__traits::_SimdBase)
+	(_Fixed::__traits::_SimdCastType, _SimdImplFixedSize): Add
+	constexpr.
+	(_SimdTuple::operator[], _M_set): Add constexpr and add
+	constant_evaluated case.
+	(_MaskImplFixedSize::_S_load): Add constant_evaluated case.
+	* include/experimental/bits/simd_scalar.h: Add constexpr.
+	* include/experimental/bits/simd_x86.h (_CommonImplX86): Add
+	constexpr and add constant_evaluated case.
+	(_SimdImplX86::_S_equal_to, _S_not_equal_to, _S_less)
+	(_S_less_equal): Value-initialize to satisfy constexpr
+	evaluation.
+	(_MaskImplX86::_S_load): Add constant_evaluated case.
+	(_MaskImplX86::_S_store): Add constexpr and constant_evaluated
+	case. Value-initialize local variables.
+	(_MaskImplX86::_S_logical_and, _S_logical_or, _S_bit_not)
+	(_S_bit_and, _S_bit_or, _S_bit_xor): Add constant_evaluated
+	case.
+	* testsuite/experimental/simd/pr109261_constexpr_simd.cc: New
+	test.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-22  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_builtin.h (_S_fpclassify): Move
+	__infn into #ifdef'ed block.
+	* testsuite/experimental/simd/tests/fpclassify.cc: Declare
+	constants only when used.
+	* testsuite/experimental/simd/tests/frexp.cc: Likewise.
+	* testsuite/experimental/simd/tests/logarithm.cc: Likewise.
+	* testsuite/experimental/simd/tests/trunc_ceil_floor.cc:
+	Likewise.
+	* testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc:
+	Move totest and expect1 into #ifdef'ed block.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-03-28  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd.h (is_simd_flag_type): New.
+	(_IsSimdFlagType): New.
+	(copy_from, copy_to, load ctors): Constrain _Flags using
+	_IsSimdFlagType.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-03-28  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_x86.h (_SimdImplX86): Use
+	_Base::_S_divides if the optimized _S_divides function is hidden
+	via the preprocessor.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-03-21  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_detail.h: Don't declare the
+	simd API as constexpr with Clang.
+	* include/experimental/bits/simd_x86.h (__movm): New.
+	(_S_blend_avx512): Resolve FIXME. Implement blend using __movm
+	and ?:.
+	(_SimdImplX86::_S_masked_unary): Clang does not implement the
+	same builtins. Implement the function using __movm, ?:, and -
+	operators on vector_size types instead.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd.h: Line breaks and indenting
+	fixed to follow the libstdc++ standard.
+	* include/experimental/bits/simd_builtin.h: Likewise.
+	* include/experimental/bits/simd_fixed_size.h: Likewise.
+	* include/experimental/bits/simd_neon.h: Likewise.
+	* include/experimental/bits/simd_ppc.h: Likewise.
+	* include/experimental/bits/simd_scalar.h: Likewise.
+	* include/experimental/bits/simd_x86.h: Likewise.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108030
+	* include/experimental/bits/simd_fixed_size.h
+	(_SimdImplFixedSize::_S_broadcast): Replace inline with
+	_GLIBCXX_SIMD_INTRINSIC.
+	(_SimdImplFixedSize::_S_generate): Likewise.
+	(_SimdImplFixedSize::_S_load): Likewise.
+	(_SimdImplFixedSize::_S_masked_load): Likewise.
+	(_SimdImplFixedSize::_S_store): Likewise.
+	(_SimdImplFixedSize::_S_masked_store): Likewise.
+	(_SimdImplFixedSize::_S_min): Likewise.
+	(_SimdImplFixedSize::_S_max): Likewise.
+	(_SimdImplFixedSize::_S_complement): Likewise.
+	(_SimdImplFixedSize::_S_unary_minus): Likewise.
+	(_SimdImplFixedSize::_S_plus): Likewise.
+	(_SimdImplFixedSize::_S_minus): Likewise.
+	(_SimdImplFixedSize::_S_multiplies): Likewise.
+	(_SimdImplFixedSize::_S_divides): Likewise.
+	(_SimdImplFixedSize::_S_modulus): Likewise.
+	(_SimdImplFixedSize::_S_bit_and): Likewise.
+	(_SimdImplFixedSize::_S_bit_or): Likewise.
+	(_SimdImplFixedSize::_S_bit_xor): Likewise.
+	(_SimdImplFixedSize::_S_bit_shift_left): Likewise.
+	(_SimdImplFixedSize::_S_bit_shift_right): Likewise.
+	(_SimdImplFixedSize::_S_remquo): Add inline keyword (to be
+	explicit about not always-inline, yet).
+	(_SimdImplFixedSize::_S_isinf): Likewise.
+	(_SimdImplFixedSize::_S_isfinite): Likewise.
+	(_SimdImplFixedSize::_S_isnan): Likewise.
+	(_SimdImplFixedSize::_S_isnormal): Likewise.
+	(_SimdImplFixedSize::_S_signbit): Likewise.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108856
+	* include/experimental/bits/simd_builtin.h
+	(_SimdImplBuiltin::_S_masked_unary): More efficient
+	implementation of masked inc-/decrement for integers and floats
+	without AVX2.
+	* include/experimental/bits/simd_x86.h
+	(_SimdImplX86::_S_masked_unary): New. Use AVX512 masked subtract
+	builtins for masked inc-/decrement.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	* testsuite/experimental/simd/tests/reductions.cc: Introduce
+	max_distance as the type-dependent max error.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108030
+	* include/experimental/bits/simd_detail.h
+	(_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA): Define as empty for
+	__clang__.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-16  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108030
+	* include/experimental/bits/simd_detail.h: Define
+	_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA.
+	* include/experimental/bits/simd.h: Annotate lambdas with
+	_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA.
+	* include/experimental/bits/simd_builtin.h: Ditto.
+	* include/experimental/bits/simd_converter.h: Ditto.
+	* include/experimental/bits/simd_fixed_size.h: Ditto.
+	* include/experimental/bits/simd_math.h: Ditto.
+	* include/experimental/bits/simd_neon.h: Ditto.
+	* include/experimental/bits/simd_x86.h: Ditto.
+
 2023-05-16  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 8be71168f7bbafa04f592a7524432351ffea71ba
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Tue May 23 23:48:49 2023

    libstdc++: Add missing constexpr to simd_neon
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/109261
            * include/experimental/bits/simd_neon.h (_S_reduce): Add
            constexpr and make NEON implementation conditional on
            not __builtin_is_constant_evaluated.
    
    (cherry picked from commit b0a483b0a011f9cbc8b25053eae809c77dae2a12)

diff --git a/libstdc++-v3/include/experimental/bits/simd_neon.h b/libstdc++-v3/include/experimental/bits/simd_neon.h
index 5eb5b9655f9..3adb366ec8f 100644
--- a/libstdc++-v3/include/experimental/bits/simd_neon.h
+++ b/libstdc++-v3/include/experimental/bits/simd_neon.h
@@ -84,50 +84,46 @@ template <typename _Abi, typename>
     // }}}
     // _S_reduce {{{
     template <typename _Tp, typename _BinaryOperation>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
       _S_reduce(simd<_Tp, _Abi> __x, _BinaryOperation&& __binary_op)
       {
-	constexpr size_t _Np = __x.size();
-	if constexpr (sizeof(__x) == 16 && _Np >= 4
-		      && !_Abi::template _S_is_partial<_Tp>)
-	  {
-	    const auto __halves = split<simd<_Tp, simd_abi::_Neon<8>>>(__x);
-	    const auto __y = __binary_op(__halves[0], __halves[1]);
-	    return _SimdImplNeon<simd_abi::_Neon<8>>::_S_reduce(
-	      __y, static_cast<_BinaryOperation&&>(__binary_op));
-	  }
-	else if constexpr (_Np == 8)
-	  {
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<1, 0, 3, 2, 5, 4, 7, 6>(
-				       __x._M_data)));
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<3, 2, 1, 0, 7, 6, 5, 4>(
-				       __x._M_data)));
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<7, 6, 5, 4, 3, 2, 1, 0>(
-				       __x._M_data)));
-	    return __x[0];
-	  }
-	else if constexpr (_Np == 4)
-	  {
-	    __x
-	      = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				   __vector_permute<1, 0, 3, 2>(__x._M_data)));
-	    __x
-	      = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				   __vector_permute<3, 2, 1, 0>(__x._M_data)));
-	    return __x[0];
-	  }
-	else if constexpr (_Np == 2)
+	if (not __builtin_is_constant_evaluated())
 	  {
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<1, 0>(__x._M_data)));
-	    return __x[0];
+	    constexpr size_t _Np = __x.size();
+	    if constexpr (sizeof(__x) == 16 && _Np >= 4
+			    && !_Abi::template _S_is_partial<_Tp>)
+	      {
+		const auto __halves = split<simd<_Tp, simd_abi::_Neon<8>>>(__x);
+		const auto __y = __binary_op(__halves[0], __halves[1]);
+		return _SimdImplNeon<simd_abi::_Neon<8>>::_S_reduce(
+			 __y, static_cast<_BinaryOperation&&>(__binary_op));
+	      }
+	    else if constexpr (_Np == 8)
+	      {
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<1, 0, 3, 2, 5, 4, 7, 6>(__x._M_data)));
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<3, 2, 1, 0, 7, 6, 5, 4>(__x._M_data)));
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<7, 6, 5, 4, 3, 2, 1, 0>(__x._M_data)));
+		return __x[0];
+	      }
+	    else if constexpr (_Np == 4)
+	      {
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<1, 0, 3, 2>(__x._M_data)));
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<3, 2, 1, 0>(__x._M_data)));
+		return __x[0];
+	      }
+	    else if constexpr (_Np == 2)
+	      {
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<1, 0>(__x._M_data)));
+		return __x[0];
+	      }
 	  }
-	else
-	  return _Base::_S_reduce(__x,
-				  static_cast<_BinaryOperation&&>(__binary_op));
+	return _Base::_S_reduce(__x, static_cast<_BinaryOperation&&>(__binary_op));
       }
 
     // }}}

commit 2b502c3119c91fe3ba2313f0842a3bedd395bc91
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Wed May 24 12:50:46 2023

    libstdc++: Fix SFINAE for __is_intrinsic_type on ARM
    
    On ARM NEON doesn't support double, so __is_intrinsic_type_v<double,
    whatever> should say false (instead of being ill-formed).
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/109261
            * include/experimental/bits/simd.h (__intrinsic_type):
            Specialize __intrinsic_type<double, 8> and
            __intrinsic_type<double, 16> in any case, but provide the member
            type only with __aarch64__.
    
    (cherry picked from commit aa8b363171a95b8f867a74f29c75f9577e9087e1)

diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h
index c8419156ece..ec142c91c04 100644
--- a/libstdc++-v3/include/experimental/bits/simd.h
+++ b/libstdc++-v3/include/experimental/bits/simd.h
@@ -2369,15 +2369,21 @@ template <>
   struct __intrinsic_type<float, 16, void>
   { using type = float32x4_t; };
 
-#if _GLIBCXX_SIMD_HAVE_NEON_A64
 template <>
   struct __intrinsic_type<double, 8, void>
-  { using type = float64x1_t; };
+  {
+#if _GLIBCXX_SIMD_HAVE_NEON_A64
+   using type = float64x1_t;
+#endif
+  };
 
 template <>
   struct __intrinsic_type<double, 16, void>
-  { using type = float64x2_t; };
+  {
+#if _GLIBCXX_SIMD_HAVE_NEON_A64
+    using type = float64x2_t;
 #endif
+  };
 
 #define _GLIBCXX_SIMD_ARM_INTRIN(_Bits, _Np)                                   \
 template <>                                                                    \

commit ff7360dafe209b960535eaaa3efcfbaaa44daff9
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Wed May 24 16:43:07 2023

    libstdc++: Fix type of first argument to vec_cntm call
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/109949
            * include/experimental/bits/simd.h (__intrinsic_type): If
            __ALTIVEC__ is defined, map gnu::vector_size types to their
            corresponding __vector T types without losing unsignedness of
            integer types. Also prefer long long over long.
            * include/experimental/bits/simd_ppc.h (_S_popcount): Cast mask
            object to the expected unsigned vector type.
    
    (cherry picked from commit efd2b55d8562c6e80cb7ee8b9b1f9418f0c00cd9)

diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h
index ec142c91c04..10ed1422640 100644
--- a/libstdc++-v3/include/experimental/bits/simd.h
+++ b/libstdc++-v3/include/experimental/bits/simd.h
@@ -2466,11 +2466,40 @@ template <typename _Tp, size_t _Bytes>
 		  "no __intrinsic_type support for 64-bit floating point on PowerPC w/o VSX");
 #endif
 
-    using type =
-      typename __intrinsic_type_impl<
-		 conditional_t<is_floating_point_v<_Tp>,
-			       conditional_t<_S_is_ldouble, double, _Tp>,
-			       __int_for_sizeof_t<_Tp>>>::type;
+    static constexpr auto __element_type()
+    {
+      if constexpr (is_floating_point_v<_Tp>)
+	{
+	  if constexpr (_S_is_ldouble)
+	    return double {};
+	  else
+	    return _Tp {};
+	}
+      else if constexpr (is_signed_v<_Tp>)
+	{
+	  if constexpr (sizeof(_Tp) == sizeof(_SChar))
+	    return _SChar {};
+	  else if constexpr (sizeof(_Tp) == sizeof(short))
+	    return short {};
+	  else if constexpr (sizeof(_Tp) == sizeof(int))
+	    return int {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_LLong))
+	    return _LLong {};
+	}
+      else
+	{
+	  if constexpr (sizeof(_Tp) == sizeof(_UChar))
+	    return _UChar {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_UShort))
+	    return _UShort {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_UInt))
+	    return _UInt {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_ULLong))
+	    return _ULLong {};
+	}
+    }
+
+    using type = typename __intrinsic_type_impl<decltype(__element_type())>::type;
   };
 #endif // __ALTIVEC__
 
diff --git a/libstdc++-v3/include/experimental/bits/simd_ppc.h b/libstdc++-v3/include/experimental/bits/simd_ppc.h
index 40ad48bcec1..484814e9a3a 100644
--- a/libstdc++-v3/include/experimental/bits/simd_ppc.h
+++ b/libstdc++-v3/include/experimental/bits/simd_ppc.h
@@ -130,7 +130,8 @@ template <typename _Abi, typename>
 	const auto __kv = __as_vector(__k);
 	if constexpr (__have_power10vec)
 	  {
-	    return vec_cntm(__to_intrin(__kv), 1);
+	    using _Intrin = __intrinsic_type16_t<make_unsigned_t<__int_for_sizeof_t<_Tp>>>;
+	    return vec_cntm(reinterpret_cast<_Intrin>(__kv), 1);
 	  }
 	else if constexpr (sizeof(_Tp) >= sizeof(int))
 	  {

commit 002a4f04b3c9479380b07e93a2072b99778f06d4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu May 25 02:20:23 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5b2cd0ee4d1..37d8ec9db79 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230524
+20230525
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index beef8d6c8e7..a39512d440d 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,37 @@
+2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109949
+	* include/experimental/bits/simd.h (__intrinsic_type): If
+	__ALTIVEC__ is defined, map gnu::vector_size types to their
+	corresponding __vector T types without losing unsignedness of
+	integer types. Also prefer long long over long.
+	* include/experimental/bits/simd_ppc.h (_S_popcount): Cast mask
+	object to the expected unsigned vector type.
+
+2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109261
+	* include/experimental/bits/simd.h (__intrinsic_type):
+	Specialize __intrinsic_type<double, 8> and
+	__intrinsic_type<double, 16> in any case, but provide the member
+	type only with __aarch64__.
+
+2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109261
+	* include/experimental/bits/simd_neon.h (_S_reduce): Add
+	constexpr and make NEON implementation conditional on
+	not __builtin_is_constant_evaluated.
+
 2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
 
 	Backported from master:

commit 4d39f68b891ed2ac7aca5ef24119f50976b84c22
Author: Georg-Johann Lay <avr@gjlay.de>
Date:   Thu May 25 19:02:34 2023

    target/82931: Make a pattern more generic to match more bit-transfers.
    
    There is already a pattern in avr.md that matches single-bit transfers
    from one register to another one, but it only handled bit 0 of 8-bit
    registers.  This change makes that pattern more generic so it matches
    more of similar single-bit transfers.
    
    gcc/
            PR target/82931
            * config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6.
            Handle any bit position and use mode QISI.
            * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost
            of 2 insns for bit-transfer of respective style.
    
    gcc/testsuite/
            PR target/82931
            * gcc.target/avr/pr82931.c: New test.

diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 406b2cbcef5..e52f1d81db7 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -10844,6 +10844,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
             *total += COSTS_N_INSNS (1);
           return true;
         }
+      if (IOR == code
+          && AND == GET_CODE (XEXP (x, 0))
+          && AND == GET_CODE (XEXP (x, 1))
+          && single_zero_operand (XEXP (XEXP (x, 0), 1), mode))
+        {
+          // Open-coded bit transfer.
+          *total = COSTS_N_INSNS (2);
+          return true;
+        }
       *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
       *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, 0, speed);
       if (!CONST_INT_P (XEXP (x, 1)))
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 1c12a5b2def..4b994296554 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -9097,16 +9097,20 @@
   "bst %3,0\;bld %0,%4"
   [(set_attr "length" "2")])
 
-;; Move bit $3.0 into bit $0.0.
-;; For bit 0, combiner generates slightly different pattern.
-(define_insn "*movbitqi.0"
-  [(set (match_operand:QI 0 "register_operand"                     "=r")
-        (ior:QI (and:QI (match_operand:QI 1 "register_operand"      "0")
-                        (match_operand:QI 2 "single_zero_operand"   "n"))
-                (and:QI (match_operand:QI 3 "register_operand"      "r")
-                        (const_int 1))))]
-  "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
-  "bst %3,0\;bld %0,0"
+;; Move bit $3.x into bit $0.x.
+(define_insn "*movbit<mode>.0-6"
+  [(set (match_operand:QISI 0 "register_operand"                       "=r")
+        (ior:QISI (and:QISI (match_operand:QISI 1 "register_operand"    "0")
+                            (match_operand:QISI 2 "single_zero_operand" "n"))
+                  (and:QISI (match_operand:QISI 3 "register_operand"    "r")
+                            (match_operand:QISI 4 "single_one_operand"  "n"))))]
+  "GET_MODE_MASK(<MODE>mode)
+   == (GET_MODE_MASK(<MODE>mode) & (INTVAL(operands[2]) ^ INTVAL(operands[4])))"
+  {
+    auto bitmask = GET_MODE_MASK (<MODE>mode) & UINTVAL (operands[4]);
+    operands[4] = GEN_INT (exact_log2 (bitmask));
+    return "bst %T3%T4" CR_TAB "bld %T0%T4";
+  }
   [(set_attr "length" "2")])
 
 ;; Move bit $2.0 into bit $0.7.
diff --git a/gcc/testsuite/gcc.target/avr/pr82931.c b/gcc/testsuite/gcc.target/avr/pr82931.c
new file mode 100644
index 00000000000..477284fa127
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/pr82931.c
@@ -0,0 +1,29 @@
+/* { dg-options "-Os" } */
+/* { dg-final { scan-assembler-times "bst" 4 } } */
+/* { dg-final { scan-assembler-times "bld" 4 } } */
+
+typedef __UINT8_TYPE__ uint8_t;
+typedef __UINT16_TYPE__ uint16_t;
+
+#define BitMask (1u << 14)
+#define Bit8Mask ((uint8_t) (1u << 4))
+
+void merge1_8 (uint8_t *dst, const uint8_t *src)
+{
+    *dst = (*src & Bit8Mask) | (*dst & ~ Bit8Mask);
+}
+
+void merge2_8 (uint8_t *dst, const uint8_t *src)
+{
+    *dst ^= (*dst ^ *src) & Bit8Mask;
+}
+
+void merge1_16 (uint16_t *dst, const uint16_t *src)
+{
+    *dst = (*src & BitMask) | (*dst & ~ BitMask);
+}
+
+void merge2_16 (uint16_t *dst, const uint16_t *src)
+{
+    *dst ^= (*dst ^ *src) & BitMask;
+}

commit 0537c71aa7ef88c4ffe754cf7af81e346273b079
Author: Georg-Johann Lay <avr@gjlay.de>
Date:   Tue May 23 14:54:12 2023

    target/104327: Allow more inlining between different optimization levels.
    
    avr-common.cc introduces the following options that are set depending
    on optimization level: -mgas-isr-prologues, -mmain-is-OS-task and
    -fsplit-wide-types-early.  The inliner thinks that different options
    disallow cross-optimization inlining, so provide can_inline_p.
    
    gcc/
            PR target/104327
            * config/avr/avr.cc (avr_can_inline_p): New static function.
            (TARGET_CAN_INLINE_P): Define to that function.

diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index e52f1d81db7..52aa5c26e1e 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -1019,6 +1019,19 @@ avr_no_gccisr_function_p (tree func)
   return avr_lookup_function_attribute1 (func, "no_gccisr");
 }
 
+
+/* Implement `TARGET_CAN_INLINE_P'.  */
+/* Some options like -mgas_isr_prologues depend on optimization level,
+   and the inliner might think that due to different options, inlining
+   is not permitted; see PR104327.  */
+
+static bool
+avr_can_inline_p (tree /* caller */, tree /* callee */)
+{
+  // No restrictions whatsoever.
+  return true;
+}
+
 /* Implement `TARGET_SET_CURRENT_FUNCTION'.  */
 /* Sanity cheching for above function attributes.  */
 
@@ -14768,6 +14781,9 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #undef  TARGET_MD_ASM_ADJUST
 #define TARGET_MD_ASM_ADJUST avr_md_asm_adjust
 
+#undef  TARGET_CAN_INLINE_P
+#define TARGET_CAN_INLINE_P avr_can_inline_p
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 

commit 16dc59588804e099b2bd59452232f78a10fe965a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 26 02:20:14 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 42ccb6c2a5e..dd3669d66ed 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/104327
+	* config/avr/avr.cc (avr_can_inline_p): New static function.
+	(TARGET_CAN_INLINE_P): Define to that function.
+
+2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/82931
+	* config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6.
+	Handle any bit position and use mode QISI.
+	* config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost
+	of 2 insns for bit-transfer of respective style.
+
 2023-05-23  Georg-Johann Lay  <avr@gjlay.de>
 
 	* config/avr/avr.cc (avr_insn_cost): New static function.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 37d8ec9db79..1ecb4a83fea 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230525
+20230526
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 00cb9083c22..15be02f2667 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/82931
+	* gcc.target/avr/pr82931.c: New test.
+
 2023-05-22   Michael Meissner  <meissner@linux.ibm.com>
 
 	PR target/70243

commit 10ebb8b9db2ec7ad53e4fc1f2900d9a8c8ddeaea
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 27 02:19:37 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1ecb4a83fea..f2e1a8687bc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230526
+20230527

commit b189fdbd54e564afcf56020ee3677e4150ea0597
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 28 02:19:29 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f2e1a8687bc..4f495f3bb8a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230527
+20230528

commit 5fefed9dbbf5a0258a372c000e0fc331b9e75252
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon May 29 13:18:01 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4f495f3bb8a..5f5439b6a42 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230528
+20230529

commit 7b75c5fd57cccdc3d509317a8a10acaf98f77311
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 30 02:20:05 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5f5439b6a42..9de50cecbd7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230529
+20230530

commit 2910660f00c74d12d17e3114870e287804a3332c
Author: Andreas Schwab <schwab@suse.de>
Date:   Sun May 28 12:08:22 2023

    riscv: update riscv_asan_shadow_offset
    
    gcc/
            PR target/110036
            * config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to
            match libsanitizer.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4939d9964db..dddd72aa237 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5600,9 +5600,8 @@ riscv_asan_shadow_offset (void)
   /* We only have libsanitizer support for RV64 at present.
 
      This number must match kRiscv*_ShadowOffset* in the file
-     libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
-     even though 1<<36 makes more sense.  */
-  return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
+     libsanitizer/asan/asan_mapping.h.  */
+  return TARGET_64BIT ? HOST_WIDE_INT_UC (0xd55550000) : 0;
 }
 
 /* Initialize the GCC target structure.  */

commit 6ae07a5cd9b43a4d1cb0bbde938fbd0a53f7ae3c
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Tue May 23 16:30:53 2023

    testsuite: make mve_intrinsic_type_overloads-int.c libc-agnostic
    
    Glibc defines int32_t as 'int' while newlib defines it as 'long int'.
    
    Although these correspond to the same size, g++ complains when using the
    'wrong' version:
      invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive]
    or
      invalid conversion from 'int*' to 'int32_t*' {aka 'long int*'} [-fpermissive]
    
    when calling vst1q(int32*, int32x4_t) with a first parameter of type
    'long int *' (resp. 'int *')
    
    To make this test pass with any type of toolchain, this patch defines
    'word_type' according to which libc is in use.
    
    2023-05-23  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/testsuite/
            * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c:
            Support both definitions of int32_t.
    
    (cherry picked from commit d12d2aa4fccc76a9a08c8120c5e37d9cab8683e8)

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
index 7947dc024bc..ab51cc8b323 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
@@ -47,14 +47,22 @@ foo2 (short * addr, int16x8_t value)
   vst1q (addr, value);
 }
 
-void
-foo3 (int * addr, int32x4_t value)
-{
-  vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
-}
+/* Glibc defines int32_t as 'int' while newlib defines it as 'long int'.
+
+   Although these correspond to the same size, g++ complains when using the
+   'wrong' version:
+  invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive]
+
+  The trick below is to make this test pass whether using glibc-based or
+  newlib-based toolchains.  */
 
+#if defined(__GLIBC__)
+#define word_type int
+#else
+#define word_type long int
+#endif
 void
-foo4 (long * addr, int32x4_t value)
+foo3 (word_type * addr, int32x4_t value)
 {
   vst1q (addr, value);
 }
@@ -78,13 +86,7 @@ foo7 (unsigned short * addr, uint16x8_t value)
 }
 
 void
-foo8 (unsigned int * addr, uint32x4_t value)
-{
-  vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
-}
-
-void
-foo9 (unsigned long * addr, uint32x4_t value)
+foo8 (unsigned word_type * addr, uint32x4_t value)
 {
   vst1q (addr, value);
 }

commit 7c184ac708535c808df04a8ec074c934c971f9c4
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Thu May 25 10:45:21 2023

    libstdc++: Resolve -Wsign-compare issue
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * include/experimental/bits/simd_ppc.h (_S_bit_shift_left):
            Negative __y is UB, so prefer signed compare.
    
    (cherry picked from commit 1a1abec1d618cde709c585fcce89330bb33b07ac)

diff --git a/libstdc++-v3/include/experimental/bits/simd_ppc.h b/libstdc++-v3/include/experimental/bits/simd_ppc.h
index 484814e9a3a..b9a0d3fdffa 100644
--- a/libstdc++-v3/include/experimental/bits/simd_ppc.h
+++ b/libstdc++-v3/include/experimental/bits/simd_ppc.h
@@ -64,7 +64,7 @@ template <typename _Abi, typename>
 	__x = _Base::_S_bit_shift_left(__x, __y);
 	if constexpr (sizeof(_Tp) < sizeof(int))
 	  {
-	    if (__y >= sizeof(_Tp) * __CHAR_BIT__)
+	    if (__y >= int(sizeof(_Tp) * __CHAR_BIT__))
 	      return {};
 	  }
 	return __x;

commit c6ce93538145372d2d6077e3991a3053c1262e14
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Thu May 25 12:07:45 2023

    libstdc++: Fix test assumptions on long and long double
    
    Expect that long might not fit into the long double mantissa bits.
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * testsuite/experimental/simd/tests/operator_cvt.cc: Make long
            double <-> (u)long conversion tests conditional on sizeof(long
            double) and sizeof(long).
    
    (cherry picked from commit 291549d43e823f163fa9961e42a751b5ce0d57fb)

diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/operator_cvt.cc b/libstdc++-v3/testsuite/experimental/simd/tests/operator_cvt.cc
index 3241d33f654..6f9d3c3b780 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/operator_cvt.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/operator_cvt.cc
@@ -220,8 +220,6 @@ template <typename V>
 	binary_op_return_type<vldouble, short>();
 	binary_op_return_type<vldouble, ushort>();
 	binary_op_return_type<vldouble, uint>();
-	binary_op_return_type<vldouble, long>();
-	binary_op_return_type<vldouble, ulong>();
 	binary_op_return_type<vldouble, float>();
 	binary_op_return_type<vldouble, double>();
 
@@ -231,8 +229,6 @@ template <typename V>
 	binary_op_return_type<vf64<long double>, ushort>();
 	binary_op_return_type<vf64<long double>, int>();
 	binary_op_return_type<vf64<long double>, uint>();
-	binary_op_return_type<vf64<long double>, long>();
-	binary_op_return_type<vf64<long double>, ulong>();
 	binary_op_return_type<vf64<long double>, float>();
 	binary_op_return_type<vf64<long double>, double>();
 	binary_op_return_type<vf64<long double>, vf64<long double>>();
@@ -245,8 +241,6 @@ template <typename V>
 	binary_op_return_type<simd<long double, A>, ushort>();
 	binary_op_return_type<simd<long double, A>, int>();
 	binary_op_return_type<simd<long double, A>, uint>();
-	binary_op_return_type<simd<long double, A>, long>();
-	binary_op_return_type<simd<long double, A>, ulong>();
 	binary_op_return_type<simd<long double, A>, float>();
 	binary_op_return_type<simd<long double, A>, double>();
 
@@ -258,6 +252,24 @@ template <typename V>
 	    VERIFY((is_substitution_failure<vf64<ldouble>, ullong>));
 	    VERIFY((is_substitution_failure<simd<ldouble, A>, llong>));
 	    VERIFY((is_substitution_failure<simd<ldouble, A>, ullong>));
+	    if constexpr (sizeof(long) == sizeof(llong))
+	      {
+		VERIFY((is_substitution_failure<vldouble, long>));
+		VERIFY((is_substitution_failure<vldouble, ulong>));
+		VERIFY((is_substitution_failure<vf64<ldouble>, long>));
+		VERIFY((is_substitution_failure<vf64<ldouble>, ulong>));
+		VERIFY((is_substitution_failure<simd<ldouble, A>, long>));
+		VERIFY((is_substitution_failure<simd<ldouble, A>, ulong>));
+	      }
+	    else
+	      {
+		binary_op_return_type<vldouble, long>();
+		binary_op_return_type<vldouble, ulong>();
+		binary_op_return_type<vf64<long double>, long>();
+		binary_op_return_type<vf64<long double>, ulong>();
+		binary_op_return_type<simd<long double, A>, long>();
+		binary_op_return_type<simd<long double, A>, ulong>();
+	      }
 	  }
 	else
 	  {
@@ -267,6 +279,12 @@ template <typename V>
 	    binary_op_return_type<vf64<long double>, ullong>();
 	    binary_op_return_type<simd<long double, A>, llong>();
 	    binary_op_return_type<simd<long double, A>, ullong>();
+	    binary_op_return_type<vldouble, long>();
+	    binary_op_return_type<vldouble, ulong>();
+	    binary_op_return_type<vf64<long double>, long>();
+	    binary_op_return_type<vf64<long double>, ulong>();
+	    binary_op_return_type<simd<long double, A>, long>();
+	    binary_op_return_type<simd<long double, A>, ulong>();
 	  }
 
 	VERIFY((is_substitution_failure<vf64<long double>, vldouble>));

commit 64295a0340faf2c3a711b983ea8f65163ab18a9e
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Thu May 25 12:53:06 2023

    libstdc++: Simplify calculation of expected value in simd test
    
    This avoids a failure on PR109964.
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            * testsuite/experimental/simd/tests/integer_operators.cc:
            Compute expected value differently to avoid getting turned into
            a vector shift.
    
    (cherry picked from commit 3e2689e568425f14d6728504ad6f5d32b90320ad)

diff --git a/libstdc++-v3/testsuite/experimental/simd/tests/integer_operators.cc b/libstdc++-v3/testsuite/experimental/simd/tests/integer_operators.cc
index 40760059ca2..4991b052641 100644
--- a/libstdc++-v3/testsuite/experimental/simd/tests/integer_operators.cc
+++ b/libstdc++-v3/testsuite/experimental/simd/tests/integer_operators.cc
@@ -180,11 +180,10 @@ template <typename V>
 	  for (int j = 0; j < 100; ++j)
 	    {
 	      const V seq([&](auto i) -> T { return (j + i) % n_promo_bits; });
-	      COMPARE(V(1) >> seq, V([&](auto i) { return T(T(1) >> seq[i]); }))
-		<< "seq = " << seq;
-	      COMPARE(make_value_unknown(V(1)) >> make_value_unknown(seq),
-		V([&](auto i) { return T(T(1) >> seq[i]); }))
-		<< "seq = " << seq;
+	      const V expect([&](auto i) { return seq[i] == 0 ? T(1) : T(0); });
+	      COMPARE(V(1) >> seq, expect) << "\nseq = " << seq;
+	      COMPARE(make_value_unknown(V(1)) >> make_value_unknown(seq), expect)
+		<< "\nseq = " << seq;
 	    }
 	  for_constexpr<int, 0, n_promo_bits - 1>([](auto shift_ic) {
 	    constexpr int shift = shift_ic;

commit 467887d5750d03d438ab704437b2c5e5da78497e
Author: Matthias Kretz <m.kretz@gsi.de>
Date:   Fri May 26 12:23:44 2023

    libstdc++: Correct NTTP and simd_mask ctor call
    
    Signed-off-by: Matthias Kretz <m.kretz@gsi.de>
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/109822
            * include/experimental/bits/simd.h (to_native): Use int NTTP
            as specified in PTS2.
            (to_compatible): Likewise. Add missing tag to call mask
            generator ctor.
            * testsuite/experimental/simd/pr109822_cast_functions.cc: New
            test.
    
    (cherry picked from commit 668d43502f465d48adbc1fe2956b979f36657e5f)

diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h
index 10ed1422640..b18ce9d34a2 100644
--- a/libstdc++-v3/include/experimental/bits/simd.h
+++ b/libstdc++-v3/include/experimental/bits/simd.h
@@ -3304,7 +3304,7 @@ template <typename _Tp, int _Np>
     return {__mem, vector_aligned};
   }
 
-template <typename _Tp, size_t _Np>
+template <typename _Tp, int _Np>
   _GLIBCXX_SIMD_INTRINSIC
   enable_if_t<(_Np == native_simd_mask<_Tp>::size()), native_simd_mask<_Tp>>
   to_native(const fixed_size_simd_mask<_Tp, _Np>& __x)
@@ -3315,7 +3315,7 @@ template <typename _Tp, size_t _Np>
   }
 
 // to_compatible {{{2
-template <typename _Tp, size_t _Np>
+template <typename _Tp, int _Np>
   _GLIBCXX_SIMD_INTRINSIC enable_if_t<(_Np == simd<_Tp>::size()), simd<_Tp>>
   to_compatible(const simd<_Tp, simd_abi::fixed_size<_Np>>& __x)
   {
@@ -3324,12 +3324,13 @@ template <typename _Tp, size_t _Np>
     return {__mem, vector_aligned};
   }
 
-template <typename _Tp, size_t _Np>
+template <typename _Tp, int _Np>
   _GLIBCXX_SIMD_INTRINSIC
   enable_if_t<(_Np == simd_mask<_Tp>::size()), simd_mask<_Tp>>
   to_compatible(const simd_mask<_Tp, simd_abi::fixed_size<_Np>>& __x)
   {
     return simd_mask<_Tp>(
+	     __private_init,
 	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
   }
 
diff --git a/libstdc++-v3/testsuite/experimental/simd/pr109822_cast_functions.cc b/libstdc++-v3/testsuite/experimental/simd/pr109822_cast_functions.cc
new file mode 100644
index 00000000000..3deafbf7a1f
--- /dev/null
+++ b/libstdc++-v3/testsuite/experimental/simd/pr109822_cast_functions.cc
@@ -0,0 +1,63 @@
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+
+#include <experimental/simd>
+
+namespace stdx = std::experimental;
+
+template <typename T, typename V>
+  void
+  test01()
+  {
+    using M = typename V::mask_type;
+    [[maybe_unused]] auto x = to_fixed_size(V());
+    [[maybe_unused]] auto k = to_fixed_size(M());
+    if constexpr (stdx::simd<T>::size() == V::size())
+      {
+	[[maybe_unused]] auto xx = to_compatible(x);
+	[[maybe_unused]] auto kk = to_compatible(k);
+	x = to_fixed_size(xx);
+	k = to_fixed_size(kk);
+      }
+    if constexpr (stdx::native_simd<T>::size() == V::size())
+      {
+	[[maybe_unused]] auto xx = to_native(x);
+	[[maybe_unused]] auto kk = to_native(k);
+	x = to_fixed_size(xx);
+	k = to_fixed_size(kk);
+      }
+  }
+
+template <typename T>
+  void
+  iterate_abis()
+  {
+    test01<T, stdx::simd<T, stdx::simd_abi::scalar>>();
+    test01<T, stdx::simd<T>>();
+    test01<T, stdx::native_simd<T>>();
+    test01<T, stdx::fixed_size_simd<T, 3>>();
+    test01<T, stdx::fixed_size_simd<T, stdx::simd_abi::max_fixed_size<T> - 4>>();
+  }
+
+int
+main()
+{
+  iterate_abis<char>();
+  iterate_abis<wchar_t>();
+  iterate_abis<char16_t>();
+  iterate_abis<char32_t>();
+
+  iterate_abis<signed char>();
+  iterate_abis<unsigned char>();
+  iterate_abis<short>();
+  iterate_abis<unsigned short>();
+  iterate_abis<int>();
+  iterate_abis<unsigned int>();
+  iterate_abis<long>();
+  iterate_abis<unsigned long>();
+  iterate_abis<long long>();
+  iterate_abis<unsigned long long>();
+  iterate_abis<float>();
+  iterate_abis<double>();
+  iterate_abis<long double>();
+}

commit 987b24420bc8ce95830992d36a1304e585be79b3
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Fri May 5 13:34:23 2023

    [libstdc++] [testsuite] xfail double-prec from_chars for ldbl
    
    When long double is wider than double, but from_chars is implemented
    in terms of double, tests that involve the full precision of long
    double are expected to fail.  Mark them as such on aarch64-*-vxworks.
    
    
    for  libstdc++-v3/ChangeLog
    
            * testsuite/20_util/from_chars/4.cc: Skip long double test06
            on aarch64-vxworks.
            * testsuite/20_util/to_chars/long_double.cc: Xfail run on
            aarch64-vxworks.
    
    (cherry picked from commit e383fc69d2a3eab37319ea41543ee09c8cdd6e57)

diff --git a/libstdc++-v3/testsuite/20_util/from_chars/4.cc b/libstdc++-v3/testsuite/20_util/from_chars/4.cc
index c27df4ffa5e..6c840ece802 100644
--- a/libstdc++-v3/testsuite/20_util/from_chars/4.cc
+++ b/libstdc++-v3/testsuite/20_util/from_chars/4.cc
@@ -18,6 +18,7 @@
 // <charconv> is supported in C++14 as a GNU extension
 // { dg-do run { target c++14 } }
 // { dg-add-options ieee }
+// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* } }
 
 #include <charconv>
 #include <string>
@@ -354,7 +355,7 @@ test06()
 {
   test_max_mantissa<float, unsigned long>();
   test_max_mantissa<double, unsigned long long>();
-#ifdef __GLIBCXX_TYPE_INT_N_0
+#if defined __GLIBCXX_TYPE_INT_N_0 && !defined SKIP_LONG_DOUBLE
   test_max_mantissa<long double, unsigned __GLIBCXX_TYPE_INT_N_0>();
 #endif
 }
diff --git a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
index 94b5b5967d3..52e382e76a1 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
@@ -34,6 +34,10 @@
 // more portable and robust to differences in system printf behavior.
 // { dg-xfail-run-if "Non-conforming printf (see PR98384)" { *-*-solaris* *-*-darwin* } }
 
+// On systems that use double-precision from_chars for long double,
+// this is expected to fail.
+// { dg-xfail-run-if "from_chars limited to double-precision" { aarch64-*-vxworks* } }
+
 // { dg-require-effective-target ieee_floats }
 // { dg-require-effective-target size32plus }
 

commit b99118d46f4c35c355f99983809cfccc8cd67d7f
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Thu May 25 10:57:11 2023

    [libstdc++] [testsuite] xfail to_chars/long_double on x86-vxworks
    
    Just as on aarch64, x86's wider long double experiences loss of
    precision with from_chars implemented in terms of double.  Expect the
    execution fail.
    
    
    for  libstdc++-v3/ChangeLog
    
            * testsuite/20_util/to_chars/long_double.cc: Expect execution
            fail on x86-vxworks.
    
    (cherry picked from commit 7daa166fe89fca4ff1baa063c00a5a690f7e462f)

diff --git a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
index 52e382e76a1..01bfec79bb1 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
@@ -36,7 +36,7 @@
 
 // On systems that use double-precision from_chars for long double,
 // this is expected to fail.
-// { dg-xfail-run-if "from_chars limited to double-precision" { aarch64-*-vxworks* } }
+// { dg-xfail-run-if "from_chars limited to double-precision" { aarch64-*-vxworks* i*86-*-vxworks* } }
 
 // { dg-require-effective-target ieee_floats }
 // { dg-require-effective-target size32plus }

commit 9d43cd02c6e53155916ac0e2f8bdc48b6703771c
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Tue May 30 23:46:26 2023

    [libstdc++] [testsuite] xfail double-prec from_chars for x86_64 ldbl
    
    When long double is wider than double, but from_chars is implemented
    in terms of double, tests that involve the full precision of long
    double are expected to fail.  Mark them as such on x86_64-*-vxworks*.
    
    for  libstdc++-v3/ChangeLog
    
            * testsuite/20_util/from_chars/4.cc: Skip long double test06
            on x86_64-vxworks.
            * testsuite/20_util/to_chars/long_double.cc: Xfail run on
            x86_64-vxworks.
    
    (cherry picked from commit 282e4e745981c5c6e3edaae315e1f499a45402df)

diff --git a/libstdc++-v3/testsuite/20_util/from_chars/4.cc b/libstdc++-v3/testsuite/20_util/from_chars/4.cc
index 6c840ece802..495f22c365d 100644
--- a/libstdc++-v3/testsuite/20_util/from_chars/4.cc
+++ b/libstdc++-v3/testsuite/20_util/from_chars/4.cc
@@ -18,7 +18,7 @@
 // <charconv> is supported in C++14 as a GNU extension
 // { dg-do run { target c++14 } }
 // { dg-add-options ieee }
-// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* } }
+// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* x86_64-*-vxworks* } }
 
 #include <charconv>
 #include <string>
diff --git a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
index 01bfec79bb1..133410a8dbb 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
@@ -36,7 +36,7 @@
 
 // On systems that use double-precision from_chars for long double,
 // this is expected to fail.
-// { dg-xfail-run-if "from_chars limited to double-precision" { aarch64-*-vxworks* i*86-*-vxworks* } }
+// { dg-xfail-run-if "from_chars limited to double-precision" { aarch64-*-vxworks* i*86-*-vxworks* x86_64-*-vxworks* } }
 
 // { dg-require-effective-target ieee_floats }
 // { dg-require-effective-target size32plus }

commit 6bd66f01b2b629d2af66c3ce3c372f05ba59d11b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 31 02:20:34 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dd3669d66ed..f2ba8cc41a4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2023-05-30  Andreas Schwab  <schwab@suse.de>
+
+	PR target/110036
+	* config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to
+	match libsanitizer.
+
 2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
 
 	PR target/104327
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9de50cecbd7..748e702e080 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230530
+20230531
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 15be02f2667..da30fa001df 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-30  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	Backported from master:
+	2023-05-30  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c:
+	Support both definitions of int32_t.
+
 2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
 
 	PR target/82931
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index a39512d440d..214b6013268 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,70 @@
+2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	Backported from master:
+	2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	* testsuite/20_util/from_chars/4.cc: Skip long double test06
+	on x86_64-vxworks.
+	* testsuite/20_util/to_chars/long_double.cc: Xfail run on
+	x86_64-vxworks.
+
+2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	Backported from master:
+	2023-05-25  Alexandre Oliva  <oliva@adacore.com>
+
+	* testsuite/20_util/to_chars/long_double.cc: Expect execution
+	fail on x86-vxworks.
+
+2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	Backported from master:
+	2023-05-05  Alexandre Oliva  <oliva@adacore.com>
+
+	* testsuite/20_util/from_chars/4.cc: Skip long double test06
+	on aarch64-vxworks.
+	* testsuite/20_util/to_chars/long_double.cc: Xfail run on
+	aarch64-vxworks.
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109822
+	* include/experimental/bits/simd.h (to_native): Use int NTTP
+	as specified in PTS2.
+	(to_compatible): Likewise. Add missing tag to call mask
+	generator ctor.
+	* testsuite/experimental/simd/pr109822_cast_functions.cc: New
+	test.
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	* testsuite/experimental/simd/tests/integer_operators.cc:
+	Compute expected value differently to avoid getting turned into
+	a vector shift.
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	* testsuite/experimental/simd/tests/operator_cvt.cc: Make long
+	double <-> (u)long conversion tests conditional on sizeof(long
+	double) and sizeof(long).
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-26  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_ppc.h (_S_bit_shift_left):
+	Negative __y is UB, so prefer signed compare.
+
 2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
 
 	Backported from master:

commit bc92a44b59e2531285ae89ae518919e067d07a14
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 1 02:20:39 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 748e702e080..e171f9ed053 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230531
+20230601

commit 4466c5ba6e2f1759a2ce461f15fc4e018872a22e
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Jun 1 12:30:10 2023

    doc: Fix description of x86 -m32 option [PR109954]
    
    This option does not imply -march=i386 so it's incorrect to say it
    generates code that will run on "any i386 system".
    
    gcc/ChangeLog:
    
            PR target/109954
            * doc/invoke.texi (x86 Options): Fix description of -m32 option.
    
    (cherry picked from commit eeb92704967875411416b0b9508aa6f49e8192fd)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 87eedfffa6c..d945a5eae9f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -33101,7 +33101,7 @@ on x86-64 processors in 64-bit environments.
 Generate code for a 16-bit, 32-bit or 64-bit environment.
 The @option{-m32} option sets @code{int}, @code{long}, and pointer types
 to 32 bits, and
-generates code that runs on any i386 system.
+generates code that runs in 32-bit mode.
 
 The @option{-m64} option sets @code{int} to 32 bits and @code{long} and pointer
 types to 64 bits, and generates code for the x86-64 architecture.

commit 148e717a0cda31cdea59c2f8b61c16c8249b31a6
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 2 02:21:19 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f2ba8cc41a4..09eb8f795a9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR target/109954
+	* doc/invoke.texi (x86 Options): Fix description of -m32 option.
+
 2023-05-30  Andreas Schwab  <schwab@suse.de>
 
 	PR target/110036
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e171f9ed053..d0de28459d0 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230601
+20230602

commit 6f8e64989c2418bb8a4050fc1f50039a7b9a0225
Author: Georg-Johann Lay <avr@gjlay.de>
Date:   Fri Jun 2 12:41:07 2023

    target/110088: Improve operation of l-reg with const after move from d-reg.
    
    After reload, there may be sequences like
       lreg = dreg
       lreg = lreg <op> const
    with an LD_REGS dreg, non-LD_REGS lreg, and <op> in PLUS, IOR, AND.
    If dreg dies after the first insn, it is possible to use
       dreg = dreg <op> const
       lreg = dreg
    instead which is more efficient.
    
    gcc/
            PR target/110088
            * config/avr/avr.md: Add an RTL peephole to optimize operations on
            non-LD_REGS after a move from LD_REGS.
            (piaop): New code iterator.

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 4b994296554..6858dbab4ab 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -279,6 +279,7 @@
 (define_code_iterator any_extract [sign_extract zero_extract])
 (define_code_iterator any_shiftrt [lshiftrt ashiftrt])
 
+(define_code_iterator piaop [plus ior and])
 (define_code_iterator bitop [xor ior and])
 (define_code_iterator xior [xor ior])
 (define_code_iterator eqne [eq ne])
@@ -4714,7 +4715,8 @@
   [(parallel [(set (match_operand:HISI 0 "register_operand")
                    (bitop:HISI (match_dup 0)
                                (match_operand:HISI 1 "register_operand")))
-              (clobber (scratch:QI))])]
+              (clobber (scratch:QI))
+              (clobber (reg:CC REG_CC))])]
   "optimize
    && reload_completed"
   [(const_int 1)]
@@ -4728,6 +4730,43 @@
     DONE;
   })
 
+;; If  $0 = $0 <op> const  requires a QI scratch, and d-reg $1 dies after
+;; the first insn, then we can replace
+;;    $0 = $1
+;;    $0 = $0 <op> const
+;; by
+;;    $1 = $1 <op> const
+;;    $0 = $1
+;; This transorms constraint alternative "r,0,n,&d" of the first operation
+;; to alternative "d,0,n,X".
+;; "*addhi3_clobber"  "*addpsi3"  "*addsi3"
+;; "*addhq3"  "*adduhq3"  "*addha3"  "*adduha3"
+;; "*addsq3"  "*addusq3"  "*addsa3"  "*addusa3"
+;; "*iorhi3"  "*iorpsi3"  "*iorsi3"
+;; "*andhi3"  "*andpsi3"  "*andsi3"
+(define_peephole2
+  [(parallel [(set (match_operand:ORDERED234 0 "register_operand")
+                   (match_operand:ORDERED234 1 "d_register_operand"))
+              (clobber (reg:CC REG_CC))])
+   (parallel [(set (match_dup 0)
+                   (piaop:ORDERED234 (match_dup 0)
+                                     (match_operand:ORDERED234 2 "const_operand")))
+              ; A d-reg as scratch tells that this insn is expensive, and
+              ; that $0 is not a d-register: l-reg or something like SI:14 etc.
+              (clobber (match_operand:QI 3 "d_register_operand"))
+              (clobber (reg:CC REG_CC))])]
+  "peep2_reg_dead_p (1, operands[1])"
+  [(parallel [(set (match_dup 1)
+                   (piaop:ORDERED234 (match_dup 1)
+                                     (match_dup 2)))
+              (clobber (scratch:QI))
+              (clobber (reg:CC REG_CC))])
+   ; Unfortunately, the following insn misses a REG_DEAD note for $1,
+   ; so this peep2 works only once.
+   (parallel [(set (match_dup 0)
+                   (match_dup 1))
+              (clobber (reg:CC REG_CC))])])
+
 
 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
 ;; swap

commit a55d4a7474cd1ce3547857a1342f3897d1da15e5
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 3 02:20:46 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 09eb8f795a9..397bdb4b975 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2023-06-02  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/110088
+	* config/avr/avr.md: Add an RTL peephole to optimize operations on
+	non-LD_REGS after a move from LD_REGS.
+	(piaop): New code iterator.
+
 2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d0de28459d0..1760b75fb77 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230602
+20230603

commit e9fda0f289dd654b3ef3b91584b1377a9a0f0c6e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 4 02:20:12 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1760b75fb77..a5bdb7bdd09 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230603
+20230604

commit 59a264d5d8bb3fb73557aafc21319fd4fa6b1ab4
Author: Steve Kargl <kargl@gcc.gnu.org>
Date:   Fri Jun 2 19:44:11 2023

    Fortran: fix diagnostics for SELECT RANK [PR100607]
    
    gcc/fortran/ChangeLog:
    
            PR fortran/100607
            * resolve.cc (resolve_select_rank): Remove duplicate error.
            (resolve_fl_var_and_proc): Prevent NULL pointer dereference and
            suppress error message for temporary.
    
    gcc/testsuite/ChangeLog:
    
            PR fortran/100607
            * gfortran.dg/select_rank_6.f90: New test.
    
    (cherry picked from commit fae09dfc0e6bf4cfe35d817558827aea78c6426f)

diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc
index 14baf63e6af..426eb3dead3 100644
--- a/gcc/fortran/resolve.cc
+++ b/gcc/fortran/resolve.cc
@@ -9923,11 +9923,6 @@ resolve_select_rank (gfc_code *code, gfc_namespace *old_ns)
 			       || gfc_expr_attr (code->expr1).pointer))
 	gfc_error ("RANK (*) at %L cannot be used with the pointer or "
 		   "allocatable selector at %L", &c->where, &code->expr1->where);
-
-      if (case_value == -1 && (gfc_expr_attr (code->expr1).allocatable
-			       || gfc_expr_attr (code->expr1).pointer))
-	gfc_error ("RANK (*) at %L cannot be used with the pointer or "
-		   "allocatable selector at %L", &c->where, &code->expr1->where);
     }
 
   /* Add EXEC_SELECT to switch on rank.  */
@@ -12913,7 +12908,10 @@ resolve_fl_var_and_proc (gfc_symbol *sym, int mp_flag)
 
       if (allocatable)
 	{
-	  if (dimension && as->type != AS_ASSUMED_RANK)
+	  if (dimension
+	      && as
+	      && as->type != AS_ASSUMED_RANK
+	      && !sym->attr.select_rank_temporary)
 	    {
 	      gfc_error ("Allocatable array %qs at %L must have a deferred "
 			 "shape or assumed rank", sym->name, &sym->declared_at);
diff --git a/gcc/testsuite/gfortran.dg/select_rank_6.f90 b/gcc/testsuite/gfortran.dg/select_rank_6.f90
new file mode 100644
index 00000000000..d0121777bb5
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/select_rank_6.f90
@@ -0,0 +1,48 @@
+! { dg-do compile }
+! PR fortran/100607 - fix diagnostics for SELECT RANK
+! Contributed by T.Burnus
+
+program p
+  implicit none
+  integer, allocatable :: A(:,:,:)
+
+  allocate(a(5:6,-2:2, 99:100))
+  call foo(a)
+  call bar(a)
+
+contains
+
+  subroutine foo(x)
+    integer, allocatable :: x(..)
+    if (rank(x) /= 3) stop 1
+    if (any (lbound(x) /= [5, -2, 99])) stop 2
+
+    select rank (x)
+    rank(3)
+      if (any (lbound(x) /= [5, -2, 99])) stop 3
+    end select
+
+    select rank (x) ! { dg-error "pointer or allocatable selector at .2." }
+    rank(*)         ! { dg-error "pointer or allocatable selector at .2." }
+      if (rank(x) /= 1) stop 4
+      if (lbound(x, 1) /= 1) stop 5
+    end select
+  end
+
+  subroutine bar(x)
+    integer :: x(..)
+    if (rank(x) /= 3) stop 6
+    if (any (lbound(x) /= 1)) stop 7
+
+    select rank (x)
+    rank(3)
+      if (any (lbound(x) /= 1)) stop 8
+    end select
+
+    select rank (x)
+    rank(*)
+      if (rank(x) /= 1) stop 9
+      if (lbound(x, 1) /= 1) stop 10
+    end select
+  end
+end

commit 256cb821273d328e98d87aae2a061e0e889ec408
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 5 02:20:32 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a5bdb7bdd09..3e73975bf5e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230604
+20230605
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 111242f14d6..693c1b25661 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-04  Steve Kargl  <kargl@gcc.gnu.org>
+
+	Backported from master:
+	2023-06-02  Steve Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/100607
+	* resolve.cc (resolve_select_rank): Remove duplicate error.
+	(resolve_fl_var_and_proc): Prevent NULL pointer dereference and
+	suppress error message for temporary.
+
 2023-05-20  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index da30fa001df..5e24e954efc 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2023-06-04  Steve Kargl  <kargl@gcc.gnu.org>
+
+	Backported from master:
+	2023-06-02  Steve Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/100607
+	* gfortran.dg/select_rank_6.f90: New test.
+
 2023-05-30  Christophe Lyon  <christophe.lyon@linaro.org>
 
 	Backported from master:

commit eb89c6ec171fcc388398395419ea8ee89ef8c76a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 6 02:21:30 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3e73975bf5e..7e14e0ee146 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230605
+20230606

commit 6a204757ffc734de7e7794e337cd6d387cf18a48
Author: Iain Buclaw <ibuclaw@gdcproject.org>
Date:   Tue Jun 6 15:25:59 2023

    d: Merge upstream dmd 316b89f1e3, phobos 8e8aaae50.
    
    Updates D language version to v2.100.2.
    
    Phobos changes:
    
        - Fix instantiating std.container.array.Array!T where T is a
          shared class.
        - Fix calling toString on a const std.typecons.Nullable type.
    
    gcc/d/ChangeLog:
    
            * dmd/MERGE: Merge upstream dmd 316b89f1e3.
            * dmd/VERSION: Bump version to v2.100.2.
    
    libphobos/ChangeLog:
    
            * src/MERGE: Merge upstream phobos 8e8aaae50.

diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE
index d79ebfae806..51736565a57 100644
--- a/gcc/d/dmd/MERGE
+++ b/gcc/d/dmd/MERGE
@@ -1,4 +1,4 @@
-76e3b41375e3e1cb4dbca692b587d8e916c0b49f
+316b89f1e3dffcad488c26f56f58c8adfcb84b26
 
 The first line of this file holds the git revision number of the last
 merge done from the dlang/dmd repository.
diff --git a/gcc/d/dmd/VERSION b/gcc/d/dmd/VERSION
index 83a14f57e16..868f8007d2f 100644
--- a/gcc/d/dmd/VERSION
+++ b/gcc/d/dmd/VERSION
@@ -1 +1 @@
-v2.100.1
+v2.100.2
diff --git a/libphobos/src/MERGE b/libphobos/src/MERGE
index f2678185f39..8c570369602 100644
--- a/libphobos/src/MERGE
+++ b/libphobos/src/MERGE
@@ -1,4 +1,4 @@
-5fef0d28fc873fb5a0dbfb9149759d76a7b9f1b7
+8e8aaae5080ccc2e0a2202cbe9778dca96496a95
 
 The first line of this file holds the git revision number of the last
 merge done from the dlang/phobos repository.
diff --git a/libphobos/src/std/container/array.d b/libphobos/src/std/container/array.d
index 08f9ead196e..ecc45996925 100644
--- a/libphobos/src/std/container/array.d
+++ b/libphobos/src/std/container/array.d
@@ -412,9 +412,9 @@ if (!is(immutable T == immutable bool))
                     .destroy(e);
 
             static if (hasIndirections!T)
-                GC.removeRange(_payload.ptr);
+                GC.removeRange(cast(void*) _payload.ptr);
 
-            free(_payload.ptr);
+            free(cast(void*) _payload.ptr);
         }
 
         this(this) @disable;
@@ -489,14 +489,14 @@ if (!is(immutable T == immutable bool))
                 auto newPayload = newPayloadPtr[0 .. oldLength];
 
                 // copy old data over to new array
-                memcpy(newPayload.ptr, _payload.ptr, T.sizeof * oldLength);
+                memcpy(cast(void*) newPayload.ptr, cast(void*) _payload.ptr, T.sizeof * oldLength);
                 // Zero out unused capacity to prevent gc from seeing false pointers
-                memset(newPayload.ptr + oldLength,
+                memset( cast(void*) (newPayload.ptr + oldLength),
                         0,
                         (elements - oldLength) * T.sizeof);
-                GC.addRange(newPayload.ptr, sz);
-                GC.removeRange(_payload.ptr);
-                free(_payload.ptr);
+                GC.addRange(cast(void*) newPayload.ptr, sz);
+                GC.removeRange(cast(void*) _payload.ptr);
+                free(cast(void*) _payload.ptr);
                 _payload = newPayload;
             }
             else
@@ -611,12 +611,17 @@ if (!is(immutable T == immutable bool))
         return opEquals(rhs);
     }
 
+    // fix https://issues.dlang.org/show_bug.cgi?23140
+    private alias Unshared(T) = T;
+    private alias Unshared(T: shared U, U) = U;
+
     /// ditto
     bool opEquals(ref const Array rhs) const
     {
         if (empty) return rhs.empty;
         if (rhs.empty) return false;
-        return _data._payload == rhs._data._payload;
+
+        return cast(Unshared!(T)[]) _data._payload ==  cast(Unshared!(T)[]) rhs._data._payload;
     }
 
     /**
@@ -1740,6 +1745,16 @@ if (!is(immutable T == immutable bool))
     assertThrown!AssertError(array.length = 5);
 }
 
+// https://issues.dlang.org/show_bug.cgi?id=23140
+@system unittest
+{
+    shared class C
+    {
+    }
+
+    Array!C ac;
+    ac = Array!C([new C]);
+}
 ////////////////////////////////////////////////////////////////////////////////
 // Array!bool
 ////////////////////////////////////////////////////////////////////////////////
diff --git a/libphobos/src/std/typecons.d b/libphobos/src/std/typecons.d
index fb15001233a..34e884cac8a 100644
--- a/libphobos/src/std/typecons.d
+++ b/libphobos/src/std/typecons.d
@@ -3793,8 +3793,28 @@ Params:
                 sink.formatValue(_value, fmt);
             }
         }
+
+        void toString()(scope void delegate(const(char)[]) sink, scope const ref FormatSpec!char fmt) const
+        {
+            if (isNull)
+            {
+                sink.formatValue("Nullable.null", fmt);
+            }
+            else
+            {
+                sink.formatValue(_value, fmt);
+            }
+        }
     }
 
+@system unittest
+{
+    import std.conv : to;
+
+    const Nullable!(ulong, 0) x = 1;
+    assert(x.to!string == "1");
+}
+
 /**
 Check if `this` is in the null state.
 
@@ -4320,8 +4340,28 @@ Params:
                 sink.formatValue(*_value, fmt);
             }
         }
+
+        void toString()(scope void delegate(const(char)[]) sink, scope const ref FormatSpec!char fmt) const
+        {
+            if (isNull)
+            {
+                sink.formatValue("Nullable.null", fmt);
+            }
+            else
+            {
+                sink.formatValue(*_value, fmt);
+            }
+        }
     }
 
+@system unittest
+{
+    import std.conv : to;
+
+    const NullableRef!(ulong) x = new ulong(1);
+    assert(x.to!string == "1");
+}
+
 /**
 Binds the internal state to `value`.
 

commit 104da95833b28b9d2af786b8ee194c83be6e8da4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 7 02:21:41 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7e14e0ee146..2e61d1d960e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230606
+20230607
diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog
index 4218c9aec47..e6f4cea8e7b 100644
--- a/gcc/d/ChangeLog
+++ b/gcc/d/ChangeLog
@@ -1,3 +1,8 @@
+2023-06-06  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	* dmd/MERGE: Merge upstream dmd 316b89f1e3.
+	* dmd/VERSION: Bump version to v2.100.2.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/libphobos/ChangeLog b/libphobos/ChangeLog
index 953e1dbfca4..39eafa42df7 100644
--- a/libphobos/ChangeLog
+++ b/libphobos/ChangeLog
@@ -1,3 +1,7 @@
+2023-06-06  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	* src/MERGE: Merge upstream phobos 8e8aaae50.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.

commit 7e464d07d6acb1a209e28f88a686593fce19c658
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 8 02:20:56 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2e61d1d960e..73ca44c893e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230607
+20230608

commit a620451032abb28343c31438a4e779ea5d2e1bbf
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed May 24 10:33:04 2023

    arm: PR target/109939 Correct signedness of return type of __ssat intrinsics
    
    As the PR says we shouldn't be using qualifier_unsigned for the return type of the __ssat intrinsics.
    UNSIGNED_SAT_BINOP_UNSIGNED_IMM_QUALIFIERS already exists for that.
    This was just a thinko.
    This patch fixes this and the warning with -Wconversion goes away.
    
    Bootstrapped and tested on arm-none-linux-gnueabihf.
    
    gcc/ChangeLog:
    
            PR target/109939
            * config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use
            qualifier_none for the return operand.
    
    gcc/testsuite/ChangeLog:
    
            PR target/109939
            * gcc.target/arm/pr109939.c: New test.
    
    (cherry picked from commit 95542a6ec4b350c653b793b7c36a8210b0e9a89d)

diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc
index 36a40a1dc80..557d6f68fd1 100644
--- a/gcc/config/arm/arm-builtins.cc
+++ b/gcc/config/arm/arm-builtins.cc
@@ -97,7 +97,7 @@ arm_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 /* T (T, unsigned immediate).  */
 static enum arm_type_qualifiers
 arm_sat_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-  = { qualifier_unsigned, qualifier_none, qualifier_unsigned_immediate };
+  = { qualifier_none, qualifier_none, qualifier_unsigned_immediate };
 #define SAT_BINOP_UNSIGNED_IMM_QUALIFIERS \
   (arm_sat_binop_imm_qualifiers)
 
diff --git a/gcc/testsuite/gcc.target/arm/pr109939.c b/gcc/testsuite/gcc.target/arm/pr109939.c
new file mode 100644
index 00000000000..aafda7cd3cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr109939.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_sat_ok } */
+/* { dg-add-options arm_sat } */
+/* { dg-additional-options "-O -Wall -Wconversion" } */
+
+#include <arm_acle.h>
+
+int dbg_ssat_out;
+int dbg_ssat_in;
+
+void test_arm_ssat(void)
+{
+    dbg_ssat_out = __ssat(dbg_ssat_in, 16);
+}

commit 43619dc6e120a80305d4a52d7f9b8833c110a7db
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Thu May 25 14:34:46 2023

    arm: Fix ICE due to infinite splitting [PR109800]
    
    In r11-966-g9a182ef9ee011935d827ab5c6c9a7cd8e22257d8 we introduce a
    simplification to emit_move_insn that attempts to simplify moves of the form:
    
    (set (subreg:M1 (reg:M2 ...)) (constant C))
    
    where M1 and M2 are of equal mode size. That is problematic for the splitter
    vfp.md:no_literal_pool_df_immediate in the arm backend, which tries to pun an
    lvalue DFmode pseudo into DImode and assign a constant to it with
    emit_move_insn, as the new transformation simply undoes this, and we end up
    splitting indefinitely.
    
    This patch changes things around in the arm backend so that we use a
    DImode temporary (instead of DFmode) and first load the DImode constant
    into the pseudo, and then pun the pseudo into DFmode as an rvalue in a
    reg -> reg move. I believe this should be semantically equivalent but
    avoids the pathalogical behaviour seen in the PR.
    
    gcc/ChangeLog:
    
            PR target/109800
            * config/arm/arm.md (movdf): Generate temporary pseudo in DImode
            instead of DFmode.
            * config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an
            lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into
            DFmode as an rvalue.
    
    gcc/testsuite/ChangeLog:
    
            PR target/109800
            * gcc.target/arm/pure-code/pr109800.c: New test.
    
    (cherry picked from commit f5298d9969b4fa34ff3aecd54b9630e22b2984a5)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 60468f6182c..912b939f886 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -7466,7 +7466,7 @@
       && !arm_const_double_rtx (operands[1])
       && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1])))
     {
-      rtx clobreg = gen_reg_rtx (DFmode);
+      rtx clobreg = gen_reg_rtx (DImode);
       emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1],
 						   clobreg));
       DONE;
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 7a430ef8d36..31e5818d4e3 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -2138,7 +2138,7 @@
 (define_insn_and_split "no_literal_pool_df_immediate"
   [(set (match_operand:DF 0 "s_register_operand" "=w")
 	(match_operand:DF 1 "const_double_operand" "F"))
-   (clobber (match_operand:DF 2 "s_register_operand" "=r"))]
+   (clobber (match_operand:DI 2 "s_register_operand" "=r"))]
   "arm_disable_literal_pool
    && TARGET_VFP_BASE
    && !arm_const_double_rtx (operands[1])
@@ -2153,8 +2153,9 @@
   unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32);
   ival |= (zext_hwi (buf[1 - order], 32) << 32);
   rtx cst = gen_int_mode (ival, DImode);
-  emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst);
-  emit_move_insn (operands[0], operands[2]);
+  emit_move_insn (operands[2], cst);
+  emit_move_insn (operands[0],
+		  simplify_gen_subreg (DFmode, operands[2], DImode, 0));
   DONE;
 }
 )
diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
new file mode 100644
index 00000000000..d797b790232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mbig-endian -mpure-code" } */
+double f() { return 5.0; }

commit 7a6e2986aa6f2e30ccae2b826982026232a33fa2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 9 02:20:37 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 397bdb4b975..339199cf292 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2023-06-08  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-05-25  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/109800
+	* config/arm/arm.md (movdf): Generate temporary pseudo in DImode
+	instead of DFmode.
+	* config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an
+	lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into
+	DFmode as an rvalue.
+
+2023-06-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2023-05-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/109939
+	* config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use
+	qualifier_none for the return operand.
+
 2023-06-02  Georg-Johann Lay  <avr@gjlay.de>
 
 	PR target/110088
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 73ca44c893e..a4ca097fc3e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230608
+20230609
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5e24e954efc..9deca127269 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2023-06-08  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-05-25  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/109800
+	* gcc.target/arm/pure-code/pr109800.c: New test.
+
+2023-06-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2023-05-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/109939
+	* gcc.target/arm/pr109939.c: New test.
+
 2023-06-04  Steve Kargl  <kargl@gcc.gnu.org>
 
 	Backported from master:

commit 887f903ab05ddcac498247384734efbc6cf45147
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Jun 5 06:38:41 2023

    Explicitly view_convert_expr mask to signed type when folding pblendvb builtins.
    
    Since mask < 0 will be always false for vector char when
    -funsigned-char, but vpblendvb needs to check the most significant
    bit. The patch explicitly VCE to vector signed char.
    
    gcc/ChangeLog:
    
            PR target/110108
            * config/i386/i386.cc (ix86_gimple_fold_builtin): Explicitly
            view_convert_expr mask to signed type when folding pblendvb
            builtins.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/pr110108-2.c: New test.

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 9a9ff3b34b8..63e8e5e01fc 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -18396,8 +18396,10 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi)
 	      tree itype = GET_MODE_INNER (TYPE_MODE (type)) == E_SFmode
 		? intSI_type_node : intDI_type_node;
 	      type = get_same_sized_vectype (itype, type);
-	      arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2);
 	    }
+	  else
+	    type = signed_type_for (type);
+	  arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2);
 	  tree zero_vec = build_zero_cst (type);
 	  tree cmp_type = truth_type_for (type);
 	  tree cmp = gimple_build (&stmts, LT_EXPR, cmp_type, arg2, zero_vec);
diff --git a/gcc/testsuite/gcc.target/i386/pr110108-2.c b/gcc/testsuite/gcc.target/i386/pr110108-2.c
new file mode 100644
index 00000000000..2d1d2fd4991
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr110108-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2 -funsigned-char" } */
+/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */
+
+#include <immintrin.h>
+__m128i do_stuff_128(__m128i X0, __m128i X1, __m128i X2) {
+  __m128i Result = _mm_blendv_epi8(X0, X1, X2);
+  return Result;
+}
+
+__m256i do_stuff_256(__m256i X0, __m256i X1, __m256i X2) {
+  __m256i Result = _mm256_blendv_epi8(X0, X1, X2);
+  return Result;
+}

commit bc4adb88611cb17280ab15ac4e13ab1d05b11825
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Jun 9 09:10:29 2023

    fortran: Fix ICE on pr96024.f90 on big-endian hosts [PR96024]
    
    The pr96024.f90 testcase ICEs on big-endian hosts.  The problem is
    that length->val.integer is accessed after checking
    length->expr_type == EXPR_CONSTANT, but it is a CHARACTER constant
    which uses length->val.character union member instead and on big-endian
    we end up reading constant 0x100000000 rather than some small number
    on little-endian and if target doesn't have enough memory for 4 times
    that (i.e. 16GB allocation), it ICEs.
    
    2023-06-09  Jakub Jelinek  <jakub@redhat.com>
    
            PR fortran/96024
            * primary.cc (gfc_convert_to_structure_constructor): Only do
            constant string ctor length verification and truncation/padding
            if constant length has INTEGER type.
    
    (cherry picked from commit 4cf6e322adc19f927859e0a5edfa93cec4b8c844)

diff --git a/gcc/fortran/primary.cc b/gcc/fortran/primary.cc
index e48ba755c8a..1ae6a12e0b7 100644
--- a/gcc/fortran/primary.cc
+++ b/gcc/fortran/primary.cc
@@ -3196,10 +3196,11 @@ gfc_convert_to_structure_constructor (gfc_expr *e, gfc_symbol *sym, gfc_expr **c
 	goto cleanup;
 
       /* For a constant string constructor, make sure the length is
-	 correct; truncate of fill with blanks if needed.  */
+	 correct; truncate or fill with blanks if needed.  */
       if (this_comp->ts.type == BT_CHARACTER && !this_comp->attr.allocatable
 	  && this_comp->ts.u.cl && this_comp->ts.u.cl->length
 	  && this_comp->ts.u.cl->length->expr_type == EXPR_CONSTANT
+	  && this_comp->ts.u.cl->length->ts.type == BT_INTEGER
 	  && actual->expr->ts.type == BT_CHARACTER
 	  && actual->expr->expr_type == EXPR_CONSTANT)
 	{

commit 8d64b55db0bec62873503739fabc2a4d3219ad58
Author: Iain Sandoe <iain@sandoe.co.uk>
Date:   Thu Jun 1 14:43:35 2023

    Darwin, PPC: Fix struct layout with pragma pack [PR110044].
    
    This bug was essentially that darwin_rs6000_special_round_type_align()
    was ignoring externally-imposed capping of field alignment.
    
    Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
    
            PR target/110044
    
    gcc/ChangeLog:
    
            * config/rs6000/rs6000.cc (darwin_rs6000_special_round_type_align):
            Make sure that we do not have a cap on field alignment before altering
            the struct layout based on the type alignment of the first entry.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/powerpc/darwin-abi-13-0.c: New test.
            * gcc.target/powerpc/darwin-abi-13-1.c: New test.
            * gcc.target/powerpc/darwin-abi-13-2.c: New test.
            * gcc.target/powerpc/darwin-structs-0.h: New test.
    
    (cherry picked from commit 84d080a29a780973bef47171ba708ae2f7b4ee47)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f678561071a..56941e6e2df 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -8128,7 +8128,8 @@ darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
       type = TREE_TYPE (type);
   } while (AGGREGATE_TYPE_P (type));
 
-  if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
+  if (type != error_mark_node && ! AGGREGATE_TYPE_P (type)
+      && ! TYPE_PACKED (type) && maximum_field_alignment == 0)
     align = MAX (align, TYPE_ALIGN (type));
 
   return align;
diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c
new file mode 100644
index 00000000000..d8d3c63a083
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+#include "darwin-structs-0.h"
+
+int tcd[sizeof(cd) != 12 ? -1 : 1];
+int acd[__alignof__(cd) != 4 ? -1 : 1];
+
+int sdc[sizeof(dc) != 16 ? -1 : 1];
+int adc[__alignof__(dc) != 8 ? -1 : 1];
+
+int scL[sizeof(cL) != 12 ? -1 : 1];
+int acL[__alignof__(cL) != 4 ? -1 : 1];
+
+int sLc[sizeof(Lc) != 16 ? -1 : 1];
+int aLc[__alignof__(Lc) != 8 ? -1 : 1];
+
+int scD[sizeof(cD) != 32 ? -1 : 1];
+int acD[__alignof__(cD) != 16 ? -1 : 1];
+
+int sDc[sizeof(Dc) != 32 ? -1 : 1];
+int aDc[__alignof__(Dc) != 16 ? -1 : 1];
diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c
new file mode 100644
index 00000000000..4d888d383fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+#pragma pack(push, 1)
+
+#include "darwin-structs-0.h"
+
+int tcd[sizeof(cd) != 9 ? -1 : 1];
+int acd[__alignof__(cd) != 1 ? -1 : 1];
+
+int sdc[sizeof(dc) != 9 ? -1 : 1];
+int adc[__alignof__(dc) != 1 ? -1 : 1];
+
+int scL[sizeof(cL) != 9 ? -1 : 1];
+int acL[__alignof__(cL) != 1 ? -1 : 1];
+
+int sLc[sizeof(Lc) != 9 ? -1 : 1];
+int aLc[__alignof__(Lc) != 1 ? -1 : 1];
+
+int scD[sizeof(cD) != 17 ? -1 : 1];
+int acD[__alignof__(cD) != 1 ? -1 : 1];
+
+int sDc[sizeof(Dc) != 17 ? -1 : 1];
+int aDc[__alignof__(Dc) != 1 ? -1 : 1];
+
+#pragma pack(pop)
diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c
new file mode 100644
index 00000000000..3bd52c0a8f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+#pragma pack(push, 2)
+
+#include "darwin-structs-0.h"
+
+int tcd[sizeof(cd) != 10 ? -1 : 1];
+int acd[__alignof__(cd) != 2 ? -1 : 1];
+
+int sdc[sizeof(dc) != 10 ? -1 : 1];
+int adc[__alignof__(dc) != 2 ? -1 : 1];
+
+int scL[sizeof(cL) != 10 ? -1 : 1];
+int acL[__alignof__(cL) != 2 ? -1 : 1];
+
+int sLc[sizeof(Lc) != 10 ? -1 : 1];
+int aLc[__alignof__(Lc) != 2 ? -1 : 1];
+
+int scD[sizeof(cD) != 18 ? -1 : 1];
+int acD[__alignof__(cD) != 2 ? -1 : 1];
+
+int sDc[sizeof(Dc) != 18 ? -1 : 1];
+int aDc[__alignof__(Dc) != 2 ? -1 : 1];
+
+#pragma pack(pop)
diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h b/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h
new file mode 100644
index 00000000000..1db44f7a808
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h
@@ -0,0 +1,29 @@
+typedef struct _cd {
+ char c;
+ double d;
+} cd;
+
+typedef struct _dc {
+ double d;
+ char c;
+} dc;
+
+typedef struct _cL {
+ char c;
+ long long L;
+} cL;
+
+typedef struct _Lc {
+ long long L;
+ char c;
+} Lc;
+
+typedef struct _cD {
+ char c;
+ long double D;
+} cD;
+
+typedef struct _Dc {
+ long double D;
+ char c;
+} Dc;

commit 3b09a5453114fee10b0f0984793ce968503dbea7
Author: Jeevitha Palanisamy <jeevitha@linux.ibm.com>
Date:   Tue Jun 6 13:19:02 2023

    rs6000: Remove duplicate expression [PR106907]
    
    PR106907 has few warnings spotted from cppcheck. In that addressing duplicate
    expression issue here. Here the same expression is used twice in logical
    AND(&&) operation which result in same result so removing that.
    
    2023-06-06  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
    
    gcc/
            PR target/106907
            * config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove
            duplicate expression.
    
    (cherry picked from commit c4deccd44655c5d748dfed200a37f2b678c32fe8)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 56941e6e2df..2623e4bd6e9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -28604,7 +28604,6 @@ vec_const_128bit_to_bytes (rtx op,
 
   info->all_words_same
     = (info->words[0] == info->words[1]
-       && info->words[0] == info->words[1]
        && info->words[0] == info->words[2]
        && info->words[0] == info->words[3]);
 

commit 2614b3f942d2a0e05cc69a3a080d0cf23e36573d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 10 02:21:07 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 339199cf292..72c11de8ed6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,29 @@
+2023-06-09  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
+
+	Backported from master:
+	2023-06-06  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
+
+	PR target/106907
+	* config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove
+	duplicate expression.
+
+2023-06-09  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-06-02  Iain Sandoe  <iain@sandoe.co.uk>
+
+	PR target/110044
+	* config/rs6000/rs6000.cc (darwin_rs6000_special_round_type_align):
+	Make sure that we do not have a cap on field alignment before altering
+	the struct layout based on the type alignment of the first entry.
+
+2023-06-09  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/110108
+	* config/i386/i386.cc (ix86_gimple_fold_builtin): Explicitly
+	view_convert_expr mask to signed type when folding pblendvb
+	builtins.
+
 2023-06-08  Alex Coplan  <alex.coplan@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a4ca097fc3e..dc88eb6d69e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230609
+20230610
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 693c1b25661..21b5d65d2dc 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-06-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/96024
+	* primary.cc (gfc_convert_to_structure_constructor): Only do
+	constant string ctor length verification and truncation/padding
+	if constant length has INTEGER type.
+
 2023-06-04  Steve Kargl  <kargl@gcc.gnu.org>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9deca127269..a32ee4887cb 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,18 @@
+2023-06-09  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-06-02  Iain Sandoe  <iain@sandoe.co.uk>
+
+	PR target/110044
+	* gcc.target/powerpc/darwin-abi-13-0.c: New test.
+	* gcc.target/powerpc/darwin-abi-13-1.c: New test.
+	* gcc.target/powerpc/darwin-abi-13-2.c: New test.
+	* gcc.target/powerpc/darwin-structs-0.h: New test.
+
+2023-06-09  liuhongt  <hongtao.liu@intel.com>
+
+	* gcc.target/i386/pr110108-2.c: New test.
+
 2023-06-08  Alex Coplan  <alex.coplan@arm.com>
 
 	Backported from master:

commit ee92dc2dae45acc79d4dc08ea31adf894831840a
Author: Georg-Johann Lay <avr@gjlay.de>
Date:   Sat Jun 10 21:47:53 2023

    target/109650: Fix wrong code after cc0 -> CCmode transition.
    
    This patch fixes a wrong-code bug in the wake of PR92729, the transition that
    turned the AVR backend from cc0 to CCmode.  In cc0, the insn that uses cc0 like
    a conditional branch always follows the cc0 setter, which is no more the case
    with CCmode where set and use of REG_CC might be in different basic blocks.
    
    This patch removes the machine-dependent reorg pass in avr_reorg entirely.
    
    It is replaced by a new, AVR specific mini-pass that runs prior to split2.
    Canonicalization of comparisons away from the "difficult" codes GT[U] and LE[U]
    is now mostly performed by implementing TARGET_CANONICALIZE_COMPARISON.
    
    Moreover:
    
    * Text peephole conditions get "dead_or_set_regno_p (*, REG_CC)" as needed.
    
    * RTL peephole conditions get "peep2_regno_dead_p (*, REG_CC)" as needed.
    
    * Conditional branches no more clobber REG_CC.
    
    * insn output for compares looks ahead to determine the branch mode in use.
      This needs also "dead_or_set_regno_p (*, REG_CC)".
    
    * Add RTL peepholes for decrement-and-branch detection.
    
    * Some of the patterns like "*cmphi.zero-extend.0" lost their
      combine-ational part wit PR92729.  Restore them.
    
    Finally, it fixes some of the many indentation glitches left over from PR92729.
    
    gcc/
            PR target/109650
            PR target/92729
            Backport from 2023-05-10 master r14-1688.
            * config/avr/avr-passes.def (avr_pass_ifelse): Insert new pass.
            * config/avr/avr.cc (avr_pass_ifelse): New RTL pass.
            (avr_pass_data_ifelse): New pass_data for it.
            (make_avr_pass_ifelse, avr_redundant_compare, avr_cbranch_cost)
            (avr_canonicalize_comparison, avr_out_plus_set_ZN)
            (avr_out_cmp_ext): New functions.
            (compare_condtition): Make sure REG_CC dies in the branch insn.
            (avr_rtx_costs_1): Add computation of cbranch costs.
            (avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_ZN, ADJUST_LEN_CMP_ZEXT]:
            [ADJUST_LEN_CMP_SEXT]Handle them.
            (TARGET_CANONICALIZE_COMPARISON): New define.
            (avr_simplify_comparison_p, compare_diff_p, avr_compare_pattern)
            (avr_reorg_remove_redundant_compare, avr_reorg): Remove functions.
            (TARGET_MACHINE_DEPENDENT_REORG): Remove define.
            * config/avr/avr-protos.h (avr_simplify_comparison_p): Remove proto.
            (make_avr_pass_ifelse, avr_out_plus_set_ZN, cc_reg_rtx)
            (avr_out_cmp_zext): New Protos
            * config/avr/avr.md (branch, difficult_branch): Don't split insns.
            (*cbranchhi.zero-extend.0", *cbranchhi.zero-extend.1")
            (*swapped_tst<mode>, *add.for.eqne.<mode>): New insns.
            (*cbranch<mode>4): Rename to cbranch<mode>4_insn.
            (define_peephole): Add dead_or_set_regno_p(insn,REG_CC) as needed.
            (define_deephole2): Add peep2_regno_dead_p(*,REG_CC) as needed.
            Add new RTL peepholes for decrement-and-branch and *swapped_tst<mode>.
            Rework signtest-and-branch peepholes for *sbrx_branch<mode>.
            (adjust_len) [add_set_ZN, cmp_zext]: New.
            (QIPSI): New mode iterator.
            (ALLs1, ALLs2, ALLs4, ALLs234): New mode iterators.
            (gelt): New code iterator.
            (gelt_eqne): New code attribute.
            (rvbranch, *rvbranch, difficult_rvbranch, *difficult_rvbranch)
            (branch_unspec, *negated_tst<mode>, *reversed_tst<mode>)
            (*cmpqi_sign_extend): Remove insns.
            (define_c_enum "unspec") [UNSPEC_IDENTITY]: Remove.
            * config/avr/avr-dimode.md (cbranch<mode>4): Canonicalize comparisons.
            * config/avr/predicates.md (scratch_or_d_register_operand): New.
            * config/avr/constraints.md (Yxx): New constraint.
    
    gcc/testsuite/
            PR target/109650
            Backport from 2023-05-10 master r14-1688.
            * gcc.target/avr/torture/pr109650-1.c: New test.
            * gcc.target/avr/torture/pr109650-2.c: New test.

diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md
index 6e491336915..28e97da0516 100644
--- a/gcc/config/avr/avr-dimode.md
+++ b/gcc/config/avr/avr-dimode.md
@@ -455,12 +455,18 @@
 (define_expand "cbranch<mode>4"
   [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
-                        [(match_operand:ALL8 1 "register_operand"  "")
-                         (match_operand:ALL8 2 "nonmemory_operand" "")])
-         (label_ref (match_operand 3 "" ""))
-         (pc)))]
+                        [(match_operand:ALL8 1 "register_operand")
+                         (match_operand:ALL8 2 "nonmemory_operand")])
+                      (label_ref (match_operand 3))
+                      (pc)))]
   "avr_have_dimode"
    {
+    int icode = (int) GET_CODE (operands[0]);
+
+    targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false);
+    operands[0] = gen_rtx_fmt_ee ((enum rtx_code) icode,
+                                  VOIDmode, operands[1], operands[2]);
+
     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
 
     avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
@@ -490,8 +496,8 @@
         (if_then_else (match_operator 0 "ordered_comparison_operator"
                         [(reg:ALL8 ACC_A)
                          (reg:ALL8 ACC_B)])
-         (label_ref (match_operand 1 "" ""))
-         (pc)))]
+                      (label_ref (match_operand 1))
+                      (pc)))]
   "avr_have_dimode"
   "#"
   "&& reload_completed"
@@ -544,8 +550,8 @@
         (if_then_else (match_operator 0 "ordered_comparison_operator"
                         [(reg:ALL8 ACC_A)
                          (match_operand:ALL8 1 "const_operand" "n Ynn")])
-         (label_ref (match_operand 2 "" ""))
-         (pc)))
+                      (label_ref (match_operand 2 "" ""))
+                      (pc)))
    (clobber (match_scratch:QI 3 "=&d"))]
   "avr_have_dimode
    && !s8_operand (operands[1], VOIDmode)"
diff --git a/gcc/config/avr/avr-passes.def b/gcc/config/avr/avr-passes.def
index d8630151090..ba0c3f10972 100644
--- a/gcc/config/avr/avr-passes.def
+++ b/gcc/config/avr/avr-passes.def
@@ -43,3 +43,23 @@ INSERT_PASS_BEFORE (pass_free_cfg, 1, avr_pass_recompute_notes);
    insns withaout any insns in between.  */
 
 INSERT_PASS_AFTER (pass_expand, 1, avr_pass_casesi);
+
+/* If-else decision trees generated for switch / case may produce sequences
+   like
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+      SREG = compare (reg, 1 + val);
+	  if (SREG >= 0)  goto label2;
+
+   which can be optimized to
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+	  if (SREG >= 0)  goto label2;
+
+   The optimal place for such a pass would be directly after expand, but
+   it's not possible for a jump insn to target more than one code label.
+   Hence, run a mini pass right before split2 which introduces REG_CC.  */
+
+INSERT_PASS_BEFORE (pass_split_after_reload, 1, avr_pass_ifelse);
diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h
index 6023b33bcfe..e164967038f 100644
--- a/gcc/config/avr/avr-protos.h
+++ b/gcc/config/avr/avr-protos.h
@@ -58,6 +58,8 @@ extern const char *ret_cond_branch (rtx x, int len, int reverse);
 extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*);
 extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*);
 extern const char *avr_out_insert_notbit (rtx_insn *, rtx*, rtx, int*);
+extern const char *avr_out_plus_set_ZN (rtx*, int*);
+extern const char *avr_out_cmp_ext (rtx*, enum rtx_code, int*);
 
 extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int *len);
 extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int *len);
@@ -112,8 +114,6 @@ extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest);
 
 extern void avr_final_prescan_insn (rtx_insn *insn, rtx *operand,
 				    int num_operands);
-extern int avr_simplify_comparison_p (machine_mode mode,
-				      RTX_CODE op, rtx x);
 extern RTX_CODE avr_normalize_condition (RTX_CODE condition);
 extern void out_shift_with_cnt (const char *templ, rtx_insn *insn,
 				rtx operands[], int *len, int t_len);
@@ -145,6 +145,7 @@ extern rtx tmp_reg_rtx;
 extern rtx zero_reg_rtx;
 extern rtx all_regs_rtx[32];
 extern rtx rampz_rtx;
+extern rtx cc_reg_rtx;
 
 #endif /* RTX_CODE */
 
@@ -160,6 +161,7 @@ class rtl_opt_pass;
 extern rtl_opt_pass *make_avr_pass_pre_proep (gcc::context *);
 extern rtl_opt_pass *make_avr_pass_recompute_notes (gcc::context *);
 extern rtl_opt_pass *make_avr_pass_casesi (gcc::context *);
+extern rtl_opt_pass *make_avr_pass_ifelse (gcc::context *);
 
 /* From avr-log.cc */
 
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 52aa5c26e1e..c286acabf2c 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -359,6 +359,41 @@ public:
   }
 }; // avr_pass_casesi
 
+
+static const pass_data avr_pass_data_ifelse =
+{
+  RTL_PASS,      // type
+  "",            // name (will be patched)
+  OPTGROUP_NONE, // optinfo_flags
+  TV_DF_SCAN,    // tv_id
+  0,             // properties_required
+  0,             // properties_provided
+  0,             // properties_destroyed
+  0,             // todo_flags_start
+  TODO_df_finish | TODO_df_verify // todo_flags_finish
+};
+
+class avr_pass_ifelse : public rtl_opt_pass
+{
+public:
+  avr_pass_ifelse (gcc::context *ctxt, const char *name)
+    : rtl_opt_pass (avr_pass_data_ifelse, ctxt)
+  {
+    this->name = name;
+  }
+
+  void avr_rest_of_handle_ifelse (function*);
+
+  virtual bool gate (function*) { return optimize > 0; }
+
+  virtual unsigned int execute (function *func)
+  {
+    avr_rest_of_handle_ifelse (func);
+
+    return 0;
+  }
+}; // avr_pass_ifelse
+
 } // anon namespace
 
 rtl_opt_pass*
@@ -373,6 +408,12 @@ make_avr_pass_casesi (gcc::context *ctxt)
   return new avr_pass_casesi (ctxt, "avr-casesi");
 }
 
+rtl_opt_pass*
+make_avr_pass_ifelse (gcc::context *ctxt)
+{
+  return new avr_pass_ifelse (ctxt, "avr-ifelse");
+}
+
 
 /* Make one parallel insn with all the patterns from insns i[0]..i[5].  */
 
@@ -686,6 +727,304 @@ avr_pass_casesi::avr_rest_of_handle_casesi (function *func)
 }
 
 
+/* A helper for the next method.  Suppose we have two conditional branches
+
+      if (reg <cond1> xval1) goto label1;
+      if (reg <cond2> xval2) goto label2;
+
+   If the second comparison is redundant and there is a code <cond> such
+   that the sequence can be performed as
+
+      REG_CC = compare (reg, xval1);
+      if (REG_CC <cond1> 0)  goto label1;
+      if (REG_CC <cond> 0)   goto label2;
+
+   then return <cond>.  Otherwise, return UNKNOWN.
+   xval1 and xval2 are CONST_INT, and mode is the scalar int mode in which
+   the comparison will be carried out.  reverse_cond1 can be set to reverse
+   condition cond1.  This is useful if the second comparison does not follow
+   the first one, but is located after label1 like in:
+
+      if (reg <cond1> xval1) goto label1;
+      ...
+      label1:
+      if (reg <cond2> xval2) goto label2;  */
+
+static enum rtx_code
+avr_redundant_compare (enum rtx_code cond1, rtx xval1,
+		       enum rtx_code cond2, rtx xval2,
+		       machine_mode mode, bool reverse_cond1)
+{
+  HOST_WIDE_INT ival1 = INTVAL (xval1);
+  HOST_WIDE_INT ival2 = INTVAL (xval2);
+
+  unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
+  unsigned HOST_WIDE_INT uval1 = mask & UINTVAL (xval1);
+  unsigned HOST_WIDE_INT uval2 = mask & UINTVAL (xval2);
+
+  if (reverse_cond1)
+    cond1 = reverse_condition (cond1);
+
+  if (cond1 == EQ)
+    {
+      ////////////////////////////////////////////////
+      // A sequence like
+      //    if (reg == val)  goto label1;
+      //    if (reg > val)   goto label2;
+      // can be re-written using the same, simple comparison like in:
+      //    REG_CC = compare (reg, val)
+      //    if (REG_CC == 0)  goto label1;
+      //    if (REG_CC >= 0)  goto label2;
+      if (ival1 == ival2
+	  && (cond2 == GT || cond2 == GTU))
+	return avr_normalize_condition (cond2);
+
+      // Similar, but the input sequence is like
+      //    if (reg == val)  goto label1;
+      //    if (reg >= val)  goto label2;
+      if (ival1 == ival2
+	  && (cond2 == GE || cond2 == GEU))
+	return cond2;
+
+      // Similar, but the input sequence is like
+      //    if (reg == val)      goto label1;
+      //    if (reg >= val + 1)  goto label2;
+      if ((cond2 == GE && ival2 == 1 + ival1)
+	  || (cond2 == GEU && uval2 == 1 + uval1))
+	return cond2;
+
+      // Similar, but the input sequence is like
+      //    if (reg == val)      goto label1;
+      //    if (reg >  val - 1)  goto label2;
+      if ((cond2 == GT && ival2 == ival1 - 1)
+	  || (cond2 == GTU && uval2 == uval1 - 1))
+	return avr_normalize_condition (cond2);
+
+      /////////////////////////////////////////////////////////
+      // A sequence like
+      //    if (reg == val)      goto label1;
+      //    if (reg < 1 + val)   goto label2;
+      // can be re-written as
+      //    REG_CC = compare (reg, val)
+      //    if (REG_CC == 0)  goto label1;
+      //    if (REG_CC < 0)   goto label2;
+      if ((cond2 == LT && ival2 == 1 + ival1)
+	  || (cond2 == LTU && uval2 == 1 + uval1))
+	return cond2;
+
+      // Similar, but with an input sequence like
+      //    if (reg == val)   goto label1;
+      //    if (reg <= val)   goto label2;
+      if (ival1 == ival2
+	  && (cond2 == LE || cond2 == LEU))
+	return avr_normalize_condition (cond2);
+
+      // Similar, but with an input sequence like
+      //    if (reg == val)  goto label1;
+      //    if (reg < val)   goto label2;
+      if (ival1 == ival2
+	  && (cond2 == LT || cond2 == LTU))
+	return cond2;
+
+      // Similar, but with an input sequence like
+      //    if (reg == val)      goto label1;
+      //    if (reg <= val - 1)  goto label2;
+      if ((cond2 == LE && ival2 == ival1 - 1)
+	  || (cond2 == LEU && uval2 == uval1 - 1))
+	return avr_normalize_condition (cond2);
+
+    } // cond1 == EQ
+
+  return UNKNOWN;
+}
+
+
+/* If-else decision trees generated for switch / case may produce sequences
+   like
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+      SREG = compare (reg, 1 + val);
+	  if (SREG >= 0)  goto label2;
+
+   which can be optimized to
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+	  if (SREG >= 0)  goto label2;
+
+   The optimal place for such a pass would be directly after expand, but
+   it's not possible for a jump insn to target more than one code label.
+   Hence, run a mini pass right before split2 which introduces REG_CC.  */
+
+void
+avr_pass_ifelse::avr_rest_of_handle_ifelse (function*)
+{
+  rtx_insn *next_insn;
+
+  for (rtx_insn *insn = get_insns(); insn; insn = next_insn)
+    {
+      next_insn = next_nonnote_nondebug_insn (insn);
+
+      if (! next_insn)
+	break;
+
+      // Search for two cbranch insns.  The first one is a cbranch.
+      // Filter for "cbranch<mode>4_insn" with mode in QI, HI, PSI, SI.
+
+      if (! JUMP_P (insn))
+	continue;
+
+      int icode1 = recog_memoized (insn);
+
+      if (icode1 != CODE_FOR_cbranchqi4_insn
+	  && icode1 != CODE_FOR_cbranchhi4_insn
+	  && icode1 != CODE_FOR_cbranchpsi4_insn
+	  && icode1 != CODE_FOR_cbranchsi4_insn)
+	continue;
+
+      rtx_jump_insn *insn1 = as_a<rtx_jump_insn *> (insn);
+      rtx_jump_insn *insn2 = nullptr;
+      bool follow_label1 = false;
+
+      // Extract the operands of the first insn:
+      // $0 = comparison operator ($1, $2)
+      // $1 = reg
+      // $2 = reg or const_int
+      // $3 = code_label
+      // $4 = optional SCRATCH for HI, PSI, SI cases.
+
+      const auto &op = recog_data.operand;
+
+      extract_insn (insn1);
+      rtx xop1[5] = { op[0], op[1], op[2], op[3], op[4] };
+      int n_operands = recog_data.n_operands;
+
+      // For now, we can optimize cbranches that follow an EQ cbranch,
+      // and cbranches that follow the label of a NE cbranch.
+
+      if (GET_CODE (xop1[0]) == EQ
+	  && JUMP_P (next_insn)
+	  && recog_memoized (next_insn) == icode1)
+	{
+	  // The 2nd cbranch insn follows insn1, i.e. is located in the
+	  // fallthrough path of insn1.
+
+	  insn2 = as_a<rtx_jump_insn *> (next_insn);
+	}
+      else if (GET_CODE (xop1[0]) == NE)
+	{
+	  // insn1 might branch to a label followed by a cbranch.
+
+	  rtx target1 = JUMP_LABEL (insn1);
+	  rtx_insn *code_label1 = JUMP_LABEL_AS_INSN (insn1);
+	  rtx_insn *next = next_nonnote_nondebug_insn (code_label1);
+	  rtx_insn *barrier = prev_nonnote_nondebug_insn (code_label1);
+
+	  if (// Target label of insn1 is used exactly once and
+	      // is not a fallthru, i.e. is preceded by a barrier.
+	      LABEL_NUSES (target1) == 1
+	      && barrier
+	      && BARRIER_P (barrier)
+	      // Following the target label is a cbranch of the same kind.
+	      && next
+	      && JUMP_P (next)
+	      && recog_memoized (next) == icode1)
+	    {
+	      follow_label1 = true;
+	      insn2 = as_a<rtx_jump_insn *> (next);
+	    }
+	}
+
+      if (! insn2)
+	continue;
+
+      // Also extract operands of insn2, and filter for REG + CONST_INT
+      // comparsons against the same register.
+
+      extract_insn (insn2);
+      rtx xop2[5] = { op[0], op[1], op[2], op[3], op[4] };
+
+      if (! rtx_equal_p (xop1[1], xop2[1])
+	  || ! CONST_INT_P (xop1[2])
+	  || ! CONST_INT_P (xop2[2]))
+	continue;
+
+      machine_mode mode = GET_MODE (xop1[1]);
+      enum rtx_code code1 = GET_CODE (xop1[0]);
+      enum rtx_code code2 = GET_CODE (xop2[0]);
+
+      code2 = avr_redundant_compare (code1, xop1[2], code2, xop2[2],
+				     mode, follow_label1);
+      if (code2 == UNKNOWN)
+	continue;
+
+      //////////////////////////////////////////////////////
+      // Found a replacement.
+
+      if (dump_file)
+	{
+	  fprintf (dump_file, "\n;; Found chain of jump_insn %d and"
+		   " jump_insn %d, follow_label1=%d:\n",
+		   INSN_UID (insn1), INSN_UID (insn2), follow_label1);
+	  print_rtl_single (dump_file, PATTERN (insn1));
+	  print_rtl_single (dump_file, PATTERN (insn2));
+	}
+
+      if (! follow_label1)
+	next_insn = next_nonnote_nondebug_insn (insn2);
+
+      // Pop the new branch conditions and the new comparison.
+      // Prematurely split into compare + branch so that we can drop
+      // the 2nd comparison.  The following pass, split2, splits all
+      // insns for REG_CC, and it should still work as usual even when
+      // there are already some REG_CC insns around.
+
+      rtx xcond1 = gen_rtx_fmt_ee (code1, VOIDmode, cc_reg_rtx, const0_rtx);
+      rtx xcond2 = gen_rtx_fmt_ee (code2, VOIDmode, cc_reg_rtx, const0_rtx);
+      rtx xpat1 = gen_branch (xop1[3], xcond1);
+      rtx xpat2 = gen_branch (xop2[3], xcond2);
+      rtx xcompare = NULL_RTX;
+
+      if (mode == QImode)
+	{
+	  gcc_assert (n_operands == 4);
+	  xcompare = gen_cmpqi3 (xop1[1], xop1[2]);
+	}
+      else
+	{
+	  gcc_assert (n_operands == 5);
+	  rtx (*gen_cmp)(rtx,rtx,rtx)
+	    = mode == HImode  ? gen_gen_comparehi
+	    : mode == PSImode ? gen_gen_comparepsi
+	    : gen_gen_comparesi; // SImode
+	  xcompare = gen_cmp (xop1[1], xop1[2], xop1[4]);
+	}
+
+      // Emit that stuff.
+
+      rtx_insn *cmp = emit_insn_before (xcompare, insn1);
+      rtx_jump_insn *branch1 = emit_jump_insn_before (xpat1, insn1);
+      rtx_jump_insn *branch2 = emit_jump_insn_before (xpat2, insn2);
+
+      JUMP_LABEL (branch1) = xop1[3];
+      JUMP_LABEL (branch2) = xop2[3];
+      // delete_insn() decrements LABEL_NUSES when deleting a JUMP_INSN, but
+      // when we pop a new JUMP_INSN, do it by hand.
+      ++LABEL_NUSES (xop1[3]);
+      ++LABEL_NUSES (xop2[3]);
+
+      delete_insn (insn1);
+      delete_insn (insn2);
+
+      // As a side effect, also recog the new insns.
+      gcc_assert (valid_insn_p (cmp));
+      gcc_assert (valid_insn_p (branch1));
+      gcc_assert (valid_insn_p (branch2));
+    } // loop insns
+}
+
+
 /* Set `avr_arch' as specified by `-mmcu='.
    Return true on success.  */
 
@@ -3186,28 +3525,6 @@ avr_asm_final_postscan_insn (FILE *stream, rtx_insn *insn, rtx*, int)
 }
 
 
-/* Return 0 if undefined, 1 if always true or always false.  */
-
-int
-avr_simplify_comparison_p (machine_mode mode, RTX_CODE op, rtx x)
-{
-  unsigned int max = (mode == QImode ? 0xff :
-                      mode == HImode ? 0xffff :
-                      mode == PSImode ? 0xffffff :
-                      mode == SImode ? 0xffffffff : 0);
-  if (max && op && CONST_INT_P (x))
-    {
-      if (unsigned_condition (op) != op)
-        max >>= 1;
-
-      if (max != (INTVAL (x) & max)
-          && INTVAL (x) != 0xff)
-        return 1;
-    }
-  return 0;
-}
-
-
 /* Worker function for `FUNCTION_ARG_REGNO_P'.  */
 /* Returns nonzero if REGNO is the number of a hard
    register in which function arguments are sometimes passed.  */
@@ -5690,29 +6007,36 @@ avr_frame_pointer_required_p (void)
           || get_frame_size () > 0);
 }
 
-/* Returns the condition of compare insn INSN, or UNKNOWN.  */
+
+/* Returns the condition of the branch following INSN, where INSN is some
+   comparison.  If the next insn is not a branch or the condition code set
+   by INSN might be used by more insns than the next one, return UNKNOWN.
+   For now, just look at the next insn, which misses some opportunities like
+   following jumps.  */
 
 static RTX_CODE
 compare_condition (rtx_insn *insn)
 {
-  rtx_insn *next = next_real_insn (insn);
+  rtx set;
+  rtx_insn *next = next_real_nondebug_insn (insn);
 
-  if (next && JUMP_P (next))
+  if (next
+      && JUMP_P (next)
+      // If SREG does not die in the next insn, it is used in more than one
+      // branch.  This can happen due to pass .avr-ifelse optimizations.
+      && dead_or_set_regno_p (next, REG_CC)
+      // Branches are (set (pc) (if_then_else (COND (...)))).
+      && (set = single_set (next))
+      && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE)
     {
-      rtx pat = PATTERN (next);
-      if (GET_CODE (pat) == PARALLEL)
-        pat = XVECEXP (pat, 0, 0);
-      rtx src = SET_SRC (pat);
-
-      if (IF_THEN_ELSE == GET_CODE (src))
-        return GET_CODE (XEXP (src, 0));
+      return GET_CODE (XEXP (SET_SRC (set), 0));
     }
 
   return UNKNOWN;
 }
 
 
-/* Returns true iff INSN is a tst insn that only tests the sign.  */
+/* Returns true if INSN is a tst insn that only tests the sign.  */
 
 static bool
 compare_sign_p (rtx_insn *insn)
@@ -5722,23 +6046,95 @@ compare_sign_p (rtx_insn *insn)
 }
 
 
-/* Returns true iff the next insn is a JUMP_INSN with a condition
-   that needs to be swapped (GT, GTU, LE, LEU).  */
+/* Returns true if INSN is a compare insn with the EQ or NE condition.  */
 
 static bool
-compare_diff_p (rtx_insn *insn)
+compare_eq_p (rtx_insn *insn)
 {
   RTX_CODE cond = compare_condition (insn);
-  return (cond == GT || cond == GTU || cond == LE || cond == LEU) ? cond : 0;
+  return (cond == EQ || cond == NE);
 }
 
-/* Returns true iff INSN is a compare insn with the EQ or NE condition.  */
 
-static bool
-compare_eq_p (rtx_insn *insn)
+/* Implement `TARGET_CANONICALIZE_COMPARISON'.  */
+/* Basically tries to convert "difficult" comparisons like GT[U]
+   and LE[U] to simple ones.  Some asymmetric comparisons can be
+   transformed to EQ or NE against zero.  */
+
+static void
+avr_canonicalize_comparison (int *icode, rtx *op0, rtx *op1, bool op0_fixed)
 {
-  RTX_CODE cond = compare_condition (insn);
-  return (cond == EQ || cond == NE);
+  enum rtx_code code = (enum rtx_code) *icode;
+  machine_mode mode = GET_MODE (*op0);
+
+  bool signed_p = code == GT || code == LE;
+  bool unsigned_p = code == GTU || code == LEU;
+  bool difficult_p = signed_p || unsigned_p;
+
+  if (// Only do integers and fixed-points.
+      (! SCALAR_INT_MODE_P (mode)
+       && ! ALL_SCALAR_FIXED_POINT_MODE_P (mode))
+      // Only do comparisons against a register.
+      || ! register_operand (*op0, mode))
+    return;
+
+  // Canonicalize "difficult" reg-reg comparisons.
+
+  if (! op0_fixed
+      && difficult_p
+      && register_operand (*op1, mode))
+    {
+      std::swap (*op0, *op1);
+      *icode = (int) swap_condition (code);
+      return;
+    }
+
+  // Canonicalize comparisons against compile-time constants.
+
+  if (CONST_INT_P (*op1)
+      || CONST_FIXED_P (*op1))
+    {
+      // INT_MODE of the same size.
+      scalar_int_mode imode = int_mode_for_mode (mode).require ();
+
+      unsigned HOST_WIDE_INT mask = GET_MODE_MASK (imode);
+      unsigned HOST_WIDE_INT maxval = signed_p ? mask >> 1 : mask;
+
+      // Convert value *op1 to imode.
+      rtx xval = simplify_gen_subreg (imode, *op1, mode, 0);
+
+      // Canonicalize difficult comparisons against const.
+      if (difficult_p
+	  && (UINTVAL (xval) & mask) != maxval)
+	{
+	  // Convert *op0 > *op1  to *op0 >= 1 + *op1.
+	  // Convert *op0 <= *op1 to *op0 <  1 + *op1.
+	  xval = simplify_binary_operation (PLUS, imode, xval, const1_rtx);
+
+	  // Convert value back to its original mode.
+	  *op1 = simplify_gen_subreg (mode, xval, imode, 0);
+
+	  // Map  >  to  >=  and  <=  to  <.
+	  *icode = (int) avr_normalize_condition (code);
+
+	  return;
+	}
+
+      // Some asymmetric comparisons can be turned into EQ or NE.
+      if (code == LTU && xval == const1_rtx)
+	{
+	  *icode = (int) EQ;
+	  *op1 = CONST0_RTX (mode);
+	  return;
+	}
+
+      if (code == GEU && xval == const1_rtx)
+	{
+	  *icode = (int) NE;
+	  *op1 = CONST0_RTX (mode);
+	  return;
+	}
+    }
 }
 
 
@@ -6031,6 +6427,68 @@ avr_out_tstsi (rtx_insn *insn, rtx *op, int *plen)
 }
 
 
+/* Output a comparison of a zero- or sign-extended register against a
+   plain register.  CODE is SIGN_EXTEND or ZERO_EXTEND.  Return "".
+
+   PLEN != 0: Set *PLEN to the code length in words. Don't output anything.
+   PLEN == 0: Print instructions.  */
+
+const char*
+avr_out_cmp_ext (rtx xop[], enum rtx_code code, int *plen)
+{
+  // The smaller reg is the one that's to be extended.  Get its index as z.
+  int z = GET_MODE_SIZE (GET_MODE (xop[1])) < GET_MODE_SIZE (GET_MODE (xop[0]));
+  rtx zreg = xop[z];
+  rtx reg = xop[1 - z];
+  machine_mode mode = GET_MODE (reg);
+  machine_mode zmode = GET_MODE (zreg);
+  rtx zex;
+
+  if (plen)
+    *plen = 0;
+
+  // zex holds the extended bytes above zreg.  This is 0 for ZERO_EXTEND,
+  // and 0 or -1 for SIGN_EXTEND.
+
+  if (code == SIGN_EXTEND)
+    {
+      // Sign-extend the high-byte of zreg to tmp_reg.
+      int zmsb = GET_MODE_SIZE (zmode) - 1;
+      rtx xzmsb = simplify_gen_subreg (QImode, zreg, zmode, zmsb);
+
+      avr_asm_len ("mov __tmp_reg__,%0" CR_TAB
+		   "rol __tmp_reg__"    CR_TAB
+		   "sbc __tmp_reg__,__tmp_reg__", &xzmsb, plen, 3);
+      zex = tmp_reg_rtx;
+    }
+  else if (code == ZERO_EXTEND)
+    {
+      zex = zero_reg_rtx;
+    }
+  else
+    gcc_unreachable();
+
+  // Now output n_bytes bytes of the very comparison.
+
+  int n_bytes = GET_MODE_SIZE (mode);
+
+  avr_asm_len ("cp %0,%1", xop, plen, 1);
+
+  for (int b = 1; b < n_bytes; ++b)
+    {
+      rtx regs[2];
+      regs[1 - z] = simplify_gen_subreg (QImode, reg, mode, b);
+      regs[z] = (b < GET_MODE_SIZE (zmode)
+		 ? simplify_gen_subreg (QImode, zreg, zmode, b)
+		 : zex);
+
+      avr_asm_len ("cpc %0,%1", regs, plen, 1);
+    }
+
+  return "";
+}
+
+
 /* Generate asm equivalent for various shifts.  This only handles cases
    that are not already carefully hand-optimized in ?sh??i3_out.
 
@@ -8173,6 +8631,122 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label)
 }
 
 
+/* Output an instruction sequence for addition of REG in XOP[0] and CONST_INT
+   in XOP[1] in such a way that SREG.Z and SREG.N are set according to the
+   result.  XOP[2] might be a d-regs clobber register.  If XOP[2] is SCRATCH,
+   then the addition can be performed without a clobber reg.  Return "".
+
+   If PLEN == NULL, then output the instructions.
+   If PLEN != NULL, then set *PLEN to the length of the sequence in words. */
+
+const char*
+avr_out_plus_set_ZN (rtx *xop, int *plen)
+{
+  if (plen)
+    *plen = 0;
+
+  // Register to compare and value to compare against.
+  rtx xreg = xop[0];
+  rtx xval = xop[1];
+
+  machine_mode mode = GET_MODE (xreg);
+
+  // Number of bytes to operate on.
+  int n_bytes = GET_MODE_SIZE (mode);
+
+  if (n_bytes == 1)
+    {
+      if (INTVAL (xval) == 1)
+	return avr_asm_len ("inc %0", xop, plen, 1);
+
+      if (INTVAL (xval) == -1)
+	return avr_asm_len ("dec %0", xop, plen, 1);
+    }
+
+  if (n_bytes == 2
+      && test_hard_reg_class (ADDW_REGS, xreg)
+      && IN_RANGE (INTVAL (xval), 1, 63))
+    {
+      // Add 16-bit value in [1..63] to a w register.
+      return avr_asm_len ("adiw %0, %1", xop, plen, 1);
+    }
+
+  // Addition won't work; subtract the negative of XVAL instead.
+  xval = simplify_unary_operation (NEG, mode, xval, mode);
+
+  // Value (0..0xff) held in clobber register xop[2] or -1 if unknown.
+  int clobber_val = -1;
+
+  // [0] = Current sub-register.
+  // [1] = Current partial xval.
+  // [2] = 8-bit clobber d-register or SCRATCH.
+  rtx op[3];
+  op[2] = xop[2];
+
+  // Work byte-wise from LSB to MSB.  The lower two bytes might be
+  // SBIW'ed in one go.
+  for (int i = 0; i < n_bytes; ++i)
+    {
+      op[0] = simplify_gen_subreg (QImode, xreg, mode, i);
+
+      if (i == 0
+	  && n_bytes >= 2
+	  && test_hard_reg_class (ADDW_REGS, op[0]))
+	{
+	  op[1] = simplify_gen_subreg (HImode, xval, mode, 0);
+	  if (IN_RANGE (INTVAL (op[1]), 0, 63))
+	    {
+	      // SBIW can handle the lower 16 bits.
+	      avr_asm_len ("sbiw %0, %1", op, plen, 1);
+
+	      // Next byte has already been handled: Skip it.
+	      ++i;
+	      continue;
+	    }
+	}
+
+      op[1] = simplify_gen_subreg (QImode, xval, mode, i);
+
+      if (test_hard_reg_class (LD_REGS, op[0]))
+	{
+	  // d-regs can subtract immediates.
+	  avr_asm_len (i == 0
+		       ? "subi %0, %1"
+		       : "sbci %0, %1", op, plen, 1);
+	}
+      else
+	{
+	  int val8 = 0xff & INTVAL (op[1]);
+	  if (val8 == 0)
+	    {
+	      // Any register can subtract 0.
+	      avr_asm_len (i == 0
+			   ? "sub %0, __zero_reg__"
+			   : "sbc %0, __zero_reg__", op, plen, 1);
+	    }
+	  else
+	    {
+	      // Use d-register to hold partial xval.
+
+	      if (val8 != clobber_val)
+		{
+		  // Load partial xval to QI clobber reg and memoize for later.
+		  gcc_assert (REG_P (op[2]));
+		  avr_asm_len ("ldi %2, %1", op, plen, 1);
+		  clobber_val = val8;
+		}
+
+	      avr_asm_len (i == 0
+			   ? "sub %0, %2"
+			   : "sbc %0, %2", op, plen, 1);
+	    }
+	}
+    } // Loop bytes.
+
+  return "";
+}
+
+
 /* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile
    time constant XOP[2]:
 
@@ -9304,6 +9878,8 @@ avr_adjust_insn_length (rtx_insn *insn, int len)
     case ADJUST_LEN_TSTSI: avr_out_tstsi (insn, op, &len); break;
     case ADJUST_LEN_COMPARE: avr_out_compare (insn, op, &len); break;
     case ADJUST_LEN_COMPARE64: avr_out_compare64 (insn, op, &len); break;
+    case ADJUST_LEN_CMP_UEXT: avr_out_cmp_ext (op, ZERO_EXTEND, &len); break;
+    case ADJUST_LEN_CMP_SEXT: avr_out_cmp_ext (op, SIGN_EXTEND, &len); break;
 
     case ADJUST_LEN_LSHRQI: lshrqi3_out (insn, op, &len); break;
     case ADJUST_LEN_LSHRHI: lshrhi3_out (insn, op, &len); break;
@@ -9324,6 +9900,7 @@ avr_adjust_insn_length (rtx_insn *insn, int len)
     case ADJUST_LEN_CALL: len = AVR_HAVE_JMP_CALL ? 2 : 1; break;
 
     case ADJUST_LEN_INSERT_BITS: avr_out_insert_bits (op, &len); break;
+    case ADJUST_LEN_ADD_SET_ZN: avr_out_plus_set_ZN (op, &len); break;
 
     case ADJUST_LEN_INSV_NOTBIT:
       avr_out_insert_notbit (insn, op, NULL_RTX, &len);
@@ -10620,6 +11197,58 @@ avr_mul_highpart_cost (rtx x, int)
 }
 
 
+/* Return the expected cost of a conditional branch like
+   (set (pc)
+	(if_then_else (X)
+		      (label_ref *)
+		      (pc)))
+   where X is some comparison operator.  */
+
+static int
+avr_cbranch_cost (rtx x)
+{
+  bool difficult_p = difficult_comparison_operator (x, VOIDmode);
+
+  if (reload_completed)
+    {
+      // After reload, we basically just have plain branches.
+      return COSTS_N_INSNS (1 + difficult_p);
+    }
+
+  rtx xreg = XEXP (x, 0);
+  rtx xval = XEXP (x, 1);
+  machine_mode mode = GET_MODE (xreg);
+  if (mode == VOIDmode)
+    mode = GET_MODE (xval);
+  int size = GET_MODE_SIZE (mode);
+
+  if (GET_CODE (xreg) == ZERO_EXTEND
+      || GET_CODE (xval) == ZERO_EXTEND)
+    {
+      // *cbranch<HISI:mode>.<code><QIPSI:mode>.0/1, code = zero_extend.
+      return COSTS_N_INSNS (size + 1);
+    }
+
+  if (GET_CODE (xreg) == SIGN_EXTEND
+      || GET_CODE (xval) == SIGN_EXTEND)
+    {
+      // *cbranch<HISI:mode>.<code><QIPSI:mode>.0/1, code = sign_extend.
+      // Make it a bit cheaper than it actually is (less reg pressure).
+      return COSTS_N_INSNS (size + 1 + 1);
+    }
+
+  bool reg_p = register_operand (xreg, mode);
+  bool reg_or_0_p = reg_or_0_operand (xval, mode);
+
+  return COSTS_N_INSNS (size
+			// For the branch
+			+ 1 + difficult_p
+			// Combine might propagate constants other than zero
+			// into the 2nd operand.  Make that more expensive.
+			+ 1 * (!reg_p || !reg_or_0_p));
+}
+
+
 /* Mutually recursive subroutine of avr_rtx_cost for calculating the
    cost of an RTX operand given its context.  X is the rtx of the
    operand, MODE is its mode, and OUTER is the rtx_code of this
@@ -11512,6 +12141,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
         }
       break;
 
+    case IF_THEN_ELSE:
+      if (outer_code == SET
+	  && XEXP (x, 2) == pc_rtx
+	  && ordered_comparison_operator (XEXP (x, 0), VOIDmode))
+	{
+	  *total = avr_cbranch_cost (XEXP (x, 0));
+	  return true;
+	}
+
     default:
       break;
     }
@@ -11670,281 +12308,6 @@ avr_normalize_condition (RTX_CODE condition)
     }
 }
 
-/* Helper function for `avr_reorg'.  */
-
-static rtx
-avr_compare_pattern (rtx_insn *insn)
-{
-  rtx pattern = single_set (insn);
-
-  if (pattern
-      && NONJUMP_INSN_P (insn)
-      && REG_P (SET_DEST (pattern))
-      && REGNO (SET_DEST (pattern)) == REG_CC
-      && GET_CODE (SET_SRC (pattern)) == COMPARE)
-    {
-      machine_mode mode0 = GET_MODE (XEXP (SET_SRC (pattern), 0));
-      machine_mode mode1 = GET_MODE (XEXP (SET_SRC (pattern), 1));
-
-      /* The 64-bit comparisons have fixed operands ACC_A and ACC_B.
-         They must not be swapped, thus skip them.  */
-
-      if ((mode0 == VOIDmode || GET_MODE_SIZE (mode0) <= 4)
-          && (mode1 == VOIDmode || GET_MODE_SIZE (mode1) <= 4))
-        return pattern;
-    }
-
-  return NULL_RTX;
-}
-
-/* Helper function for `avr_reorg'.  */
-
-/* Expansion of switch/case decision trees leads to code like
-
-       REG_CC = compare (Reg, Num)
-       if (REG_CC == 0)
-         goto L1
-
-       REG_CC = compare (Reg, Num)
-       if (REG_CC > 0)
-         goto L2
-
-   The second comparison is superfluous and can be deleted.
-   The second jump condition can be transformed from a
-   "difficult" one to a "simple" one because "REG_CC > 0" and
-   "REG_CC >= 0" will have the same effect here.
-
-   This function relies on the way switch/case is being expaned
-   as binary decision tree.  For example code see PR 49903.
-
-   Return TRUE if optimization performed.
-   Return FALSE if nothing changed.
-
-   INSN1 is a comparison, i.e. avr_compare_pattern != 0.
-
-   We don't want to do this in text peephole because it is
-   tedious to work out jump offsets there and the second comparison
-   might have been transormed by `avr_reorg'.
-
-   RTL peephole won't do because peephole2 does not scan across
-   basic blocks.  */
-
-static bool
-avr_reorg_remove_redundant_compare (rtx_insn *insn1)
-{
-  rtx comp1, ifelse1, xcond1;
-  rtx_insn *branch1;
-  rtx comp2, ifelse2, xcond2;
-  rtx_insn *branch2, *insn2;
-  enum rtx_code code;
-  rtx_insn *jump;
-  rtx target, cond;
-
-  /* Look out for:  compare1 - branch1 - compare2 - branch2  */
-
-  branch1 = next_nonnote_nondebug_insn (insn1);
-  if (!branch1 || !JUMP_P (branch1))
-    return false;
-
-  insn2 = next_nonnote_nondebug_insn (branch1);
-  if (!insn2 || !avr_compare_pattern (insn2))
-    return false;
-
-  branch2 = next_nonnote_nondebug_insn (insn2);
-  if (!branch2 || !JUMP_P (branch2))
-    return false;
-
-  comp1 = avr_compare_pattern (insn1);
-  comp2 = avr_compare_pattern (insn2);
-  xcond1 = single_set (branch1);
-  xcond2 = single_set (branch2);
-
-  if (!comp1 || !comp2
-      || !rtx_equal_p (comp1, comp2)
-      || !xcond1 || SET_DEST (xcond1) != pc_rtx
-      || !xcond2 || SET_DEST (xcond2) != pc_rtx
-      || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond1))
-      || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond2)))
-    {
-      return false;
-    }
-
-  comp1 = SET_SRC (comp1);
-  ifelse1 = SET_SRC (xcond1);
-  ifelse2 = SET_SRC (xcond2);
-
-  /* comp<n> is COMPARE now and ifelse<n> is IF_THEN_ELSE.  */
-
-  if (EQ != GET_CODE (XEXP (ifelse1, 0))
-      || !REG_P (XEXP (comp1, 0))
-      || !CONST_INT_P (XEXP (comp1, 1))
-      || XEXP (ifelse1, 2) != pc_rtx
-      || XEXP (ifelse2, 2) != pc_rtx
-      || LABEL_REF != GET_CODE (XEXP (ifelse1, 1))
-      || LABEL_REF != GET_CODE (XEXP (ifelse2, 1))
-      || !COMPARISON_P (XEXP (ifelse2, 0))
-      || REG_CC != REGNO (XEXP (XEXP (ifelse1, 0), 0))
-      || REG_CC != REGNO (XEXP (XEXP (ifelse2, 0), 0))
-      || const0_rtx != XEXP (XEXP (ifelse1, 0), 1)
-      || const0_rtx != XEXP (XEXP (ifelse2, 0), 1))
-    {
-      return false;
-    }
-
-  /* We filtered the insn sequence to look like
-
-        (set (reg:CC cc)
-             (compare (reg:M N)
-                      (const_int VAL)))
-        (set (pc)
-             (if_then_else (eq (reg:CC cc)
-                               (const_int 0))
-                           (label_ref L1)
-                           (pc)))
-
-        (set (reg:CC cc)
-             (compare (reg:M N)
-                      (const_int VAL)))
-        (set (pc)
-             (if_then_else (CODE (reg:CC cc)
-                                 (const_int 0))
-                           (label_ref L2)
-                           (pc)))
-  */
-
-  code = GET_CODE (XEXP (ifelse2, 0));
-
-  /* Map GT/GTU to GE/GEU which is easier for AVR.
-     The first two instructions compare/branch on EQ
-     so we may replace the difficult
-
-        if (x == VAL)   goto L1;
-        if (x > VAL)    goto L2;
-
-     with easy
-
-         if (x == VAL)   goto L1;
-         if (x >= VAL)   goto L2;
-
-     Similarly, replace LE/LEU by LT/LTU.  */
-
-  switch (code)
-    {
-    case EQ:
-    case LT:  case LTU:
-    case GE:  case GEU:
-      break;
-
-    case LE:  case LEU:
-    case GT:  case GTU:
-      code = avr_normalize_condition (code);
-      break;
-
-    default:
-      return false;
-    }
-
-  /* Wrap the branches into UNSPECs so they won't be changed or
-     optimized in the remainder.  */
-
-  target = XEXP (XEXP (ifelse1, 1), 0);
-  cond = XEXP (ifelse1, 0);
-  jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn1);
-
-  JUMP_LABEL (jump) = JUMP_LABEL (branch1);
-
-  target = XEXP (XEXP (ifelse2, 1), 0);
-  cond = gen_rtx_fmt_ee (code, VOIDmode, cc_reg_rtx, const0_rtx);
-  jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn2);
-
-  JUMP_LABEL (jump) = JUMP_LABEL (branch2);
-
-  /* The comparisons in insn1 and insn2 are exactly the same;
-     insn2 is superfluous so delete it.  */
-
-  delete_insn (insn2);
-  delete_insn (branch1);
-  delete_insn (branch2);
-
-  return true;
-}
-
-
-/* Implement `TARGET_MACHINE_DEPENDENT_REORG'.  */
-/* Optimize conditional jumps.  */
-
-static void
-avr_reorg (void)
-{
-  rtx_insn *insn = get_insns();
-
-  for (insn = next_real_insn (insn); insn; insn = next_real_insn (insn))
-    {
-      rtx pattern = avr_compare_pattern (insn);
-
-      if (!pattern)
-        continue;
-
-      if (optimize
-          && avr_reorg_remove_redundant_compare (insn))
-        {
-          continue;
-        }
-
-      if (compare_diff_p (insn))
-	{
-          /* Now we work under compare insn with difficult branch.  */
-
-	  rtx_insn *next = next_real_insn (insn);
-          rtx pat = PATTERN (next);
-          if (GET_CODE (pat) == PARALLEL)
-            pat = XVECEXP (pat, 0, 0);
-
-          pattern = SET_SRC (pattern);
-
-          if (true_regnum (XEXP (pattern, 0)) >= 0
-              && true_regnum (XEXP (pattern, 1)) >= 0)
-            {
-              rtx x = XEXP (pattern, 0);
-              rtx src = SET_SRC (pat);
-              rtx t = XEXP (src, 0);
-              PUT_CODE (t, swap_condition (GET_CODE (t)));
-              XEXP (pattern, 0) = XEXP (pattern, 1);
-              XEXP (pattern, 1) = x;
-              INSN_CODE (next) = -1;
-            }
-          else if (true_regnum (XEXP (pattern, 0)) >= 0
-                   && XEXP (pattern, 1) == const0_rtx)
-            {
-              /* This is a tst insn, we can reverse it.  */
-              rtx src = SET_SRC (pat);
-              rtx t = XEXP (src, 0);
-
-              PUT_CODE (t, swap_condition (GET_CODE (t)));
-              XEXP (pattern, 1) = XEXP (pattern, 0);
-              XEXP (pattern, 0) = const0_rtx;
-              INSN_CODE (next) = -1;
-              INSN_CODE (insn) = -1;
-            }
-          else if (true_regnum (XEXP (pattern, 0)) >= 0
-                   && CONST_INT_P (XEXP (pattern, 1)))
-            {
-              rtx x = XEXP (pattern, 1);
-              rtx src = SET_SRC (pat);
-              rtx t = XEXP (src, 0);
-              machine_mode mode = GET_MODE (XEXP (pattern, 0));
-
-              if (avr_simplify_comparison_p (mode, GET_CODE (t), x))
-                {
-                  XEXP (pattern, 1) = gen_int_mode (INTVAL (x) + 1, mode);
-                  PUT_CODE (t, avr_normalize_condition (GET_CODE (t)));
-                  INSN_CODE (next) = -1;
-                  INSN_CODE (insn) = -1;
-                }
-            }
-        }
-    }
-}
 
 /* Returns register number for function return value.*/
 
@@ -14650,8 +15013,6 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #define TARGET_RTX_COSTS avr_rtx_costs
 #undef  TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST avr_address_cost
-#undef  TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG avr_reorg
 #undef  TARGET_FUNCTION_ARG
 #define TARGET_FUNCTION_ARG avr_function_arg
 #undef  TARGET_FUNCTION_ARG_ADVANCE
@@ -14784,6 +15145,9 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #undef  TARGET_CAN_INLINE_P
 #define TARGET_CAN_INLINE_P avr_can_inline_p
 
+#undef  TARGET_CANONICALIZE_COMPARISON
+#define TARGET_CANONICALIZE_COMPARISON avr_canonicalize_comparison
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 6858dbab4ab..de029476908 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -77,7 +77,6 @@
    UNSPEC_FMULS
    UNSPEC_FMULSU
    UNSPEC_COPYSIGN
-   UNSPEC_IDENTITY
    UNSPEC_INSERT_BITS
    UNSPEC_ROUND
    ])
@@ -165,6 +164,7 @@
    ashlsi, ashrsi, lshrsi,
    ashlpsi, ashrpsi, lshrpsi,
    insert_bits, insv_notbit, insv_notbit_0, insv_notbit_7,
+   add_set_ZN, cmp_uext, cmp_sext,
    no"
   (const_string "no"))
 
@@ -251,11 +251,23 @@
 (define_mode_iterator QIHI2 [QI HI])
 (define_mode_iterator QISI  [QI HI PSI SI])
 (define_mode_iterator QIDI  [QI HI PSI SI DI])
+(define_mode_iterator QIPSI [QI HI PSI])
 (define_mode_iterator HISI  [HI PSI SI])
 
+;; Ordered integral and fixed-point modes of specific sizes.
 (define_mode_iterator ALL1 [QI QQ UQQ])
 (define_mode_iterator ALL2 [HI HQ UHQ HA UHA])
 (define_mode_iterator ALL4 [SI SQ USQ SA USA])
+(define_mode_iterator ALL234 [HI SI PSI
+                              HQ UHQ HA UHA
+                              SQ USQ SA USA])
+
+;; Ordered signed integral and signed fixed-point modes of specific sizes.
+(define_mode_iterator ALLs1 [QI QQ])
+(define_mode_iterator ALLs2 [HI HQ HA])
+(define_mode_iterator ALLs4 [SI SQ SA])
+(define_mode_iterator ALLs234 [HI SI PSI
+                               HQ HA SQ SA])
 
 ;; All supported move-modes
 (define_mode_iterator MOVMODE [QI QQ UQQ
@@ -273,7 +285,7 @@
                                SQ USQ SA USA])
 
 ;; Define code iterators
-;; Define two incarnations so that we can build the cross product.
+;; Define two incarnations so that we can build the cartesian product.
 (define_code_iterator any_extend  [sign_extend zero_extend])
 (define_code_iterator any_extend2 [sign_extend zero_extend])
 (define_code_iterator any_extract [sign_extract zero_extract])
@@ -283,6 +295,7 @@
 (define_code_iterator bitop [xor ior and])
 (define_code_iterator xior [xor ior])
 (define_code_iterator eqne [eq ne])
+(define_code_iterator gelt [ge lt])
 
 (define_code_iterator ss_addsub [ss_plus ss_minus])
 (define_code_iterator us_addsub [us_plus us_minus])
@@ -310,6 +323,10 @@
   [(ss_minus "") (us_minus "")
    (ss_plus "%") (us_plus "%")])
 
+(define_code_attr gelt_eqne
+  [(ge "eq")
+   (lt "ne")])
+
 ;; Map RTX code to its standard insn name
 (define_code_attr code_stdname
   [(ashift   "ashl")
@@ -1530,9 +1547,8 @@
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0)
-                   (plus:HI
-                     (zero_extend:HI (match_dup 1))
-                     (zero_extend:HI (match_dup 2))))
+                   (plus:HI (zero_extend:HI (match_dup 1))
+                            (zero_extend:HI (match_dup 2))))
               (clobber (reg:CC REG_CC))])])
 
 
@@ -2153,7 +2169,8 @@
 (define_expand "mulqi3_call"
   [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
    (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
-   (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+   (parallel [(set (reg:QI 24)
+                   (mult:QI (reg:QI 24) (reg:QI 22)))
               (clobber (reg:QI 22))])
    (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
   ""
@@ -2167,12 +2184,14 @@
   "!AVR_HAVE_MUL"
   "#"
   "&& reload_completed"
-  [(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+  [(parallel [(set (reg:QI 24)
+                   (mult:QI (reg:QI 24) (reg:QI 22)))
               (clobber (reg:QI 22))
               (clobber (reg:CC REG_CC))])])
 
 (define_insn "*mulqi3_call"
-  [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+  [(set (reg:QI 24)
+        (mult:QI (reg:QI 24) (reg:QI 22)))
    (clobber (reg:QI 22))
    (clobber (reg:CC REG_CC))]
   "!AVR_HAVE_MUL && reload_completed"
@@ -2308,7 +2327,7 @@
   [(set (match_operand:PSI 0 "register_operand"                         "=r")
         (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand"  "r")
                                 (const_int 23))
-                 (match_operand:PSI 2 "register_operand"                 "0")))
+                  (match_operand:PSI 2 "register_operand"                "0")))
    (clobber (reg:CC REG_CC))]
   "reload_completed"
   "mov __tmp_reg__,%C1\;lsl __tmp_reg__
@@ -2434,7 +2453,7 @@
   [(set (match_operand:HI 0 "register_operand"                         "=r")
         (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
                  (zero_extend:HI (match_operand:QI 2 "register_operand" "a"))))
-    (clobber (reg:CC REG_CC))]
+   (clobber (reg:CC REG_CC))]
   "AVR_HAVE_MUL && reload_completed"
   "mulsu %1,%2
 	movw %0,r0
@@ -3089,7 +3108,7 @@
   [(parallel [(set (match_dup 0)
                    (mult:HI (zero_extend:HI (match_dup 1))
                             (match_dup 2)))
-               (clobber (reg:CC REG_CC))])])
+              (clobber (reg:CC REG_CC))])])
 
 (define_insn "*muluqihi3"
   [(set (match_operand:HI 0 "register_operand"                        "=&r")
@@ -3926,7 +3945,7 @@
   [(parallel [(set (match_dup 0)
                    (mult:PSI (zero_extend:PSI (match_dup 1))
                              (zero_extend:PSI (match_dup 2))))
-               (clobber (reg:CC REG_CC))])])
+              (clobber (reg:CC REG_CC))])])
 
 (define_insn "*umulqihipsi3"
   [(set (match_operand:PSI 0 "register_operand"                         "=&r")
@@ -5725,7 +5744,7 @@
 ;; "lshrha3"  "lshruha3"
 (define_insn_and_split "lshr<mode>3"
   [(set (match_operand:ALL2 0 "register_operand"                "=r,r,r,r,r,r,r")
-        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"    "0,0,0,r,0,0,0")
+        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"  "0,0,0,r,0,0,0")
                        (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
   ""
   "#"
@@ -5737,7 +5756,7 @@
 
 (define_insn "*lshr<mode>3"
   [(set (match_operand:ALL2 0 "register_operand"                "=r,r,r,r,r,r,r")
-        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"    "0,0,0,r,0,0,0")
+        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"  "0,0,0,r,0,0,0")
                        (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
    (clobber (reg:CC REG_CC))]
   "reload_completed"
@@ -6490,80 +6509,41 @@
 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
 ;; compare
 
-; Optimize negated tests into reverse compare if overflow is undefined.
-(define_insn "*negated_tstqi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (neg:QI (match_operand:QI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%0"
-  [(set_attr "length" "1")])
-
-(define_insn "*reversed_tstqi"
+;; "*swapped_tstqi"  "*swapped_tstqq"
+(define_insn "*swapped_tst<mode>"
   [(set (reg:CC REG_CC)
-        (compare:CC (const_int 0)
-                 (match_operand:QI 0 "register_operand" "r")))]
+        (compare:CC (match_operand:ALLs1 0 "const0_operand"   "Y00")
+                    (match_operand:ALLs1 1 "register_operand" "r")))]
   "reload_completed"
-  "cp __zero_reg__,%0"
-[(set_attr "length" "2")])
+  "cp __zero_reg__,%1"
+[(set_attr "length" "1")])
 
-(define_insn "*negated_tsthi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (neg:HI (match_operand:HI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%A0
-	cpc __zero_reg__,%B0"
-[(set_attr "length" "2")])
-
-;; Leave here the clobber used by the cmphi pattern for simplicity, even
-;; though it is unused, because this pattern is synthesized by avr_reorg.
-(define_insn "*reversed_tsthi"
+
+;; "*swapped_tsthi"  "*swapped_tsthq"  "*swapped_tstha"
+(define_insn "*swapped_tst<mode>"
   [(set (reg:CC REG_CC)
-        (compare:CC (const_int 0)
-                 (match_operand:HI 0 "register_operand" "r")))
-   (clobber (match_scratch:QI 1 "=X"))]
+        (compare:CC (match_operand:ALLs2 0 "const0_operand"   "Y00")
+                    (match_operand:ALLs2 1 "register_operand" "r")))]
   "reload_completed"
-  "cp __zero_reg__,%A0
-	cpc __zero_reg__,%B0"
-[(set_attr "length" "2")])
+  "cp __zero_reg__,%A1
+	cpc __zero_reg__,%B1"
+  [(set_attr "length" "2")])
 
-(define_insn "*negated_tstpsi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (neg:PSI (match_operand:PSI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
-  [(set_attr "length" "3")])
 
-(define_insn "*reversed_tstpsi"
+(define_insn "*swapped_tstpsi"
   [(set (reg:CC REG_CC)
         (compare:CC (const_int 0)
-                 (match_operand:PSI 0 "register_operand" "r")))
-   (clobber (match_scratch:QI 1 "=X"))]
+                    (match_operand:PSI 0 "register_operand" "r")))]
   "reload_completed"
   "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
   [(set_attr "length" "3")])
 
-(define_insn "*negated_tstsi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (neg:SI (match_operand:SI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%A0
-	cpc __zero_reg__,%B0
-	cpc __zero_reg__,%C0
-	cpc __zero_reg__,%D0"
-  [(set_attr "length" "4")])
 
-;; "*reversed_tstsi"
-;; "*reversed_tstsq" "*reversed_tstusq"
-;; "*reversed_tstsa" "*reversed_tstusa"
-(define_insn "*reversed_tst<mode>"
+;; "*swapped_tstsi"  "*swapped_tstsq"  "*swapped_tstsa"
+(define_insn "*swapped_tst<mode>"
   [(set (reg:CC REG_CC)
-        (compare:CC (match_operand:ALL4 0 "const0_operand"   "Y00")
-                 (match_operand:ALL4 1 "register_operand" "r")))
-   (clobber (match_scratch:QI 2 "=X"))]
+        (compare:CC (match_operand:ALLs4 0 "const0_operand"   "Y00")
+                    (match_operand:ALLs4 1 "register_operand" "r")))]
   "reload_completed"
   "cp __zero_reg__,%A1
 	cpc __zero_reg__,%B1
@@ -6577,38 +6557,40 @@
 (define_insn "cmp<mode>3"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL1 0 "register_operand"  "r  ,r,d")
-                 (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))]
+                    (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))]
   "reload_completed"
   "@
-	tst %0
+	cp %0, __zero_reg__
 	cp %0,%1
 	cpi %0,lo8(%1)"
   [(set_attr "length" "1,1,1")])
 
-(define_insn "*cmpqi_sign_extend"
-  [(set (reg:CC REG_CC)
-        (compare:CC (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
-                 (match_operand:HI 1 "s8_operand"                       "n")))]
-  "reload_completed"
-  "cpi %0,lo8(%1)"
-  [(set_attr "length" "1")])
-
 
-(define_insn "*cmphi.zero-extend.0"
+;; May be generated by "*cbranch<HISI:mode>.<code><QIPSI:mode>.0/1".
+(define_insn "*cmp<HISI:mode>.<code><QIPSI:mode>.0"
   [(set (reg:CC REG_CC)
-        (compare:CC (zero_extend:HI (match_operand:QI 0 "register_operand" "r"))
-                 (match_operand:HI 1 "register_operand" "r")))]
-  "reload_completed"
-  "cp %0,%A1\;cpc __zero_reg__,%B1"
-  [(set_attr "length" "2")])
+        (compare:CC (any_extend:HISI (match_operand:QIPSI 0 "register_operand" "r"))
+                    (match_operand:HISI 1 "register_operand" "r")))]
+  "reload_completed
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  {
+    return avr_out_cmp_ext (operands, <CODE>, nullptr);
+  }
+  [(set_attr "adjust_len" "cmp_<extend_su>ext")])
 
-(define_insn "*cmphi.zero-extend.1"
+;; Swapped version of the above.
+;; May be generated by "*cbranch<HISI:mode>.<code><QIPSI:mode>.0/1".
+(define_insn "*cmp<HISI:mode>.<code><QIPSI:mode>.1"
   [(set (reg:CC REG_CC)
-        (compare:CC (match_operand:HI 0 "register_operand" "r")
-                 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))))]
-  "reload_completed"
-  "cp %A0,%1\;cpc %B0,__zero_reg__"
-  [(set_attr "length" "2")])
+        (compare:CC (match_operand:HISI 0 "register_operand" "r")
+                    (any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r"))))]
+  "reload_completed
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  {
+    return avr_out_cmp_ext (operands, <CODE>, nullptr);
+  }
+  [(set_attr "adjust_len" "cmp_<extend_su>ext")])
+
 
 ;; "cmphi3"
 ;; "cmphq3" "cmpuhq3"
@@ -6616,8 +6598,8 @@
 (define_insn "cmp<mode>3"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL2 0 "register_operand"  "!w  ,r  ,r,d ,r  ,d,r")
-                 (match_operand:ALL2 1 "nonmemory_operand"  "Y00,Y00,r,s ,s  ,M,n Ynn")))
-   (clobber (match_scratch:QI 2                            "=X  ,X  ,X,&d,&d ,X,&d"))]
+                    (match_operand:ALL2 1 "nonmemory_operand"  "Y00,Y00,r,s ,s  ,M,n Ynn")))
+   (clobber (match_scratch:QI 2                               "=X  ,X  ,X,&d,&d ,X,&d"))]
   "reload_completed"
   {
     switch (which_alternative)
@@ -6644,14 +6626,14 @@
 
     return avr_out_compare (insn, operands, NULL);
   }
-  [(set_attr "length" "1,2,2,3,4,2,4")
+  [(set_attr "length" "2,2,2,3,4,2,4")
    (set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")])
 
 (define_insn "*cmppsi"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:PSI 0 "register_operand"  "r,r,d ,r  ,d,r")
-                 (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s  ,M,n")))
-   (clobber (match_scratch:QI 2                          "=X,X,&d,&d ,X,&d"))]
+                    (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s  ,M,n")))
+   (clobber (match_scratch:QI 2                             "=X,X,&d,&d ,X,&d"))]
   "reload_completed"
   {
     switch (which_alternative)
@@ -6682,8 +6664,8 @@
 (define_insn "*cmp<mode>"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL4 0 "register_operand"  "r  ,r ,d,r ,r")
-                 (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")))
-   (clobber (match_scratch:QI 2                           "=X  ,X ,X,&d,&d"))]
+                    (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")))
+   (clobber (match_scratch:QI 2                              "=X  ,X ,X,&d,&d"))]
   "reload_completed"
   {
     if (0 == which_alternative)
@@ -6697,6 +6679,13 @@
    (set_attr "adjust_len" "tstsi,*,compare,compare,compare")])
 
 
+;; A helper for avr_pass_ifelse::avr_rest_of_handle_ifelse().
+(define_expand "gen_compare<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_operand:HISI 0 "register_operand")
+                               (match_operand:HISI 1 "const_int_operand")))
+              (clobber (match_operand:QI 2 "scratch_operand"))])])
+
 ;; ----------------------------------------------------------------------
 ;; JUMP INSTRUCTIONS
 ;; ----------------------------------------------------------------------
@@ -6705,53 +6694,67 @@
 (define_expand "cbranch<mode>4"
   [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
-                        [(match_operand:ALL1 1 "register_operand" "")
-                         (match_operand:ALL1 2 "nonmemory_operand" "")])
-         (label_ref (match_operand 3 "" ""))
-         (pc)))])
+                        [(match_operand:ALL1 1 "register_operand")
+                         (match_operand:ALL1 2 "nonmemory_operand")])
+                      (label_ref (match_operand 3))
+                      (pc)))]
+  ""
+  {
+    int icode = (int) GET_CODE (operands[0]);
+
+    targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false);
+    PUT_CODE (operands[0], (enum rtx_code) icode);
+  })
 
 (define_expand "cbranch<mode>4"
   [(parallel
      [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:ORDERED234 1 "register_operand" "")
-                (match_operand:ORDERED234 2 "nonmemory_operand" "")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-      (clobber (match_scratch:QI 4 ""))])])
-
-;; "*cbranchqi4"
-;; "*cbranchqq4"  "*cbranchuqq4"
-(define_insn_and_split "*cbranch<mode>4"
+           (if_then_else (match_operator 0 "ordered_comparison_operator"
+                           [(match_operand:ALL234 1 "register_operand")
+                            (match_operand:ALL234 2 "nonmemory_operand")])
+                         (label_ref (match_operand 3))
+                         (pc)))
+      (clobber (match_scratch:QI 4))])]
+  ""
+  {
+    int icode = (int) GET_CODE (operands[0]);
+
+    targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false);
+    PUT_CODE (operands[0], (enum rtx_code) icode);
+  })
+
+
+;; "cbranchqi4_insn"
+;; "cbranchqq4_insn"  "cbranchuqq4_insn"
+(define_insn_and_split "cbranch<mode>4_insn"
   [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
-                        [(match_operand:ALL1 1 "register_operand" "r  ,r,d")
+                        [(match_operand:ALL1 1 "register_operand"  "r  ,r,d")
                          (match_operand:ALL1 2 "nonmemory_operand" "Y00,r,i")])
-         (label_ref (match_operand 3 "" ""))
-         (pc)))]
+                      (label_ref (match_operand 3))
+                      (pc)))]
    ""
    "#"
    "reload_completed"
    [(set (reg:CC REG_CC)
-                    (compare:CC (match_dup 1) (match_dup 2)))
+         (compare:CC (match_dup 1) (match_dup 2)))
     (set (pc)
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
 
-;; "*cbranchsi4"  "*cbranchsq4"  "*cbranchusq4"  "*cbranchsa4"  "*cbranchusa4"
-(define_insn_and_split "*cbranch<mode>4"
+;; "cbranchsi4_insn"
+;; "cbranchsq4_insn"  "cbranchusq4_insn"  "cbranchsa4_insn"  "cbranchusa4_insn"
+(define_insn_and_split "cbranch<mode>4_insn"
   [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:ALL4 1 "register_operand" "r  ,r ,d,r ,r")
-                (match_operand:ALL4 2 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-   (clobber (match_scratch:QI 4 "=X  ,X ,X,&d,&d"))]
+        (if_then_else
+         (match_operator 0 "ordered_comparison_operator"
+           [(match_operand:ALL4 1 "register_operand"  "r  ,r,d,r ,r")
+            (match_operand:ALL4 2 "nonmemory_operand" "Y00,r,M,M ,n Ynn")])
+         (label_ref (match_operand 3))
+         (pc)))
+   (clobber (match_scratch:QI 4                      "=X  ,X,X,&d,&d"))]
    ""
    "#"
    "reload_completed"
@@ -6762,19 +6765,18 @@
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
 
-;; "*cbranchpsi4"
-(define_insn_and_split "*cbranchpsi4"
+;; "cbranchpsi4_insn"
+(define_insn_and_split "cbranchpsi4_insn"
   [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:PSI 1 "register_operand" "r,r,d ,r  ,d,r")
-                (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s  ,M,n")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-   (clobber (match_scratch:QI 4 "=X,X,&d,&d ,X,&d"))]
+        (if_then_else
+         (match_operator 0 "ordered_comparison_operator"
+           [(match_operand:PSI 1 "register_operand"  "r,r,d ,r ,d,r")
+            (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")])
+         (label_ref (match_operand 3))
+         (pc)))
+   (clobber (match_scratch:QI 4                     "=X,X,&d,&d,X,&d"))]
    ""
    "#"
    "reload_completed"
@@ -6785,19 +6787,19 @@
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
 
-;; "*cbranchhi4"  "*cbranchhq4"  "*cbranchuhq4"  "*cbranchha4"  "*cbranchuha4"
-(define_insn_and_split "*cbranch<mode>4"
+;; "cbranchhi4_insn"
+;; "cbranchhq4_insn"  "cbranchuhq4_insn"  "cbranchha4_insn"  "cbranchuha4_insn"
+(define_insn_and_split "cbranch<mode>4_insn"
   [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:ALL2 1 "register_operand" "!w  ,r  ,r,d ,r  ,d,r")
-                (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s  ,M,n Ynn")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-   (clobber (match_scratch:QI 4 "=X  ,X  ,X,&d,&d ,X,&d"))]
+        (if_then_else
+         (match_operator 0 "ordered_comparison_operator"
+           [(match_operand:ALL2 1 "register_operand" "!w  ,r  ,r,d ,r ,d,r")
+            (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")])
+         (label_ref (match_operand 3))
+         (pc)))
+   (clobber (match_scratch:QI 4                      "=X  ,X  ,X,&d,&d,X,&d"))]
    ""
    "#"
    "reload_completed"
@@ -6808,8 +6810,71 @@
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
+
+;; Combiner pattern to compare sign- or zero-extended register against
+;; a wider register, like comparing uint8_t against uint16_t.
+(define_insn_and_split "*cbranch<HISI:mode>.<code><QIPSI:mode>.0"
+  [(set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r"))
+                         (match_operand:HISI 2 "register_operand" "r")])
+                      (label_ref (match_operand 3))
+                      (pc)))]
+  "optimize
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  "#"
+  "&& reload_completed"
+  [; "*cmp<HISI:mode>.<code><QIPSI:mode>.0"
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 1)
+                    (match_dup 2)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 3))
+                      (pc)))]
+  {
+    operands[1] = gen_rtx_<CODE> (<HISI:MODE>mode, operands[1]);
+    if (difficult_comparison_operator (operands[0], VOIDmode))
+      {
+        PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0])));
+        std::swap (operands[1], operands[2]);
+      }
+  })
+
+;; Same combiner pattern, but with swapped operands.
+(define_insn_and_split "*cbranch<HISI:mode>.<code><QIPSI:mode>.0"
+  [(set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(match_operand:HISI 1 "register_operand" "r")
+                         (any_extend:HISI (match_operand:QIPSI 2 "register_operand" "r"))])
+                      (label_ref (match_operand 3))
+                      (pc)))]
+  "optimize
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  "#"
+  "&& reload_completed"
+  [; "*cmp<HISI:mode>.<code><QIPSI:mode>.0"
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 1)
+                    (match_dup 2)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 3))
+                      (pc)))]
+  {
+    operands[2] = gen_rtx_<CODE> (<HISI:MODE>mode, operands[2]);
+    if (difficult_comparison_operator (operands[0], VOIDmode))
+      {
+        PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0])));
+        std::swap (operands[1], operands[2]);
+      }
+  })
+
 
 ;; Test a single bit in a QI/HI/SImode register.
 ;; Combine will create zero extract patterns for single bit tests.
@@ -6883,14 +6948,11 @@
   "#"
   "&& reload_completed"
   [(parallel [(set (pc)
-                   (if_then_else
-                   (match_op_dup 0
-                                 [(and:QISI
-                                   (match_dup 1)
-                                   (match_dup 2))
-                                  (const_int 0)])
-                   (label_ref (match_dup 3))
-                   (pc)))
+                   (if_then_else (match_op_dup 0 [(and:QISI (match_dup 1)
+                                                            (match_dup 2))
+                                                  (const_int 0)])
+                                 (label_ref (match_dup 3))
+                                 (pc)))
               (clobber (reg:CC REG_CC))])])
 
 (define_insn "*sbrx_and_branch<mode>"
@@ -6919,163 +6981,77 @@
                                     (const_int 2)
                                     (const_int 4))))])
 
-;; Convert sign tests to bit 7/15/31 tests that match the above insns.
-(define_peephole2
-  [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
-                       (const_int 0)))
-   (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
-                                                           (const_int 1)
-                                                           (const_int 7))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
 
-(define_peephole2
-  [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
-                       (const_int 0)))
-   (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
-                                                           (const_int 1)
-                                                           (const_int 7))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:HI 2 ""))])
-   (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:HI 2 ""))])
-   (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
+;; Convert sign tests to bit 7 tests that match the above insns.
+(define_peephole2 ; "*sbrx_branch<mode>"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_operand:ALLs1 0 "register_operand")
+                    (match_operand:ALLs1 1 "const0_operand")))
+   (set (pc)
+        (if_then_else (gelt (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(parallel [(set (pc)
+                   (if_then_else (<gelt_eqne> (zero_extract:HI (match_dup 0)
+                                                               (const_int 1)
+                                                               (match_dup 1))
+                                              (const_int 0))
+                                 (label_ref (match_dup 2))
+                                 (pc)))
               (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
+  {
+    operands[0] = avr_to_int_mode (operands[0]);
+    operands[1] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
+  })
 
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:SI 2 ""))])
-   (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
+;; Convert sign tests to bit 15/23/31 tests that match the above insns.
+(define_peephole2 ; "*sbrx_branch<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_operand:ALLs234 0 "register_operand")
+                               (match_operand:ALLs234 1 "const0_operand")))
+              (clobber (match_operand:QI 3 "scratch_operand"))])
+   (set (pc)
+        (if_then_else (gelt (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(parallel [(set (pc)
+                   (if_then_else (<gelt_eqne> (zero_extract:HI (match_dup 0)
+                                                               (const_int 1)
+                                                               (match_dup 1))
+                                              (const_int 0))
+                                 (label_ref (match_dup 2))
+                                 (pc)))
               (clobber (reg:CC REG_CC))])]
-  "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
+  {
+    operands[0] = avr_to_int_mode (operands[0]);
+    operands[1] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
+  })
 
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:SI 2 ""))])
-   (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
 
 ;; ************************************************************************
 ;; Implementation of conditional jumps here.
 ;;  Compare with 0 (test) jumps
 ;; ************************************************************************
 
-(define_insn_and_split "branch"
+(define_insn "branch"
   [(set (pc)
         (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (label_ref (match_operand 0 "" ""))
+                        [(reg:CC REG_CC)
+                         (const_int 0)])
+                      (label_ref (match_operand 0))
                       (pc)))]
   "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                                 (label_ref (match_dup 0))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*branch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
   {
     return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
   }
   [(set_attr "type" "branch")])
 
 
-;; Same as above but wrap SET_SRC so that this branch won't be transformed
-;; or optimized in the remainder.
-
-(define_insn "branch_unspec"
-  [(set (pc)
-        (unspec [(if_then_else (match_operator 1 "simple_comparison_operator"
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                               (label_ref (match_operand 0 "" ""))
-                               (pc))
-                 ] UNSPEC_IDENTITY))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
-  {
-    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
-  }
-  [(set_attr "type" "branch")])
-
-;; ****************************************************************
-;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
-;; Convert them all to proper jumps.
-;; ****************************************************************/
-
-(define_insn_and_split "difficult_branch"
+(define_insn "difficult_branch"
   [(set (pc)
         (if_then_else (match_operator 1 "difficult_comparison_operator"
                         [(reg:CC REG_CC)
@@ -7083,95 +7059,11 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                   [(reg:CC REG_CC)
-                                    (const_int 0)])
-                                 (label_ref (match_dup 0))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*difficult_branch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "difficult_comparison_operator"
-                        [(reg:CC REG_CC)
-                         (const_int 0)])
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
   {
     return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
   }
   [(set_attr "type" "branch1")])
 
-;; revers branch
-
-(define_insn_and_split "rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                                 (pc)
-                                 (label_ref (match_dup 0))))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
-  {
-    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
-  }
-  [(set_attr "type" "branch1")])
-
-(define_insn_and_split "difficult_rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "difficult_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                                 (pc)
-                                 (label_ref (match_dup 0))))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*difficult_rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "difficult_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
-  {
-    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
-  }
-  [(set_attr "type" "branch")])
 
 ;; **************************************************************************
 ;; Unconditional and other jump instructions.
@@ -7697,15 +7589,14 @@
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
-              (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+                               (const_int -1)))
+              (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))])
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7741,15 +7632,14 @@
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
+                               (const_int -1)))
               (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7783,15 +7673,14 @@
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
-              (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+                               (const_int -1)))
+              (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))])
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7825,15 +7714,14 @@
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
+                               (const_int -1)))
               (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7863,14 +7751,13 @@
               (clobber (reg:CC REG_CC))])
    (set (reg:CC REG_CC)
         (compare:CC (match_dup 0)
-                 (const_int -1)))
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 1 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+                    (const_int -1)))
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 1))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7896,14 +7783,14 @@
 (define_peephole ; "*cpse.eq"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL1 1 "register_operand" "r,r")
-                 (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00")))
-   (parallel [(set (pc)
-                   (if_then_else (eq (reg:CC REG_CC)
-                                     (const_int 0))
-                                 (label_ref (match_operand 0 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  "jump_over_one_insn_p (insn, operands[0])"
+                    (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00")))
+   (set (pc)
+        (if_then_else (eq (reg:CC REG_CC)
+                          (const_int 0))
+                      (label_ref (match_operand 0))
+                      (pc)))]
+  "jump_over_one_insn_p (insn, operands[0])
+   && dead_or_set_regno_p (insn, REG_CC)"
   "@
 	cpse %1,%2
 	cpse %1,__zero_reg__")
@@ -7931,16 +7818,16 @@
 
 (define_peephole ; "*cpse.ne"
   [(set (reg:CC REG_CC)
-        (compare:CC (match_operand:ALL1 1 "register_operand" "")
-                 (match_operand:ALL1 2 "reg_or_0_operand" "")))
-   (parallel [(set (pc)
-                   (if_then_else (ne (reg:CC REG_CC)
-                                     (const_int 0))
-                                 (label_ref (match_operand 0 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  "!AVR_HAVE_JMP_CALL
-   || !TARGET_SKIP_BUG"
+        (compare:CC (match_operand:ALL1 1 "register_operand")
+                    (match_operand:ALL1 2 "reg_or_0_operand")))
+   (set (pc)
+        (if_then_else (ne (reg:CC REG_CC)
+                          (const_int 0))
+                      (label_ref (match_operand 0))
+                      (pc)))]
+  "(!AVR_HAVE_JMP_CALL
+    || !TARGET_SKIP_BUG)
+   && dead_or_set_regno_p (insn, REG_CC)"
   {
     if (operands[2] == CONST0_RTX (<MODE>mode))
       operands[2] = zero_reg_rtx;
@@ -8135,7 +8022,7 @@
                                 (const_int 1)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (reg:CC REG_CC))])])
 
@@ -8167,7 +8054,7 @@
                                 (const_int 2)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (reg:CC REG_CC))])]
   ""
@@ -8204,7 +8091,7 @@
                                 (const_int 3)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (match_dup 3))
               (clobber (match_dup 4))
@@ -8247,7 +8134,7 @@
                                 (const_int 4)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (match_dup 3))
               (clobber (match_dup 4))
@@ -9534,6 +9421,258 @@
               (clobber (reg:CC REG_CC))])])
 
 
+;; Try optimize decrement-and-branch.  When we have an addition followed
+;; by a comparison of the result against zero, we can output the addition
+;; in such a way that SREG.N and SREG.Z are set according to the result.
+
+;; { -1, +1 } for QImode, otherwise the empty set.
+(define_mode_attr p1m1 [(QI "N P")
+                        (HI "Yxx") (PSI "Yxx") (SI "Yxx")])
+
+;; FIXME: reload1.cc::do_output_reload() does not support output reloads
+;; for JUMP_INSNs, hence letting combine doing decrement-and-branch like
+;; the following might run into ICE.  Doing reloads by hand is too painful...
+;
+; (define_insn_and_split "*add.for.eqne.<mode>.cbranch"
+;   [(set (pc)
+;         (if_then_else (eqne (match_operand:QISI 1 "register_operand"  "0")
+;                             (match_operand:QISI 2 "const_int_operand" "n"))
+;                       (label_ref (match_operand 4))
+;                       (pc)))
+;    (set (match_operand:QISI 0 "register_operand" "=r")
+;         (plus:QISI (match_dup 1)
+;                    (match_operand:QISI 3 "const_int_operand" "n")))]
+;   ;; No clobber for now as combine might not have one handy.
+;   ;; We pop a scatch in split1.
+;   "!reload_completed
+;    && const0_rtx == simplify_binary_operation (PLUS, <MODE>mode,
+;                                                operands[2], operands[3])"
+;   { gcc_unreachable(); }
+;   "&& 1"
+;   [(parallel [(set (pc)
+;                    (if_then_else (eqne (match_dup 1)
+;                                        (match_dup 2))
+;                                  (label_ref (match_dup 4))
+;                                  (pc)))
+;               (set (match_dup 0)
+;                    (plus:QISI (match_dup 1)
+;                               (match_dup 3)))
+;               (clobber (scratch:QI))])])
+;
+;; ...Hence, stick with RTL peepholes for now.  Unfortunately, there is no
+;; canonical form, and if reload shuffles registers around, we might miss
+;; opportunities to match a decrement-and-branch.
+;; doloop_end doesn't reload either, so doloop_end also won't work.
+
+(define_expand "gen_add_for_<code>_<mode>"
+  ; "*add.for.eqne.<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (plus:QISI (match_operand:QISI 0 "register_operand")
+                                          (match_operand:QISI 1 "const_int_operand"))
+                               (const_int 0)))
+              (set (match_dup 0)
+                   (plus:QISI (match_dup 0)
+                              (match_dup 1)))
+              (clobber (match_operand:QI 3))])
+   ; "branch"
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_dup 2))
+                      (pc)))])
+
+
+;; 1/3: A version without clobber: d-reg or 8-bit adds +/-1.
+(define_peephole2
+  [(parallel [(set (match_operand:QISI 0 "register_operand")
+                   (plus:QISI (match_dup 0)
+                              (match_operand:QISI 1 "const_int_operand")))
+              (clobber (reg:CC REG_CC))])
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 0)
+                    (const_int 0)))
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (3, REG_CC)
+   && (d_register_operand (operands[0], <MODE>mode)
+       || (<MODE>mode == QImode
+           && (INTVAL (operands[1]) == 1
+               || INTVAL (operands[1]) == -1)))"
+  [(scratch)]
+  {
+    emit (gen_gen_add_for_<code>_<mode> (operands[0], operands[1], operands[2],
+          gen_rtx_SCRATCH (QImode)));
+    DONE;
+  })
+
+;; 2/3: A version with clobber from the insn.
+(define_peephole2
+  [(parallel [(set (match_operand:QISI 0 "register_operand")
+                   (plus:QISI (match_dup 0)
+                              (match_operand:QISI 1 "const_int_operand")))
+              (clobber (match_operand:QI 3 "scratch_or_d_register_operand"))
+              (clobber (reg:CC REG_CC))])
+   (parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_dup 0)
+                               (const_int 0)))
+              (clobber (match_operand:QI 4 "scratch_or_d_register_operand"))])
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (3, REG_CC)"
+  [(scratch)]
+  {
+    rtx scratch = REG_P (operands[3]) ? operands[3] : operands[4];
+
+    // We need either a d-register or a scratch register to clobber.
+    if (! REG_P (scratch)
+        && ! d_register_operand (operands[0], <MODE>mode)
+        && ! (QImode == <MODE>mode
+              && (INTVAL (operands[1]) == 1
+                  || INTVAL (operands[1]) == -1)))
+      {
+        FAIL;
+      }
+    emit (gen_gen_add_for_<code>_<mode> (operands[0], operands[1], operands[2],
+          scratch));
+    DONE;
+  })
+
+;; 3/3 A version with a clobber from peephole2.
+(define_peephole2
+  [(match_scratch:QI 3 "d")
+   (parallel [(set (match_operand:QISI 0 "register_operand")
+                   (plus:QISI (match_dup 0)
+                              (match_operand:QISI 1 "const_int_operand")))
+              (clobber (reg:CC REG_CC))])
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 0)
+                    (const_int 0)))
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (3, REG_CC)"
+  [(scratch)]
+  {
+    emit (gen_gen_add_for_<code>_<mode> (operands[0], operands[1], operands[2],
+          operands[3]));
+    DONE;
+  })
+
+;; Result of the above three peepholes is an addition that also
+;; performs an EQ or NE comparison (of the result) against zero.
+;; FIXME: Using (match_dup 0) instead of operands[3/4] makes rnregs
+;; barf in regrename.cc::merge_overlapping_regs().  For now, use the
+;; fix from PR50788: Constrain as "0".
+(define_insn "*add.for.eqne.<mode>"
+  [(set (reg:CC REG_CC)
+        (compare:CC
+         (plus:QISI (match_operand:QISI 3 "register_operand"  "0,0     ,0")
+                    (match_operand:QISI 1 "const_int_operand" "n,<p1m1>,n"))
+         (const_int 0)))
+   (set (match_operand:QISI 0 "register_operand"             "=d,*r    ,r")
+        (plus:QISI (match_operand:QISI 4 "register_operand"   "0,0     ,0")
+                   (match_dup 1)))
+   (clobber (match_scratch:QI 2                              "=X,X     ,&d"))]
+  "reload_completed"
+  {
+    return avr_out_plus_set_ZN (operands, nullptr);
+  }
+  [(set_attr "adjust_len" "add_set_ZN")])
+
+
+;; Swapping both comparison and branch condition.  This can turn difficult
+;; branches to easy ones.  And in some cases, a comparison against one can
+;; be turned into a comparison against zero.
+
+(define_peephole2 ; "*swapped_tst<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_operand:ALLs234 1 "register_operand")
+                               (match_operand:ALLs234 2 "const_operand")))
+              (clobber (match_operand:QI 3 "scratch_operand"))])
+   (set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(reg:CC REG_CC)
+                         (const_int 0)])
+                      (label_ref (match_operand 4))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_dup 2)
+                    (match_dup 1)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 4))
+                      (pc)))]
+  {
+    rtx xval = avr_to_int_mode (operands[2]);
+    enum rtx_code code = GET_CODE (operands[0]);
+
+    if (code == GT && xval == const0_rtx)
+      code = LT;
+    else if (code == GE && xval == const1_rtx)
+      code = LT;
+    else if (code == LE && xval == const0_rtx)
+      code = GE;
+    else if (code == LT && xval == const1_rtx)
+      code = GE;
+    else
+      FAIL;
+
+    operands[2] = CONST0_RTX (<MODE>mode);
+    PUT_CODE (operands[0], code);
+  })
+
+;; Same, but for 8-bit modes which have no scratch reg.
+(define_peephole2 ; "*swapped_tst<mode>"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_operand:ALLs1 1 "register_operand")
+                    (match_operand:ALLs1 2 "const_operand")))
+   (set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(reg:CC REG_CC)
+                         (const_int 0)])
+                      (label_ref (match_operand 4))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_dup 2)
+                    (match_dup 1)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 4))
+                      (pc)))]
+  {
+    rtx xval = avr_to_int_mode (operands[2]);
+    enum rtx_code code = GET_CODE (operands[0]);
+
+    if (code == GT && xval == const0_rtx)
+      code = LT;
+    else if (code == GE && xval == const1_rtx)
+      code = LT;
+    else if (code == LE && xval == const0_rtx)
+      code = GE;
+    else if (code == LT && xval == const1_rtx)
+      code = GE;
+    else
+      FAIL;
+
+    operands[2] = CONST0_RTX (<MODE>mode);
+    PUT_CODE (operands[0], code);
+  })
+
+
 (define_expand "extzv"
   [(set (match_operand:QI 0 "register_operand" "")
         (zero_extract:QI (match_operand:QI 1 "register_operand"  "")
diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md
index 57397d1469b..3ce2108d6ce 100644
--- a/gcc/config/avr/constraints.md
+++ b/gcc/config/avr/constraints.md
@@ -245,6 +245,11 @@
 	    (match_test "INTVAL (avr_to_int_mode (op)) == -2"))
        (match_test "satisfies_constraint_Cm2 (op)")))
 
+;; Constraint that's the empty set.  Useful with mode and code iterators.
+(define_constraint "Yxx"
+  "A constraints that is always false"
+  (match_test "false"))
+
 (define_constraint "Yx2"
   "Fixed-point or integer constant not in the range @minus{}2 @dots{} 2"
   (and (ior (match_code "const_int")
diff --git a/gcc/config/avr/predicates.md b/gcc/config/avr/predicates.md
index c7f417d405c..1d63f7ee67c 100644
--- a/gcc/config/avr/predicates.md
+++ b/gcc/config/avr/predicates.md
@@ -27,6 +27,11 @@
   (and (match_code "reg")
        (match_test "REGNO (op) >= 16 && REGNO (op) <= 31")))
 
+(define_predicate "scratch_or_d_register_operand"
+  (ior (match_operand 0 "d_register_operand")
+       (and (match_code ("scratch"))
+            (match_operand 0 "scratch_operand"))))
+
 (define_predicate "even_register_operand"
   (and (match_code "reg")
        (and (match_test "REGNO (op) <= 31")
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c b/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c
new file mode 100644
index 00000000000..9030db00fde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-options { -std=c99 } } */
+
+typedef _Bool bool;
+typedef __UINT8_TYPE__ uint8_t;
+
+static inline __attribute__((__always_inline__))
+bool func1a (bool p1, uint8_t p2)
+{
+  if (p1)
+    return p2 <= 8;
+  return p2 <= 2;
+}
+
+__attribute__((__noinline__, __noclone__))
+bool func1b (bool p1, uint8_t p2)
+{
+  return func1a (p1, p2);
+}
+
+static inline __attribute__((__always_inline__))
+bool func2a (bool p1, unsigned p2)
+{
+  if (p1)
+    return p2 <= 8;
+  return p2 <= 2;
+}
+
+__attribute__((__noinline__, __noclone__))
+bool func2b (bool p1, unsigned p2)
+{
+  return func2a (p1, p2);
+}
+
+void test1 (void)
+{
+  if (func1a (0, 1) != func1b (0, 1)) __builtin_abort();
+  if (func1a (0, 2) != func1b (0, 2)) __builtin_abort();
+  if (func1a (0, 3) != func1b (0, 3)) __builtin_abort();
+
+  if (func1a (1, 7) != func1b (1, 7)) __builtin_abort();
+  if (func1a (1, 8) != func1b (1, 8)) __builtin_abort();
+  if (func1a (1, 9) != func1b (1, 9)) __builtin_abort();
+}
+
+void test2 (void)
+{
+  if (func2a (0, 1) != func2b (0, 1)) __builtin_abort();
+  if (func2a (0, 2) != func2b (0, 2)) __builtin_abort();
+  if (func2a (0, 3) != func2b (0, 3)) __builtin_abort();
+
+  if (func2a (1, 7) != func2b (1, 7)) __builtin_abort();
+  if (func2a (1, 8) != func2b (1, 8)) __builtin_abort();
+  if (func2a (1, 9) != func2b (1, 9)) __builtin_abort();
+}
+
+int main (void)
+{
+  test1();
+  test2();
+
+  __builtin_exit (0);
+}
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c b/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c
new file mode 100644
index 00000000000..386dc322afa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+
+typedef __UINT8_TYPE__ uint8_t;
+
+#define AI static __inline__ __attribute__((__always_inline__))
+#define NI __attribute__((__noinline__,__noclone__))
+
+AI uint8_t func1_eq (uint8_t c, unsigned x)
+{
+  if (x == c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_ne (uint8_t c, unsigned x)
+{
+  if (x != c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_ltu (uint8_t c, unsigned x)
+{
+  if (x < c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_leu (uint8_t c, unsigned x)
+{
+  if (x <= c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_gtu (uint8_t c, unsigned x)
+{
+  if (x > c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_geu (uint8_t c, unsigned x)
+{
+  if (x >= c)
+    return 1;
+  return 0;
+}
+
+NI uint8_t func2_eq (uint8_t c, unsigned x) { return func1_eq (c, x); }
+NI uint8_t func2_ne (uint8_t c, unsigned x) { return func1_ne (c, x); }
+NI uint8_t func2_ltu (uint8_t c, unsigned x) { return func1_ltu (c, x); }
+NI uint8_t func2_leu (uint8_t c, unsigned x) { return func1_leu (c, x); }
+NI uint8_t func2_gtu (uint8_t c, unsigned x) { return func1_gtu (c, x); }
+NI uint8_t func2_geu (uint8_t c, unsigned x) { return func1_geu (c, x); }
+
+AI void test4 (uint8_t c, unsigned x)
+{
+  if (func2_eq (c, x) != func1_eq (c, x)) __builtin_abort();
+  if (func2_ne (c, x) != func1_ne (c, x)) __builtin_abort();
+  if (func2_ltu (c, x) != func1_ltu (c, x)) __builtin_abort();
+  if (func2_leu (c, x) != func1_leu (c, x)) __builtin_abort();
+  if (func2_gtu (c, x) != func1_gtu (c, x)) __builtin_abort();
+  if (func2_geu (c, x) != func1_geu (c, x)) __builtin_abort();
+}
+
+int main (void)
+{
+  test4 (127, 127);
+  test4 (127, 128);
+  test4 (128, 127);
+
+  test4 (0x42, 0x142);
+  test4 (0x0, 0x100);
+  test4 (0x0, 0x0);
+  test4 (0x0, 0x1);
+
+  __builtin_exit (0);
+}

commit a7739a073a8620495c87acfa37596aaea3ca5e04
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 11 02:20:46 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 72c11de8ed6..719200c9ac2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,46 @@
+2023-06-10  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/109650
+	PR target/92729
+	Backport from 2023-05-10 master r14-1688.
+	* config/avr/avr-passes.def (avr_pass_ifelse): Insert new pass.
+	* config/avr/avr.cc (avr_pass_ifelse): New RTL pass.
+	(avr_pass_data_ifelse): New pass_data for it.
+	(make_avr_pass_ifelse, avr_redundant_compare, avr_cbranch_cost)
+	(avr_canonicalize_comparison, avr_out_plus_set_ZN)
+	(avr_out_cmp_ext): New functions.
+	(compare_condtition): Make sure REG_CC dies in the branch insn.
+	(avr_rtx_costs_1): Add computation of cbranch costs.
+	(avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_ZN, ADJUST_LEN_CMP_ZEXT]:
+	[ADJUST_LEN_CMP_SEXT]Handle them.
+	(TARGET_CANONICALIZE_COMPARISON): New define.
+	(avr_simplify_comparison_p, compare_diff_p, avr_compare_pattern)
+	(avr_reorg_remove_redundant_compare, avr_reorg): Remove functions.
+	(TARGET_MACHINE_DEPENDENT_REORG): Remove define.
+	* config/avr/avr-protos.h (avr_simplify_comparison_p): Remove proto.
+	(make_avr_pass_ifelse, avr_out_plus_set_ZN, cc_reg_rtx)
+	(avr_out_cmp_zext): New Protos
+	* config/avr/avr.md (branch, difficult_branch): Don't split insns.
+	(*cbranchhi.zero-extend.0", *cbranchhi.zero-extend.1")
+	(*swapped_tst<mode>, *add.for.eqne.<mode>): New insns.
+	(*cbranch<mode>4): Rename to cbranch<mode>4_insn.
+	(define_peephole): Add dead_or_set_regno_p(insn,REG_CC) as needed.
+	(define_deephole2): Add peep2_regno_dead_p(*,REG_CC) as needed.
+	Add new RTL peepholes for decrement-and-branch and *swapped_tst<mode>.
+	Rework signtest-and-branch peepholes for *sbrx_branch<mode>.
+	(adjust_len) [add_set_ZN, cmp_zext]: New.
+	(QIPSI): New mode iterator.
+	(ALLs1, ALLs2, ALLs4, ALLs234): New mode iterators.
+	(gelt): New code iterator.
+	(gelt_eqne): New code attribute.
+	(rvbranch, *rvbranch, difficult_rvbranch, *difficult_rvbranch)
+	(branch_unspec, *negated_tst<mode>, *reversed_tst<mode>)
+	(*cmpqi_sign_extend): Remove insns.
+	(define_c_enum "unspec") [UNSPEC_IDENTITY]: Remove.
+	* config/avr/avr-dimode.md (cbranch<mode>4): Canonicalize comparisons.
+	* config/avr/predicates.md (scratch_or_d_register_operand): New.
+	* config/avr/constraints.md (Yxx): New constraint.
+
 2023-06-09  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index dc88eb6d69e..0f040c2846a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230610
+20230611
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a32ee4887cb..0dda7aba760 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2023-06-10  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/109650
+	Backport from 2023-05-10 master r14-1688.
+	* gcc.target/avr/torture/pr109650-1.c: New test.
+	* gcc.target/avr/torture/pr109650-2.c: New test.
+
 2023-06-09  Iain Sandoe  <iain@sandoe.co.uk>
 
 	Backported from master:

commit 94c8326f42707301a37070c280447e148d5322c2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 12 02:20:55 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0f040c2846a..995c0c1e119 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230611
+20230612

commit d5f72834a4817b180625a540b99f5c1934c2e0b8
Author: Richard Biener <rguenther@suse.de>
Date:   Mon Jun 12 10:17:26 2023

    middle-end/110200 - genmatch force-leaf and convert interaction
    
    The following fixes code GENERIC generation for (convert! ...)
    which currently generates
    
      if (TREE_TYPE (_o1[0]) != type)
        _r1 = fold_build1_loc (loc, NOP_EXPR, type, _o1[0]);
        if (EXPR_P (_r1))
          goto next_after_fail867;
      else
        _r1 = _o1[0];
    
    where obviously braces are missing.
    
            PR middle-end/110200
            * genmatch.cc (expr::gen_transform): Put braces around
            the if arm for the (convert ...) short-cut.
    
    (cherry picked from commit 820d1aec89c43dbbc70d3d0b888201878388454c)

diff --git a/gcc/genmatch.cc b/gcc/genmatch.cc
index 5b25fc8da86..80c64d88928 100644
--- a/gcc/genmatch.cc
+++ b/gcc/genmatch.cc
@@ -2548,7 +2548,8 @@ expr::gen_transform (FILE *f, int indent, const char *dest, bool gimple,
 	{
 	  fprintf_indent (f, indent, "if (TREE_TYPE (_o%d[0]) != %s)\n",
 			  depth, type);
-	  indent += 2;
+	  fprintf_indent (f, indent + 2, "{\n");
+	  indent += 4;
 	}
       if (opr->kind == id_base::CODE)
 	fprintf_indent (f, indent, "_r%d = fold_build%d_loc (loc, %s, %s",
@@ -2571,7 +2572,8 @@ expr::gen_transform (FILE *f, int indent, const char *dest, bool gimple,
 	}
       if (*opr == CONVERT_EXPR)
 	{
-	  indent -= 2;
+	  fprintf_indent (f, indent - 2, "}\n");
+	  indent -= 4;
 	  fprintf_indent (f, indent, "else\n");
 	  fprintf_indent (f, indent, "  _r%d = _o%d[0];\n", depth, depth);
 	}

commit 0ec543abd50ce7b54de0bfcc11bcda2d690e0947
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 13 02:21:18 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 719200c9ac2..84bb6cf6b85 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2023-06-12  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-06-12  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/110200
+	* genmatch.cc (expr::gen_transform): Put braces around
+	the if arm for the (convert ...) short-cut.
+
 2023-06-10  Georg-Johann Lay  <avr@gjlay.de>
 
 	PR target/109650
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 995c0c1e119..5180e2ea7c6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230612
+20230613

commit ac3a1795043a30535cb5e00016abf4fe71e364af
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 14 02:20:50 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5180e2ea7c6..60b8c2b92b7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230613
+20230614

commit a58bda46377ba74df9ba2bf0a22111c74a1abae8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 15 02:20:49 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 60b8c2b92b7..3f6866a6b54 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230614
+20230615

commit ddec24e5abe99033c8d6bbe544b4c2b35a0232f2
Author: Lulu Cheng <chenglulu@loongson.cn>
Date:   Wed Jun 7 04:21:58 2023

    LoongArch: Avoid non-returning indirect jumps through $ra [PR110136]
    
    Micro-architecture unconditionally treats a "jr $ra" as "return from subroutine",
    hence doing "jr $ra" would interfere with both subroutine return prediction and
    the more general indirect branch prediction.
    
    Therefore, a problem like PR110136 can cause a significant increase in branch error
    prediction rate and affect performance. The same problem exists with "indirect_jump".
    
    gcc/ChangeLog:
    
            PR target/110136
            * config/loongarch/loongarch.md: Modify the register constraints for template
            "jumptable" and "indirect_jump" from "r" to "e".
    
    Co-authored-by: Andrew Pinski <apinski@marvell.com>
    
    (cherry picked from commit 5430c86e71927492399129f3df80824c6c334ddf)

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 8f8412fba84..a64142c7a78 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -2622,6 +2622,10 @@
 }
   [(set_attr "type" "branch")])
 
+;; Micro-architecture unconditionally treats a "jr $ra" as "return from subroutine",
+;; non-returning indirect jumps through $ra would interfere with both subroutine
+;; return prediction and the more general indirect branch prediction.
+
 (define_expand "indirect_jump"
   [(set (pc) (match_operand 0 "register_operand"))]
   ""
@@ -2632,7 +2636,7 @@
 })
 
 (define_insn "@indirect_jump<mode>"
-  [(set (pc) (match_operand:P 0 "register_operand" "r"))]
+  [(set (pc) (match_operand:P 0 "register_operand" "e"))]
   ""
   "jr\t%0"
   [(set_attr "type" "jump")
@@ -2655,7 +2659,7 @@
 
 (define_insn "@tablejump<mode>"
   [(set (pc)
-	(match_operand:P 0 "register_operand" "r"))
+	(match_operand:P 0 "register_operand" "e"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "jr\t%0"

commit e8ee5a0b00dc7a7c25dd3264e9007f440457a791
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 07:57:19 2022

    aarch64: testsuite: disable PIE for aapcs64 tests [PR70150]
    
    If GCC is built with --enable-default-pie, a lot of aapcs64 tests fail
    because relocation unsupported in PIE is used.
    
    gcc/testsuite/ChangeLog:
    
            PR testsuite/70150
            * gcc.target/aarch64/aapcs64/aapcs64.exp (additional_flags):
            Add -fno-pie -no-pie.
    
    (cherry picked from commit f30f04b1fbd4b4e13a7535fad8e698c7b24db9b8)

diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp b/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp
index 3e652c483c7..eb7c531615c 100644
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp
@@ -27,7 +27,7 @@ if { ![istarget aarch64*-*-*] } then {
 
 torture-init
 set-torture-options $C_TORTURE_OPTIONS
-set additional_flags "-W -Wall -Wno-abi"
+set additional_flags "-W -Wall -Wno-abi -fno-pie -no-pie"
 
 # Test parameter passing.  This uses abitest.S which relies on weak
 # symbols.

commit b2d29f2622c215201cb415565ab4f18b738ca35c
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 08:28:44 2022

    aarch64: testsuite: disable PIE for tests with large code model [PR70150]
    
    These tests set large code model with -mcmodel=large or target pragma for
    AArch64.  But if GCC is configured with --enable-default-pie, it triggers
    "sorry: unimplemented: code model large with -fpic".  Disable PIE to make
    avoid the issue.
    
    gcc/testsuite/ChangeLog:
    
            PR testsuite/70150
            * gcc.dg/tls/pr78796.c (dg-additional-options): Add -fno-pie
            -no-pie for aarch64-*-*.
            * gcc.target/aarch64/pr63304_1.c (dg-options): Add -fno-pie.
            * gcc.target/aarch64/pr70120-2.c (dg-options): Add -fno-pie.
            * gcc.target/aarch64/pr78733.c (dg-options): Add -fno-pie.
            * gcc.target/aarch64/pr79041-2.c (dg-options): Add -fno-pie.
            * gcc.target/aarch64/pr94530.c (dg-options): Add -fno-pie.
            * gcc.target/aarch64/pr94577.c (dg-options): Add -fno-pie.
            * gcc.target/aarch64/reload-valid-spoff.c (dg-options): Add
            -fno-pie.
    
    (cherry picked from commit a1ccb4583dfaa267648110aa7da7275acc3000f8)

diff --git a/gcc/testsuite/gcc.dg/tls/pr78796.c b/gcc/testsuite/gcc.dg/tls/pr78796.c
index 038e5366e41..96f87d47ba4 100644
--- a/gcc/testsuite/gcc.dg/tls/pr78796.c
+++ b/gcc/testsuite/gcc.dg/tls/pr78796.c
@@ -1,7 +1,7 @@
 /* PR target/78796 */
 /* { dg-do run } */
 /* { dg-options "-O2" } */
-/* { dg-additional-options "-mcmodel=large" { target aarch64-*-* } } */
+/* { dg-additional-options "-mcmodel=large -fno-pie -no-pie" { target aarch64-*-* } } */
 /* { dg-require-effective-target tls_runtime } */
 /* { dg-add-options tls } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c
index 9f1ed947806..5d519d817cc 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c
@@ -1,6 +1,6 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target lp64 } */
-/* { dg-options "-O1 --save-temps" } */
+/* { dg-options "-O1 --save-temps -fno-pie" } */
 #pragma GCC push_options
 #pragma GCC target ("+nothing+simd,cmodel=small")
 
diff --git a/gcc/testsuite/gcc.target/aarch64/pr70120-2.c b/gcc/testsuite/gcc.target/aarch64/pr70120-2.c
index 663bf2ed147..8f5cdc93fe3 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr70120-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr70120-2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target lp64 } */
-/* { dg-options "-Og -freorder-functions -g3 -mcmodel=large" } */
+/* { dg-options "-Og -freorder-functions -g3 -mcmodel=large -fno-pie" } */
 
 typedef short v32u16 __attribute__ ((vector_size (32)));
 typedef int v32u32 __attribute__ ((vector_size (32)));
diff --git a/gcc/testsuite/gcc.target/aarch64/pr78733.c b/gcc/testsuite/gcc.target/aarch64/pr78733.c
index 4695b5c1b2b..8556ef3f371 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr78733.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr78733.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */
+/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads -fno-pie" } */
 /* { dg-require-effective-target lp64 } */
 /* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* }  { "-fpic" } { "" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c
index 4695b5c1b2b..8556ef3f371 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */
+/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads -fno-pie" } */
 /* { dg-require-effective-target lp64 } */
 /* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* }  { "-fpic" } { "" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/pr94530.c b/gcc/testsuite/gcc.target/aarch64/pr94530.c
index 2797d116dcf..5dfdbe3311d 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr94530.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr94530.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target lp64 } */
-/* { dg-options "-Os -mcpu=falkor -mpc-relative-literal-loads -mcmodel=large" } */
+/* { dg-options "-Os -mcpu=falkor -mpc-relative-literal-loads -mcmodel=large -fno-pie" } */
 
 extern void bar(const char *);
 
diff --git a/gcc/testsuite/gcc.target/aarch64/pr94577.c b/gcc/testsuite/gcc.target/aarch64/pr94577.c
index 6f2d3612c26..d51799fb0bb 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr94577.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr94577.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mcmodel=large -mabi=ilp32" } */
+/* { dg-options "-mcmodel=large -mabi=ilp32 -fno-pie" } */
 
 void
 foo ()
diff --git a/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c b/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
index 7b1982abb61..37e00ac9aa1 100644
--- a/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
+++ b/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mcmodel=large -fno-builtin" }  */
+/* { dg-options "-O2 -mcmodel=large -fno-builtin -fno-pie" }  */
 /* { dg-skip-if "-mcmodel=large -fPIC not currently supported" { aarch64-*-* }  { "-fPIC" } { "" } } */
 
 typedef long unsigned int size_t;

commit 5a21f78294624dd7166e1a25a57c805a759dc0d2
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 08:45:17 2022

    aarch64: testsuite: disable PIE for fuse_adrp_add_1.c [PR70150]
    
    In PIE, symbol "fixed_regs" is addressed via GOT.  It will break the
    scan-assembler pattern and cause test failure with --enable-default-pie.
    
    gcc/testsuite/ChangeLog:
    
            PR testsuite/70150
            * gcc.target/aarch64/fuse_adrp_add_1.c (dg-options): Add
            -fno-pie.
    
    (cherry picked from commit 7e8a3dbbb26f66ce8ea60be48962022b5fb2ef55)

diff --git a/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c b/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c
index e49aadaa639..d66fe3a4b23 100644
--- a/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target aarch64_small } */
-/* { dg-options "-O3 -mcpu=cortex-a57" } */
+/* { dg-options "-O3 -mcpu=cortex-a57 -fno-pie" } */
 
 enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS,
                  XGRF_REGS, ALL_REGS, LIM_REG_CLASSES };

commit 9391ed101cb401e5fda6b39978bd16b263931526
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 08:20:12 2022

    aarch64: testsuite: disable stack protector for sve-pcs tests
    
    If GCC is configured with --enable-default-ssp, the stack protector can
    make many sve-pcs tests fail.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp (sve_flags):
            Add -fno-stack-protector.
    
    (cherry picked from commit edb336cc575a82cfc2a883e4c3453c36267482c1)

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp b/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp
index 83786733f35..76f5fd4ffd8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp
@@ -37,11 +37,12 @@ if ![info exists DEFAULT_CFLAGS] then {
 # Initialize `dg'.
 dg-init
 
-# Force SVE if we're not testing it already.
+# Force SVE if we're not testing it already.  And, disable stack protector
+# to avoid test failures with --enable-default-ssp.
 if { [check_effective_target_aarch64_sve] } {
-    set sve_flags ""
+    set sve_flags "-fno-stack-protector"
 } else {
-    set sve_flags "-march=armv8.2-a+sve"
+    set sve_flags "-march=armv8.2-a+sve -fno-stack-protector"
 }
 
 # Main loop.

commit df39444ecfb2eaca1b24a52c6fc54e7ef70d5e98
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 08:23:10 2022

    aarch64: testsuite: disable stack protector for pr103147-10 tests
    
    Stack protector influence code generation and cause function body checks
    fail.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/pr103147-10.c (dg-options): Add
            -fno-stack-protector.
            * g++.target/aarch64/pr103147-10.C: Likewise.
    
    (cherry picked from commit 2fa31207ea602d48b8f69982e0bde1d143e54ecb)

diff --git a/gcc/testsuite/g++.target/aarch64/pr103147-10.C b/gcc/testsuite/g++.target/aarch64/pr103147-10.C
index 914fdf9c692..e12771533f7 100644
--- a/gcc/testsuite/g++.target/aarch64/pr103147-10.C
+++ b/gcc/testsuite/g++.target/aarch64/pr103147-10.C
@@ -1,4 +1,4 @@
-/* { dg-options "-O2 -fpack-struct -mstrict-align" } */
+/* { dg-options "-O2 -fpack-struct -mstrict-align -fno-stack-protector" } */
 /* { dg-final { check-function-bodies "**" "" "" } } */
 
 #include <arm_neon.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c
index b2c34e4155d..57942bfd10a 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2 -fpack-struct -mstrict-align" } */
+/* { dg-options "-O2 -fpack-struct -mstrict-align -fno-stack-protector" } */
 /* { dg-final { check-function-bodies "**" "" "" } } */
 
 #include <arm_neon.h>

commit 868371e673de074565b5340f81049eb61d070b07
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 08:38:31 2022

    aarch64: testsuite: disable stack protector for auto-init-7.c
    
    The test scans for "const_int 0" in the RTL dump, but stack protector
    can produce more "const_int 0".  To avoid a failure with
    --enable-default-ssp, disable stack protector for this.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/auto-init-7.c (dg-options): Add
            -fno-stack-protector.
    
    (cherry picked from commit 4c59cfc4a4da579d60bfd82404e3ff51c72aca79)

diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-7.c b/gcc/testsuite/gcc.target/aarch64/auto-init-7.c
index ac27fbe92f4..fde6e568532 100644
--- a/gcc/testsuite/gcc.target/aarch64/auto-init-7.c
+++ b/gcc/testsuite/gcc.target/aarch64/auto-init-7.c
@@ -1,6 +1,6 @@
 /* Verify zero initialization for array, union, and structure type automatic variables.  */
 /* { dg-do compile } */
-/* { dg-options "-ftrivial-auto-var-init=zero -fdump-rtl-expand" } */
+/* { dg-options "-ftrivial-auto-var-init=zero -fdump-rtl-expand -fno-stack-protector" } */
 
 struct S
 {

commit cd0b91e1dfa6a60e7e7981207c43695f0ba422a1
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 08:50:03 2022

    aarch64: testsuite: disable stack protector for pr104005.c
    
    Storing stack guarding variable need one stp instruction, breaking the
    scan-assembler-not pattern in the test.  Disable stack protector to
    avoid a test failure with --enable-default-ssp.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/pr104005.c (dg-options): Add
            -fno-stack-protector.
    
    (cherry picked from commit 5937cfb981debb2aeb72a1ed255fc3ed5a5835c4)

diff --git a/gcc/testsuite/gcc.target/aarch64/pr104005.c b/gcc/testsuite/gcc.target/aarch64/pr104005.c
index 09dd81910eb..9f1ef2dc308 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr104005.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr104005.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2 -funroll-loops" } */
+/* { dg-options "-O2 -funroll-loops -fno-stack-protector" } */
 
 typedef int v2 __attribute__((vector_size(8)));
 

commit b93928b36dbc88efd55cbefecb3a26302fc099db
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Sat Sep 24 09:16:57 2022

    aarch64: testsuite: disable stack protector for tests relying on stack offset
    
    Stack protector needs a guard value on the stack and change the stack
    layout.  So we need to disable it for those tests, to avoid test failure
    with --enable-default-ssp.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/shrink_wrap_1.c (dg-options): Add
            -fno-stack-protector.
            * gcc.target/aarch64/stack-check-cfa-1.c (dg-options): Add
            -fno-stack-protector.
            * gcc.target/aarch64/stack-check-cfa-2.c (dg-options): Add
            -fno-stack-protector.
            * gcc.target/aarch64/test_frame_17.c (dg-options): Add
            -fno-stack-protector.
    
    (cherry picked from commit 59a72acbccf4c81a04b4d09760fc8b16992de106)

diff --git a/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c b/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c
index ab7cd74ec3b..067220c04a0 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { aarch64*-*-* } } } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fno-stack-protector" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*
diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c
index 6885894a97e..412a9ed1aab 100644
--- a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables" } */
+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables -fno-stack-protector" } */
 /* { dg-require-effective-target supports_stack_clash_protection } */
 
 #define SIZE 128*1024
diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c
index 5796a53be06..e440569a078 100644
--- a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables" } */
+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables -fno-stack-protector" } */
 /* { dg-require-effective-target supports_stack_clash_protection } */
 
 #define SIZE 1280*1024 + 512
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_17.c b/gcc/testsuite/gcc.target/aarch64/test_frame_17.c
index 44f13291128..5d432ad0854 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_17.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fno-stack-protector" } */
 
 /* Test reuse of stack adjustment temporaries.  */
 

commit 43e8299b7181c4828eab984259a8d76edfec0bd2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 16 02:20:59 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 84bb6cf6b85..c1c682ab1b0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-15  Lulu Cheng  <chenglulu@loongson.cn>
+
+	Backported from master:
+	2023-06-15  Lulu Cheng  <chenglulu@loongson.cn>
+		    Andrew Pinski  <apinski@marvell.com>
+
+	PR target/110136
+	* config/loongarch/loongarch.md: Modify the register constraints for template
+	"jumptable" and "indirect_jump" from "r" to "e".
+
 2023-06-12  Richard Biener  <rguenther@suse.de>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3f6866a6b54..d8455aa601e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230615
+20230616
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0dda7aba760..49de2f769ee 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,85 @@
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	* gcc.target/aarch64/shrink_wrap_1.c (dg-options): Add
+	-fno-stack-protector.
+	* gcc.target/aarch64/stack-check-cfa-1.c (dg-options): Add
+	-fno-stack-protector.
+	* gcc.target/aarch64/stack-check-cfa-2.c (dg-options): Add
+	-fno-stack-protector.
+	* gcc.target/aarch64/test_frame_17.c (dg-options): Add
+	-fno-stack-protector.
+
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	* gcc.target/aarch64/pr104005.c (dg-options): Add
+	-fno-stack-protector.
+
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	* gcc.target/aarch64/auto-init-7.c (dg-options): Add
+	-fno-stack-protector.
+
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	* gcc.target/aarch64/pr103147-10.c (dg-options): Add
+	-fno-stack-protector.
+	* g++.target/aarch64/pr103147-10.C: Likewise.
+
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	* gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp (sve_flags):
+	Add -fno-stack-protector.
+
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	PR testsuite/70150
+	* gcc.target/aarch64/fuse_adrp_add_1.c (dg-options): Add
+	-fno-pie.
+
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	PR testsuite/70150
+	* gcc.dg/tls/pr78796.c (dg-additional-options): Add -fno-pie
+	-no-pie for aarch64-*-*.
+	* gcc.target/aarch64/pr63304_1.c (dg-options): Add -fno-pie.
+	* gcc.target/aarch64/pr70120-2.c (dg-options): Add -fno-pie.
+	* gcc.target/aarch64/pr78733.c (dg-options): Add -fno-pie.
+	* gcc.target/aarch64/pr79041-2.c (dg-options): Add -fno-pie.
+	* gcc.target/aarch64/pr94530.c (dg-options): Add -fno-pie.
+	* gcc.target/aarch64/pr94577.c (dg-options): Add -fno-pie.
+	* gcc.target/aarch64/reload-valid-spoff.c (dg-options): Add
+	-fno-pie.
+
+2023-06-15  Xi Ruoyao  <xry111@xry111.site>
+
+	Backported from master:
+	2023-03-07  Xi Ruoyao  <xry111@xry111.site>
+
+	PR testsuite/70150
+	* gcc.target/aarch64/aapcs64/aapcs64.exp (additional_flags):
+	Add -fno-pie -no-pie.
+
 2023-06-10  Georg-Johann Lay  <avr@gjlay.de>
 
 	PR target/109650

commit 5a8af9c5a03edad65917b5789ffae6b3d90cf35a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 17 02:21:07 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d8455aa601e..e65e8e48ae9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230616
+20230617

commit 4dd85040abf0c26aa5395f7bd44fbf4207b5e252
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 18 02:20:33 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e65e8e48ae9..8f07d5bff0e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230617
+20230618

commit 782bb52886eb05f83d9f86898f27027d49060c39
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 19 02:20:34 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 8f07d5bff0e..b45a5ceabca 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230618
+20230619

commit 372d0240a07cd765cd45e47ef9bf4c401a2ee8dd
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 20 02:21:04 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b45a5ceabca..414ba4c8afb 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230619
+20230620

commit 90e1030d4c6d981c2293d89db6d1d57c057ad61d
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Mon Jun 12 08:07:52 2023

    rs6000: Don't use TFmode for 128 bits fp constant in toc [PR110011]
    
    As PR110011 shows, when encoding 128 bits fp constant into
    toc, we adopts REAL_VALUE_TO_TARGET_LONG_DOUBLE which is
    to find the first float mode with LONG_DOUBLE_TYPE_SIZE
    bits of precision, it would be TFmode here.  But the 128
    bits fp constant can be with mode IFmode or KFmode, which
    doesn't necessarily have the same underlying float format
    as the one of TFmode, like this PR exposes, with option
    -mabi=ibmlongdouble TFmode has ibm_extended_format while
    KFmode has ieee_quad_format, mixing up the formats (the
    encoding/decoding ways) would cause unexpected results.
    
    This patch is to make it use constant's own mode instead
    of TFmode for real_to_target call.
    
            PR target/110011
    
    gcc/ChangeLog:
    
            * config/rs6000/rs6000.cc (output_toc): Use the mode of the 128-bit
            floating constant itself for real_to_target call.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/powerpc/pr110011.c: New test.
    
    (cherry picked from commit 388809f2afde874180da0669c669e241037eeba0)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2623e4bd6e9..dd263fbf9fe 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -17117,7 +17117,7 @@ output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
       if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
 	REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
       else
-	REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
+	real_to_target (k, CONST_DOUBLE_REAL_VALUE (x), GET_MODE (x));
 
       if (TARGET_64BIT)
 	{
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110011.c b/gcc/testsuite/gcc.target/powerpc/pr110011.c
new file mode 100644
index 00000000000..5b04d3e298a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110011.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target float128_runtime } */
+/* Force long double to be with IBM format here, to verify
+   _Float128 constant still uses its own format (IEEE) for
+   encoding rather than IBM format.  */
+/* { dg-options "-mfp-in-toc -mabi=ibmlongdouble" } */
+/* { dg-add-options float128 } */
+
+#define MPFR_FLOAT128_MAX 0x1.ffffffffffffffffffffffffffffp+16383f128
+
+__attribute__ ((noipa))
+_Float128 f128_max ()
+{
+  return MPFR_FLOAT128_MAX;
+}
+
+typedef union
+{
+  int w[4];
+  _Float128 f128;
+} U;
+
+int main ()
+{
+
+  U umax;
+  umax.f128 = f128_max ();
+  /* ieee float128 max:
+     7ffeffff ffffffff ffffffff ffffffff.  */
+  if (umax.w[1] != 0xffffffff || umax.w[2] != 0xffffffff)
+    __builtin_abort ();
+#ifdef __LITTLE_ENDIAN__
+  if (umax.w[0] != 0xffffffff || umax.w[3] != 0x7ffeffff)
+    __builtin_abort ();
+#else
+  if (umax.w[3] != 0xffffffff || umax.w[0] != 0x7ffeffff)
+    __builtin_abort ();
+#endif
+
+  return 0;
+}
+

commit 31d88c795a0eb05df5a0684c34ec74116cce133f
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Mon Jun 12 08:08:22 2023

    rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]
    
    As PR109932 shows, builtins __builtin_{un,}pack_vector_int128
    should be guarded under vsx rather than power7, as their
    corresponding bif patterns have the conditions TARGET_VSX
    and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode).  This patch is to
    move __builtin_{un,}pack_vector_int128 to stanza vsx to ensure
    their supports.
    
            PR target/109932
    
    gcc/ChangeLog:
    
            * config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
            __builtin_unpack_vector_int128): Move from stanza power7 to vsx.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/powerpc/pr109932-1.c: New test.
            * gcc.target/powerpc/pr109932-2.c: New test.
    
    (cherry picked from commit ff83d1b47aadcdaf80a4fda84b0dc00bb2cd3641)

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index dd39a27be40..d2c0565dc62 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2008,6 +2008,13 @@
   const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
     XXSPLTD_V2DI vsx_xxspltd_v2di {}
 
+  const vsq __builtin_pack_vector_int128 (unsigned long long, \
+                                          unsigned long long);
+    PACK_V1TI packv1ti {}
+
+  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+    UNPACK_V1TI unpackv1ti {}
+
 
 ; Power7 builtins (ISA 2.06).
 [power7]
@@ -2029,16 +2036,9 @@
   const unsigned int __builtin_divweu (unsigned int, unsigned int);
     DIVWEU diveu_si {}
 
-  const vsq __builtin_pack_vector_int128 (unsigned long long, \
-                                          unsigned long long);
-    PACK_V1TI packv1ti {}
-
   void __builtin_ppc_speculation_barrier ();
     SPECBARR speculation_barrier {}
 
-  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
-    UNPACK_V1TI unpackv1ti {}
-
 
 ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
 [power7-64]
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
new file mode 100644
index 00000000000..3e3f9eaa65e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
new file mode 100644
index 00000000000..3e3f9eaa65e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+

commit 4591c2c8a6b15ca99ba049d84e0e694f12db4f60
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Tue Jun 13 10:04:54 2023

    testsuite: Check int128 effective target for pr109932-{1,2}.c [PR110230]
    
    This patch is to make newly added test cases pr109932-{1,2}.c
    check int128 effective target to avoid unsupported type error
    on 32-bit.  I did hit this failure during testing and fixed
    it, but made a stupid mistake not updating the local formatted
    patch which was actually out of date.
    
            PR testsuite/110230
            PR target/109932
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/powerpc/pr109932-1.c: Adjust with int128 effective target.
            * gcc.target/powerpc/pr109932-2.c: Ditto.
    
    (cherry picked from commit 16eb9d69079d769b2aa2c07ce54aca20f5547c14)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
index 3e3f9eaa65e..374d9f60618 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target int128 } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
 /* { dg-options "-maltivec -mno-vsx" } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
index 3e3f9eaa65e..374d9f60618 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target int128 } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
 /* { dg-options "-maltivec -mno-vsx" } */
 

commit 5071f380a1bd741a361982750d28c20acc9f1f05
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 21 02:20:53 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c1c682ab1b0..466861bc455 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2023-06-20  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-06-12  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/109932
+	* config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
+	__builtin_unpack_vector_int128): Move from stanza power7 to vsx.
+
+2023-06-20  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-06-12  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/110011
+	* config/rs6000/rs6000.cc (output_toc): Use the mode of the 128-bit
+	floating constant itself for real_to_target call.
+
 2023-06-15  Lulu Cheng  <chenglulu@loongson.cn>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 414ba4c8afb..047f836b4f3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230620
+20230621
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 49de2f769ee..974d1ce48c8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,30 @@
+2023-06-20  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-06-13  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR testsuite/110230
+	PR target/109932
+	* gcc.target/powerpc/pr109932-1.c: Adjust with int128 effective target.
+	* gcc.target/powerpc/pr109932-2.c: Ditto.
+
+2023-06-20  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-06-12  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/109932
+	* gcc.target/powerpc/pr109932-1.c: New test.
+	* gcc.target/powerpc/pr109932-2.c: New test.
+
+2023-06-20  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-06-12  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/110011
+	* gcc.target/powerpc/pr110011.c: New test.
+
 2023-06-15  Xi Ruoyao  <xry111@xry111.site>
 
 	Backported from master:

commit 636795a6dfc17ead7b22b9f76b0fc47bdb9d357d
Author: Jason Merrill <jason@redhat.com>
Date:   Fri Aug 19 05:53:16 2022

    libstdc++: avoid bogus -Wrestrict [PR105651]
    
            PR tree-optimization/105651
    
    libstdc++-v3/ChangeLog:
    
            * include/bits/basic_string.tcc (_M_replace): Add an assert
            to avoid -Wrestrict false positive.

diff --git a/libstdc++-v3/include/bits/basic_string.tcc b/libstdc++-v3/include/bits/basic_string.tcc
index 0696b96604c..48fa28e6466 100644
--- a/libstdc++-v3/include/bits/basic_string.tcc
+++ b/libstdc++-v3/include/bits/basic_string.tcc
@@ -529,6 +529,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 		    {
 		      const size_type __nleft = (__p + __len1) - __s;
 		      this->_S_move(__p, __s, __nleft);
+		      // Tell the middle-end that the copy can't overlap
+		      // (PR105651).
+		      if (__len2 < __nleft)
+			__builtin_unreachable();
 		      this->_S_copy(__p + __nleft, __p + __len2,
 				    __len2 - __nleft);
 		    }

commit 2dfa92f0653771f6872847d1f2629abce21c9158
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 22 02:19:48 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 047f836b4f3..2fa39115675 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230621
+20230622
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 214b6013268..bf1868bccd2 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,9 @@
+2023-06-21  Jason Merrill  <jason@redhat.com>
+
+	PR tree-optimization/105651
+	* include/bits/basic_string.tcc (_M_replace): Add an assert
+	to avoid -Wrestrict false positive.
+
 2023-05-30  Alexandre Oliva  <oliva@adacore.com>
 
 	Backported from master:

commit c0ab0d4af51382d9d8d4e6b026865842d8e06d7e
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Tue Jun 6 12:04:45 2023

    aarch64: Fix whitespace in ls64 builtin implementation [PR110100]
    
    The ls64 builtin code was using incorrect GNU style with eight spaces where
    there should be a tab. Fixed thusly.
    
    gcc/ChangeLog:
    
            PR target/110100
            * config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types):
            Replace eight consecutive spaces with tabs.
            (aarch64_init_ls64_builtins): Likewise.
            (aarch64_expand_builtin_ls64): Likewise.
            * config/aarch64/aarch64.md (ld64b): Likewise.
            (st64b): Likewise.
            (st64bv): Likewise
            (st64bv0): Likewise.
    
    (cherry picked from commit 713613541254039a34e1dd8fd4a613a299af1fd6)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index 42276e7caf7..06738d22691 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1634,11 +1634,11 @@ aarch64_init_ls64_builtins_types (void)
   gcc_assert (TYPE_ALIGN (array_type) == 64);
 
   tree field = build_decl (input_location, FIELD_DECL,
-                           get_identifier ("val"), array_type);
+			   get_identifier ("val"), array_type);
 
   ls64_arm_data_t = lang_hooks.types.simulate_record_decl (input_location,
-                         tuple_type_name,
-                         make_array_slice (&field, 1));
+			 tuple_type_name,
+			 make_array_slice (&field, 1));
 
   gcc_assert (TYPE_MODE (ls64_arm_data_t) == V8DImode);
   gcc_assert (TYPE_MODE_RAW (ls64_arm_data_t) == TYPE_MODE (ls64_arm_data_t));
@@ -1653,16 +1653,16 @@ aarch64_init_ls64_builtins (void)
   ls64_builtins_data data[4] = {
     {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B,
      build_function_type_list (ls64_arm_data_t,
-                               const_ptr_type_node, NULL_TREE)},
+			       const_ptr_type_node, NULL_TREE)},
     {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B,
      build_function_type_list (void_type_node, ptr_type_node,
-                               ls64_arm_data_t, NULL_TREE)},
+			       ls64_arm_data_t, NULL_TREE)},
     {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV,
      build_function_type_list (uint64_type_node, ptr_type_node,
-                               ls64_arm_data_t, NULL_TREE)},
+			       ls64_arm_data_t, NULL_TREE)},
     {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0,
      build_function_type_list (uint64_type_node, ptr_type_node,
-                               ls64_arm_data_t, NULL_TREE)},
+			       ls64_arm_data_t, NULL_TREE)},
   };
 
   for (size_t i = 0; i < ARRAY_SIZE (data); ++i)
@@ -2281,40 +2281,40 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target)
     {
     case AARCH64_LS64_BUILTIN_LD64B:
       {
-        rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
-        create_output_operand (&ops[0], target, V8DImode);
-        create_input_operand (&ops[1], op0, DImode);
-        expand_insn (CODE_FOR_ld64b, 2, ops);
-        return ops[0].value;
+	rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+	create_output_operand (&ops[0], target, V8DImode);
+	create_input_operand (&ops[1], op0, DImode);
+	expand_insn (CODE_FOR_ld64b, 2, ops);
+	return ops[0].value;
       }
     case AARCH64_LS64_BUILTIN_ST64B:
       {
-        rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
-        rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
-        create_output_operand (&ops[0], op0, DImode);
-        create_input_operand (&ops[1], op1, V8DImode);
-        expand_insn (CODE_FOR_st64b, 2, ops);
-        return const0_rtx;
+	rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+	rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
+	create_output_operand (&ops[0], op0, DImode);
+	create_input_operand (&ops[1], op1, V8DImode);
+	expand_insn (CODE_FOR_st64b, 2, ops);
+	return const0_rtx;
       }
     case AARCH64_LS64_BUILTIN_ST64BV:
       {
-        rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
-        rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
-        create_output_operand (&ops[0], target, DImode);
-        create_input_operand (&ops[1], op0, DImode);
-        create_input_operand (&ops[2], op1, V8DImode);
-        expand_insn (CODE_FOR_st64bv, 3, ops);
-        return ops[0].value;
+	rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+	rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
+	create_output_operand (&ops[0], target, DImode);
+	create_input_operand (&ops[1], op0, DImode);
+	create_input_operand (&ops[2], op1, V8DImode);
+	expand_insn (CODE_FOR_st64bv, 3, ops);
+	return ops[0].value;
       }
     case AARCH64_LS64_BUILTIN_ST64BV0:
       {
-        rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
-        rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
-        create_output_operand (&ops[0], target, DImode);
-        create_input_operand (&ops[1], op0, DImode);
-        create_input_operand (&ops[2], op1, V8DImode);
-        expand_insn (CODE_FOR_st64bv0, 3, ops);
-        return ops[0].value;
+	rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+	rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
+	create_output_operand (&ops[0], target, DImode);
+	create_input_operand (&ops[1], op0, DImode);
+	create_input_operand (&ops[2], op1, V8DImode);
+	expand_insn (CODE_FOR_st64bv0, 3, ops);
+	return ops[0].value;
       }
     }
 
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d24c8afcfa6..d89b2badba7 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -7668,9 +7668,9 @@
 ;; Load/Store 64-bit (LS64) instructions.
 (define_insn "ld64b"
   [(set (match_operand:V8DI 0 "register_operand" "=r")
-        (unspec_volatile:V8DI
-          [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))]
-            UNSPEC_LD64B)
+	(unspec_volatile:V8DI
+	  [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))]
+	    UNSPEC_LD64B)
   )]
   "TARGET_LS64"
   "ld64b\\t%0, [%1]"
@@ -7679,8 +7679,8 @@
 
 (define_insn "st64b"
   [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r"))
-        (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")]
-            UNSPEC_ST64B)
+	(unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")]
+	    UNSPEC_ST64B)
   )]
   "TARGET_LS64"
   "st64b\\t%1, [%0]"
@@ -7689,10 +7689,10 @@
 
 (define_insn "st64bv"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET))
+	(unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET))
    (set (mem:V8DI (match_operand:DI 1 "register_operand" "r"))
-        (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")]
-            UNSPEC_ST64BV)
+	(unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")]
+	    UNSPEC_ST64BV)
   )]
   "TARGET_LS64"
   "st64bv\\t%0, %2, [%1]"
@@ -7701,10 +7701,10 @@
 
 (define_insn "st64bv0"
   [(set (match_operand:DI 0 "register_operand" "=r")
-        (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET))
+	(unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET))
    (set (mem:V8DI (match_operand:DI 1 "register_operand" "r"))
-        (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")]
-            UNSPEC_ST64BV0)
+	(unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")]
+	    UNSPEC_ST64BV0)
   )]
   "TARGET_LS64"
   "st64bv0\\t%0, %2, [%1]"

commit 0112ed013847ca9dbef4ba21f1c3f94c5bbe310b
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Tue Jun 6 12:52:19 2023

    aarch64: Fix wrong code with st64b builtin [PR110100]
    
    The st64b pattern incorrectly had an output constraint on the register
    operand containing the destination address for the store, leading to
    wrong code. This patch fixes that.
    
    gcc/ChangeLog:
    
            PR target/110100
            * config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64):
            Use input operand for the destination address.
            * config/aarch64/aarch64.md (st64b): Fix constraint on address
            operand.
    
    gcc/testsuite/ChangeLog:
    
            PR target/110100
            * gcc.target/aarch64/acle/pr110100.c: New test.
    
    (cherry picked from commit 737a0b749a7bc3e7cb904ea2d4b18dc130514b85)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index 06738d22691..d8b69e802ed 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2291,7 +2291,7 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target)
       {
 	rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
 	rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
-	create_output_operand (&ops[0], op0, DImode);
+	create_input_operand (&ops[0], op0, DImode);
 	create_input_operand (&ops[1], op1, V8DImode);
 	expand_insn (CODE_FOR_st64b, 2, ops);
 	return const0_rtx;
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d89b2badba7..b9b3ba4f916 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -7678,7 +7678,7 @@
 )
 
 (define_insn "st64b"
-  [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r"))
+  [(set (mem:V8DI (match_operand:DI 0 "register_operand" "r"))
 	(unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")]
 	    UNSPEC_ST64B)
   )]
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c
new file mode 100644
index 00000000000..f56d5e619e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.7-a -O2" } */
+#include <arm_acle.h>
+void do_st64b(data512_t data) {
+  __arm_st64b((void*)0x10000000, data);
+}
+/* { dg-final { scan-assembler {mov\tx([123])?[0-9], 268435456} } } */

commit 4481d70c9edcd89a8d9f6c0d705b05230aa080e3
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Tue Jun 6 16:19:03 2023

    aarch64: Allow compiler to define ls64 builtins [PR110132]
    
    This patch refactors the ls64 builtins to allow the compiler to define them
    directly instead of having wrapper functions in arm_acle.h. This should be not
    only easier to maintain, but it makes two important correctness fixes:
     - It fixes PR110132, where the builtins ended up getting declared with
       invisible bindings in the C FE, so the FE ended up synthesizing
       incompatible implicit definitions for these builtins.
     - It allows the builtins to be used with LTO, which didn't work previously.
    
    We also take the opportunity to add test coverage from C++ for these
    builtins.
    
    gcc/ChangeLog:
    
            PR target/110132
            * config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin):
            New. Use it ...
            (aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE
            names for builtins.
            (aarch64_general_init_builtins): Ensure we invoke the arm_acle.h
            setup if in_lto_p, just like we do for SVE.
            * config/aarch64/arm_acle.h: (__arm_ld64b): Delete.
            (__arm_st64b): Delete.
            (__arm_st64bv): Delete.
            (__arm_st64bv0): Delete.
    
    gcc/testsuite/ChangeLog:
    
            PR target/110132
            * lib/target-supports.exp (check_effective_target_aarch64_asm_FUNC_ok):
            Extend to ls64.
            * g++.target/aarch64/acle/acle.exp: New.
            * g++.target/aarch64/acle/ls64.C: New test.
            * g++.target/aarch64/acle/ls64_lto.C: New test.
            * gcc.target/aarch64/acle/ls64_lto.c: New test.
            * gcc.target/aarch64/acle/pr110132.c: New test.
    
    (cherry picked from commit 9963029a24f2d2510b82e7106fae3f364da33c5d)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index d8b69e802ed..197b763658c 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -751,6 +751,16 @@ aarch64_general_add_builtin (const char *name, tree type, unsigned int code,
 			       NULL, attrs);
 }
 
+static tree
+aarch64_general_simulate_builtin (const char *name, tree fntype,
+				  unsigned int code,
+				  tree attrs = NULL_TREE)
+{
+  code = (code << AARCH64_BUILTIN_SHIFT) | AARCH64_BUILTIN_GENERAL;
+  return simulate_builtin_function_decl (input_location, name, fntype,
+					 code, NULL, attrs);
+}
+
 static const char *
 aarch64_mangle_builtin_scalar_type (const_tree type)
 {
@@ -1651,23 +1661,24 @@ aarch64_init_ls64_builtins (void)
   aarch64_init_ls64_builtins_types ();
 
   ls64_builtins_data data[4] = {
-    {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B,
+    {"__arm_ld64b", AARCH64_LS64_BUILTIN_LD64B,
      build_function_type_list (ls64_arm_data_t,
 			       const_ptr_type_node, NULL_TREE)},
-    {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B,
+    {"__arm_st64b", AARCH64_LS64_BUILTIN_ST64B,
      build_function_type_list (void_type_node, ptr_type_node,
 			       ls64_arm_data_t, NULL_TREE)},
-    {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV,
+    {"__arm_st64bv", AARCH64_LS64_BUILTIN_ST64BV,
      build_function_type_list (uint64_type_node, ptr_type_node,
 			       ls64_arm_data_t, NULL_TREE)},
-    {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0,
+    {"__arm_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0,
      build_function_type_list (uint64_type_node, ptr_type_node,
 			       ls64_arm_data_t, NULL_TREE)},
   };
 
   for (size_t i = 0; i < ARRAY_SIZE (data); ++i)
     aarch64_builtin_decls[data[i].code]
-      = aarch64_general_add_builtin (data[i].name, data[i].type, data[i].code);
+      = aarch64_general_simulate_builtin (data[i].name, data[i].type,
+					  data[i].code);
 }
 
 static void
@@ -1800,6 +1811,9 @@ aarch64_general_init_builtins (void)
 
   if (TARGET_MEMTAG)
     aarch64_init_memtag_builtins ();
+
+  if (in_lto_p)
+    handle_arm_acle_h ();
 }
 
 /* Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group.  */
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index d26e269cb84..24c02d4fdf3 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -270,40 +270,7 @@ __ttest (void)
 #endif
 
 #ifdef __ARM_FEATURE_LS64
-#pragma GCC push_options
-#pragma GCC target ("+nothing+ls64")
-
 typedef __arm_data512_t data512_t;
-
-__extension__ extern __inline data512_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_ld64b (const void *__addr)
-{
-  return __builtin_aarch64_ld64b (__addr);
-}
-
-__extension__ extern __inline void
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_st64b (void *__addr, data512_t __value)
-{
-  __builtin_aarch64_st64b (__addr, __value);
-}
-
-__extension__ extern __inline uint64_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_st64bv (void *__addr, data512_t __value)
-{
-  return __builtin_aarch64_st64bv (__addr, __value);
-}
-
-__extension__ extern __inline uint64_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_st64bv0 (void *__addr, data512_t __value)
-{
-  return __builtin_aarch64_st64bv0 (__addr, __value);
-}
-
-#pragma GCC pop_options
 #endif
 
 #pragma GCC push_options
diff --git a/gcc/testsuite/g++.target/aarch64/acle/acle.exp b/gcc/testsuite/g++.target/aarch64/acle/acle.exp
new file mode 100644
index 00000000000..9e1cbf4a0c6
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/acle/acle.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 2014-2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if ![istarget aarch64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib g++-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/g++.target/aarch64/acle/ls64.C b/gcc/testsuite/g++.target/aarch64/acle/ls64.C
new file mode 100644
index 00000000000..d9002785b57
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/acle/ls64.C
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.7-a" } */
+#include <arm_acle.h>
+int main()
+{
+  data512_t d = __arm_ld64b ((const void *)0x1000);
+  __arm_st64b ((void *)0x2000, d);
+  uint64_t x = __arm_st64bv ((void *)0x3000, d);
+  x += __arm_st64bv0 ((void *)0x4000, d);
+}
diff --git a/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C b/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C
new file mode 100644
index 00000000000..274a4771e1c
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C
@@ -0,0 +1,10 @@
+/* { dg-do link { target aarch64_asm_ls64_ok } } */
+/* { dg-additional-options "-march=armv8.7-a -flto" } */
+#include <arm_acle.h>
+int main()
+{
+  data512_t d = __arm_ld64b ((const void *)0x1000);
+  __arm_st64b ((void *)0x2000, d);
+  uint64_t x = __arm_st64bv ((void *)0x3000, d);
+  x += __arm_st64bv0 ((void *)0x4000, d);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c
new file mode 100644
index 00000000000..8b4f2427771
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c
@@ -0,0 +1,10 @@
+/* { dg-do link { target aarch64_asm_ls64_ok } } */
+/* { dg-additional-options "-march=armv8.7-a -flto" } */
+#include <arm_acle.h>
+int main(void)
+{
+  data512_t d = __arm_ld64b ((const void *)0x1000);
+  __arm_st64b ((void *)0x2000, d);
+  uint64_t x = __arm_st64bv ((void *)0x3000, d);
+  x += __arm_st64bv0 ((void *)0x4000, d);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c b/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c
new file mode 100644
index 00000000000..fb88d633dd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.7-a" } */
+
+/* Check that ls64 builtins can be invoked using a preprocesed testcase
+   without triggering bogus builtin warnings, see PR110132.
+
+   Note that this is purely to test GCC internals and user code should
+   include arm_acle.h to make use of these builtins.  */
+
+#pragma GCC aarch64 "arm_acle.h"
+typedef __arm_data512_t data512_t;
+void f(void *p, data512_t d)
+{
+  __arm_st64b (p, d);
+}
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index c858bd93b8e..14eac421d7f 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -10597,7 +10597,7 @@ proc check_effective_target_aarch64_tiny { } {
 # various architecture extensions via the .arch_extension pseudo-op.
 
 foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
-			  "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" } {
+			  "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64" } {
     eval [string map [list FUNC $aarch64_ext] {
 	proc check_effective_target_aarch64_asm_FUNC_ok { } {
 	  if { [istarget aarch64*-*-*] } {

commit c3f04b79eca06c8fe4ad5d2e3d194942a7c2ef10
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 23 02:20:18 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 466861bc455..6aea52f78fa 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,46 @@
+2023-06-22  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110132
+	* config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin):
+	New. Use it ...
+	(aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE
+	names for builtins.
+	(aarch64_general_init_builtins): Ensure we invoke the arm_acle.h
+	setup if in_lto_p, just like we do for SVE.
+	* config/aarch64/arm_acle.h: (__arm_ld64b): Delete.
+	(__arm_st64b): Delete.
+	(__arm_st64bv): Delete.
+	(__arm_st64bv0): Delete.
+
+2023-06-22  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110100
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64):
+	Use input operand for the destination address.
+	* config/aarch64/aarch64.md (st64b): Fix constraint on address
+	operand.
+
+2023-06-22  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110100
+	* config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types):
+	Replace eight consecutive spaces with tabs.
+	(aarch64_init_ls64_builtins): Likewise.
+	(aarch64_expand_builtin_ls64): Likewise.
+	* config/aarch64/aarch64.md (ld64b): Likewise.
+	(st64b): Likewise.
+	(st64bv): Likewise
+	(st64bv0): Likewise.
+
 2023-06-20  Kewen Lin  <linkw@linux.ibm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2fa39115675..0d054fa2ec3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230622
+20230623
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 974d1ce48c8..0ed53723264 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,25 @@
+2023-06-22  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110132
+	* lib/target-supports.exp (check_effective_target_aarch64_asm_FUNC_ok):
+	Extend to ls64.
+	* g++.target/aarch64/acle/acle.exp: New.
+	* g++.target/aarch64/acle/ls64.C: New test.
+	* g++.target/aarch64/acle/ls64_lto.C: New test.
+	* gcc.target/aarch64/acle/ls64_lto.c: New test.
+	* gcc.target/aarch64/acle/pr110132.c: New test.
+
+2023-06-22  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110100
+	* gcc.target/aarch64/acle/pr110100.c: New test.
+
 2023-06-20  Kewen Lin  <linkw@linux.ibm.com>
 
 	Backported from master:

commit f06f1b4102b1c6965ad6b1da0094d6de5c3a2940
Author: Richard Biener <rguenther@suse.de>
Date:   Fri Jun 9 09:29:09 2023

    middle-end/110182 - TYPE_PRECISION on VECTOR_TYPE causes wrong-code
    
    When folding two conversions in a row we use TYPE_PRECISION but
    that's invalid for VECTOR_TYPE.  The following fixes this by
    using element_precision instead.
    
            PR middle-end/110182
            * match.pd (two conversions in a row): Use element_precision
            to DTRT for VECTOR_TYPE.
    
    (cherry picked from commit 3e12669a0eb968cfcbe9242b382fd8020935edf8)

diff --git a/gcc/match.pd b/gcc/match.pd
index 70b85b965b9..f2828006fd6 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3711,19 +3711,19 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
       int inside_ptr = POINTER_TYPE_P (inside_type);
       int inside_float = FLOAT_TYPE_P (inside_type);
       int inside_vec = VECTOR_TYPE_P (inside_type);
-      unsigned int inside_prec = TYPE_PRECISION (inside_type);
+      unsigned int inside_prec = element_precision (inside_type);
       int inside_unsignedp = TYPE_UNSIGNED (inside_type);
       int inter_int = INTEGRAL_TYPE_P (inter_type);
       int inter_ptr = POINTER_TYPE_P (inter_type);
       int inter_float = FLOAT_TYPE_P (inter_type);
       int inter_vec = VECTOR_TYPE_P (inter_type);
-      unsigned int inter_prec = TYPE_PRECISION (inter_type);
+      unsigned int inter_prec = element_precision (inter_type);
       int inter_unsignedp = TYPE_UNSIGNED (inter_type);
       int final_int = INTEGRAL_TYPE_P (type);
       int final_ptr = POINTER_TYPE_P (type);
       int final_float = FLOAT_TYPE_P (type);
       int final_vec = VECTOR_TYPE_P (type);
-      unsigned int final_prec = TYPE_PRECISION (type);
+      unsigned int final_prec = element_precision (type);
       int final_unsignedp = TYPE_UNSIGNED (type);
     }
    (switch

commit c409f2a1cc5d5bffe2fb93454924ae402c57f8f6
Author: Richard Biener <rguenther@suse.de>
Date:   Mon Jun 19 09:52:45 2023

    tree-optimization/110298 - CFG cleanup and stale nb_iterations
    
    When unrolling we eventually kill nb_iterations info since it may
    refer to removed SSA names.  But we do this only after cleaning
    up the CFG which in turn can end up accessing it.  Fixed by
    swapping the two.
    
            PR tree-optimization/110298
            * tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely):
            Clear number of iterations info before cleaning up the CFG.
    
            * gcc.dg/torture/pr110298.c: New testcase.
    
    (cherry picked from commit 916add3bf6e46467e4391e358b11ecfbc4daa275)

diff --git a/gcc/testsuite/gcc.dg/torture/pr110298.c b/gcc/testsuite/gcc.dg/torture/pr110298.c
new file mode 100644
index 00000000000..139f5c77d89
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr110298.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+
+int a, b, c, d, e;
+int f() {
+  c = 0;
+  for (; c >= 0; c--) {
+    d = 0;
+    for (; d <= 0; d++) {
+      e = 0;
+      for (; d + c + e >= 0; e--)
+        ;
+      a = 1;
+      b = 0;
+      for (; a; ++b)
+        a *= 2;
+      for (; b + d >= 0;)
+        return 0;
+    }
+  }
+}
diff --git a/gcc/tree-ssa-loop-ivcanon.cc b/gcc/tree-ssa-loop-ivcanon.cc
index e2ac2044741..408916c7de0 100644
--- a/gcc/tree-ssa-loop-ivcanon.cc
+++ b/gcc/tree-ssa-loop-ivcanon.cc
@@ -1487,15 +1487,16 @@ tree_unroll_loops_completely (bool may_increase_size, bool unroll_outer)
 	    }
 	  BITMAP_FREE (fathers);
 
+	  /* Clean up the information about numbers of iterations, since
+	     complete unrolling might have invalidated it.  */
+	  scev_reset ();
+
 	  /* This will take care of removing completely unrolled loops
 	     from the loop structures so we can continue unrolling now
 	     innermost loops.  */
 	  if (cleanup_tree_cfg ())
 	    update_ssa (TODO_update_ssa_only_virtuals);
 
-	  /* Clean up the information about numbers of iterations, since
-	     complete unrolling might have invalidated it.  */
-	  scev_reset ();
 	  if (flag_checking && loops_state_satisfies_p (LOOP_CLOSED_SSA))
 	    verify_loop_closed_ssa (true);
 	}

commit 72ceed08d45137b0f1a9b4ea8ca533aa6489bc39
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Mon May 15 22:41:56 2023

    libstdc++: Document removal of implicit allocator rebinding extensions
    
    Traditionally libstdc++ allowed containers to be
    instantiated with allocator's that have the wrong value type, implicitly
    rebinding the allocator to the container's value type. Since C++20 that
    has been explicitly ill-formed, so the extension is no longer supported
    in strict modes (e.g. -std=c++17) and in C++20 and later.
    
    libstdc++-v3/ChangeLog:
    
            * doc/xml/manual/evolution.xml: Document removal of implicit
            allocator rebinding extensions in strict mode and for C++20.
            * doc/html/*: Regenerate.
    
    (cherry picked from commit 8cbaf679a3c1875c5475bd1cb0fb86fb9d03b2d4)

diff --git a/libstdc++-v3/doc/html/manual/api.html b/libstdc++-v3/doc/html/manual/api.html
index 604380e0136..fd6420a9e2c 100644
--- a/libstdc++-v3/doc/html/manual/api.html
+++ b/libstdc++-v3/doc/html/manual/api.html
@@ -370,6 +370,11 @@ Calling a <code class="code">std::bind</code> result as volatile was deprecated
   For the non-default <code class="option">--enable-symvers=gnu-versioned-namespace</code>
   configuration, the shared library SONAME has been changed to
   <code class="filename">libstdc++.so.8</code>.
+</p><p>
+  The extension allowing containers to be instantiated with an allocator
+  that doesn't match the container's value type is no longer allowed in
+  strict (<code class="option">-std=c++NN</code>) modes, only in
+  <code class="option">-std=gnu++NN</code> modes.
 </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="api.rel_91"></a><code class="constant">9</code></h3></div></div></div><p>
   C++17 header
   <code class="filename">&lt;memory_resource&gt;</code>
@@ -425,6 +430,10 @@ Calling a <code class="code">std::bind</code> result as volatile was deprecated
   and
   <code class="filename">&lt;stop_token&gt;</code>
   added.
+</p><p>
+  The extension allowing containers to be instantiated with an allocator
+  that doesn't match the container's value type is no longer allowed in
+  C++20 mode, even in non-strict <code class="option">-std=gnu++20</code> mode.
 </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="api.rel_111"></a><code class="constant">11</code></h3></div></div></div><p>
   The <code class="option">--enable-cheaders=c_std</code> configuration
   was deprecated.
diff --git a/libstdc++-v3/doc/xml/manual/evolution.xml b/libstdc++-v3/doc/xml/manual/evolution.xml
index 82936189179..9259c43fb19 100644
--- a/libstdc++-v3/doc/xml/manual/evolution.xml
+++ b/libstdc++-v3/doc/xml/manual/evolution.xml
@@ -915,6 +915,13 @@ Calling a <code>std::bind</code> result as volatile was deprecated for C++17.
   <filename>libstdc++.so.8</filename>.
 </para>
 
+<para>
+  The extension allowing containers to be instantiated with an allocator
+  that doesn't match the container's value type is no longer allowed in
+  strict (<option>-std=c++NN</option>) modes, only in
+  <option>-std=gnu++NN</option> modes.
+</para>
+
 </section>
 
 <section xml:id="api.rel_91"><info><title><constant>9</constant></title></info>
@@ -998,6 +1005,12 @@ Calling a <code>std::bind</code> result as volatile was deprecated for C++17.
   added.
 </para>
 
+<para>
+  The extension allowing containers to be instantiated with an allocator
+  that doesn't match the container's value type is no longer allowed in
+  C++20 mode, even in non-strict <option>-std=gnu++20</option> mode.
+</para>
+
 </section>
 
 <section xml:id="api.rel_111"><info><title><constant>11</constant></title></info>

commit f4d011b4aa0fc7a9e3df0dada2fd3e1e95e32a6c
Author: Ian Lance Taylor <iant@golang.org>
Date:   Sat Jun 24 01:16:06 2023

    compiler, libgo: support bootstrapping gc compiler
    
    In the Go 1.21 release the package internal/profile imports
    internal/lazyregexp.  That works when bootstrapping with Go 1.17,
    because that compiler has internal/lazyregep and permits importing it.
    We also have internal/lazyregexp in libgo, but since it is not installed
    it is not available for importing.  This CL adds internal/lazyregexp
    to the list of internal packages that are installed for bootstrapping.
    
    The Go 1.21, and earlier, releases have a couple of functions in
    the internal/abi package that are always fully intrinsified.
    The gofrontend recognizes and intrinsifies those functions as well.
    However, the gofrontend was also building function descriptors
    for references to the functions without calling them, which
    failed because there was nothing to refer to.  That is OK for the
    gc compiler, which guarantees that the functions are only called,
    not referenced.  This CL arranges to not generate function descriptors
    for these functions.
    
    For golang/go#60913
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/504798

diff --git a/gcc/go/gofrontend/expressions.cc b/gcc/go/gofrontend/expressions.cc
index 1b3b3bf135e..88b4ceacc07 100644
--- a/gcc/go/gofrontend/expressions.cc
+++ b/gcc/go/gofrontend/expressions.cc
@@ -12325,7 +12325,8 @@ Call_expression::intrinsify(Gogo* gogo,
           return Runtime::make_call(code, loc, 3, a1, a2, a3);
         }
     }
-  else if (package == "internal/abi")
+  else if (package == "internal/abi"
+	   || package == "bootstrap/internal/abi") // for bootstrapping gc
     {
       if (is_method)
 	return NULL;
diff --git a/gcc/go/gofrontend/gogo.cc b/gcc/go/gofrontend/gogo.cc
index d35c6baf582..cca03dcdc35 100644
--- a/gcc/go/gofrontend/gogo.cc
+++ b/gcc/go/gofrontend/gogo.cc
@@ -3331,6 +3331,9 @@ class Create_function_descriptors : public Traverse
   int
   expression(Expression**);
 
+  static bool
+  skip_descriptor(Gogo* gogo, const Named_object*);
+
  private:
   Gogo* gogo_;
 };
@@ -3341,6 +3344,9 @@ class Create_function_descriptors : public Traverse
 int
 Create_function_descriptors::function(Named_object* no)
 {
+  if (Create_function_descriptors::skip_descriptor(this->gogo_, no))
+    return TRAVERSE_CONTINUE;
+
   if (no->is_function()
       && no->func_value()->enclosing() == NULL
       && !no->func_value()->is_method()
@@ -3428,6 +3434,28 @@ Create_function_descriptors::expression(Expression** pexpr)
   return TRAVERSE_CONTINUE;
 }
 
+// The gc compiler has some special cases that it always compiles as
+// intrinsics.  For those we don't want to generate a function
+// descriptor, as there will be no code for it to refer to.
+
+bool
+Create_function_descriptors::skip_descriptor(Gogo* gogo,
+					     const Named_object* no)
+{
+  const std::string& pkgpath(no->package() == NULL
+			     ? gogo->pkgpath()
+			     : no->package()->pkgpath());
+
+  // internal/abi is the standard library package,
+  // bootstrap/internal/abi is the name used when bootstrapping the gc
+  // compiler.
+
+  return ((pkgpath == "internal/abi"
+	   || pkgpath == "bootstrap/internal/abi")
+	  && (no->name() == "FuncPCABI0"
+	      || no->name() == "FuncPCABIInternal"));
+}
+
 // Create function descriptors as needed.  We need a function
 // descriptor for all exported functions and for all functions that
 // are referenced without being called.
@@ -3449,7 +3477,8 @@ Gogo::create_function_descriptors()
       if (no->is_function_declaration()
 	  && !no->func_declaration_value()->type()->is_method()
 	  && !Linemap::is_predeclared_location(no->location())
-	  && !Gogo::is_hidden_name(no->name()))
+	  && !Gogo::is_hidden_name(no->name())
+	  && !Create_function_descriptors::skip_descriptor(this, no))
 	fndecls.push_back(no);
     }
   for (std::vector<Named_object*>::const_iterator p = fndecls.begin();
diff --git a/libgo/Makefile.am b/libgo/Makefile.am
index b03e6553e90..c273d94d111 100644
--- a/libgo/Makefile.am
+++ b/libgo/Makefile.am
@@ -417,6 +417,7 @@ toolexeclibgounicode_DATA = \
 # Some internal packages are needed to bootstrap the gc toolchain.
 toolexeclibgointernaldir = $(toolexeclibgodir)/internal
 toolexeclibgointernal_DATA = \
+	internal/lazyregexp.gox \
 	internal/reflectlite.gox \
 	internal/unsafeheader.gox
 
diff --git a/libgo/Makefile.in b/libgo/Makefile.in
index 16ed62a82ed..04fdb60d497 100644
--- a/libgo/Makefile.in
+++ b/libgo/Makefile.in
@@ -885,6 +885,7 @@ toolexeclibgounicode_DATA = \
 # Some internal packages are needed to bootstrap the gc toolchain.
 toolexeclibgointernaldir = $(toolexeclibgodir)/internal
 toolexeclibgointernal_DATA = \
+	internal/lazyregexp.gox \
 	internal/reflectlite.gox \
 	internal/unsafeheader.gox
 
diff --git a/libgo/go/internal/abi/abi.go b/libgo/go/internal/abi/abi.go
index c4a108847ca..66251274d97 100644
--- a/libgo/go/internal/abi/abi.go
+++ b/libgo/go/internal/abi/abi.go
@@ -17,10 +17,7 @@ package abi
 // compile-time error.
 //
 // Implemented as a compile intrinsic.
-func FuncPCABI0(f any) uintptr {
-	// The compiler should remove all calls.
-	panic("FuncPCABI0")
-}
+func FuncPCABI0(f any) uintptr
 
 // FuncPCABIInternal returns the entry PC of the function f. If f is a
 // direct reference of a function, it must be defined as ABIInternal.
@@ -29,7 +26,4 @@ func FuncPCABI0(f any) uintptr {
 // the behavior is undefined.
 //
 // Implemented as a compile intrinsic.
-func FuncPCABIInternal(f any) uintptr {
-	// The compiler should remove all calls.
-	panic("FuncPCABIInternal")
-}
+func FuncPCABIInternal(f any) uintptr

commit e64fd0c315ea9ee5a6fe0a5124f73cdd0642b2ad
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 24 02:20:02 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6aea52f78fa..8979d546020 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2023-06-23  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110298
+	* tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely):
+	Clear number of iterations info before cleaning up the CFG.
+
+2023-06-23  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-06-09  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/110182
+	* match.pd (two conversions in a row): Use element_precision
+	to DTRT for VECTOR_TYPE.
+
 2023-06-22  Alex Coplan  <alex.coplan@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0d054fa2ec3..cbffb8130b6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230623
+20230624
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0ed53723264..ec39d336379 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2023-06-23  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110298
+	* gcc.dg/torture/pr110298.c: New testcase.
+
 2023-06-22  Alex Coplan  <alex.coplan@arm.com>
 
 	Backported from master:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index bf1868bccd2..bb874201610 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,12 @@
+2023-06-23  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+	* doc/xml/manual/evolution.xml: Document removal of implicit
+	allocator rebinding extensions in strict mode and for C++20.
+	* doc/html/*: Regenerate.
+
 2023-06-21  Jason Merrill  <jason@redhat.com>
 
 	PR tree-optimization/105651

commit fb4a080d854d2e517afe1013a316ee3327aecb68
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 25 02:19:43 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cbffb8130b6..2ee91bf4891 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230624
+20230625

commit f315d6592d4d313b02eac340b7b4b5e0147e7cb4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 26 02:20:00 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2ee91bf4891..2cf61a4ffbf 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230625
+20230626

commit 016047f54713dc601c661ab57c78a26da3759608
Author: Iain Buclaw <ibuclaw@gdcproject.org>
Date:   Mon Jun 26 02:29:46 2023

    d: Fix crash in d/dmd/root/aav.d:127 dmd_aaGetRvalue from DsymbolTable::lookup
    
    Backports patch from upstream dmd mainline for fixing PR110113.
    
    The data being Mem.xrealloc'd contains many Array(T) fields, some of
    which have self references in their data.ptr field thanks to the
    smallarray optimization used by Array.
    
    Naturally then, the memcpy from old GC data to new retains those self
    referenced addresses, and the GC marks the old data as "free". Some time
    later GC.malloc will return a pointer to said "free" data. So now we
    have two GC references to the same memory. One that is treating the data
    as an Array(VarDeclaration) in dmd.escape.escapeByStorage, and the other
    as an AA in the symtab of a dmd.dsymbol.ScopeDsymbol.
    
    Fix this memory corruption by not storing the data in a global variable
    for reuse.  If there are no more live references, the GC will free it.
    
            PR d/110113
    
    gcc/d/ChangeLog:
    
            * dmd/escape.d (checkMutableArguments): Always allocate new buffer for
            computing escapeBy.
    
    gcc/testsuite/ChangeLog:
    
            * gdc.test/compilable/test23978.d: New test.
    
    Reviewed-on: https://github.com/dlang/dmd/pull/15302
    (cherry picked from commit ae3a4cefd855512b10b833a56f275b701bacdb34)

diff --git a/gcc/d/dmd/escape.d b/gcc/d/dmd/escape.d
index 7c7ba96db0d..ab85f8706ec 100644
--- a/gcc/d/dmd/escape.d
+++ b/gcc/d/dmd/escape.d
@@ -77,22 +77,7 @@ bool checkMutableArguments(Scope* sc, FuncDeclaration fd, TypeFunction tf,
         bool isMutable;         // true if reference to mutable
     }
 
-    /* Store escapeBy as static data escapeByStorage so we can keep reusing the same
-     * arrays rather than reallocating them.
-     */
-    __gshared EscapeBy[] escapeByStorage;
-    auto escapeBy = escapeByStorage;
-    if (escapeBy.length < len)
-    {
-        auto newPtr = cast(EscapeBy*)mem.xrealloc(escapeBy.ptr, len * EscapeBy.sizeof);
-        // Clear the new section
-        memset(newPtr + escapeBy.length, 0, (len - escapeBy.length) * EscapeBy.sizeof);
-        escapeBy = newPtr[0 .. len];
-        escapeByStorage = escapeBy;
-    }
-    else
-        escapeBy = escapeBy[0 .. len];
-
+    auto escapeBy = new EscapeBy[len];
     const paramLength = tf.parameterList.length;
 
     // Fill in escapeBy[] with arguments[], ethis, and outerVars[]
@@ -212,13 +197,6 @@ bool checkMutableArguments(Scope* sc, FuncDeclaration fd, TypeFunction tf,
         escape(i, eb, false);
     }
 
-    /* Reset the arrays in escapeBy[] so we can reuse them next time through
-     */
-    foreach (ref eb; escapeBy)
-    {
-        eb.er.reset();
-    }
-
     return errors;
 }
 
diff --git a/gcc/testsuite/gdc.test/compilable/test23978.d b/gcc/testsuite/gdc.test/compilable/test23978.d
new file mode 100644
index 00000000000..cc30f728dee
--- /dev/null
+++ b/gcc/testsuite/gdc.test/compilable/test23978.d
@@ -0,0 +1,30 @@
+// REQUIRED_ARGS: -preview=dip1021 -lowmem
+// https://issues.dlang.org/show_bug.cgi?id=23978
+
+// Note: this is a memory corruption bug.
+// Memory returned by `GC.realloc` retains references to old memory in it,
+// mostly because of the smallarray optimization for `Array(T)`.
+// If this fails again, it might not be consistent, so try running it multiple times.
+
+class LUBench { }
+void lup(ulong , ulong , int , int = 1)
+{
+    new LUBench;
+}
+void lup_3200(ulong iters, ulong flops)
+{
+    lup(iters, flops, 3200);
+}
+void raytrace()
+{
+    struct V
+    {
+        float x, y, z;
+        auto normalize() { }
+        struct Tid { }
+        auto spawnLinked() { }
+        string[] namesByTid;
+        class MessageBox { }
+        auto cross() { }
+    }
+}

commit 0f54a73b998b72f7c8452a63730ec3b16fc47854
Author: Iain Buclaw <ibuclaw@gdcproject.org>
Date:   Mon Jun 26 03:24:27 2023

    d: Suboptimal codegen for __builtin_expect(cond, false)
    
    Since PR96435, both boolean objects and expressions have been evaluated
    in the following way.
    
        (*(ubyte*)&obj_or_expr) & 1
    
    It has been noted that sometimes this can cause the back-end to optimize
    in non-obvious ways - in particular with __builtin_expect.
    
    This @safe feature is now restricted to just when reading the value of a
    bool field that comes from a union.
    
            PR d/110359
    
    gcc/d/ChangeLog:
    
            * d-convert.cc (convert_for_rvalue): Only apply the @safe boolean
            conversion to boolean fields of a union.
            (convert_for_condition): Call convert_for_rvalue in the default case.
    
    gcc/testsuite/ChangeLog:
    
            * gdc.dg/pr110359.d: New test.
    
    (cherry picked from commit ab98db1e8c1b997414539f41b7fb814019497d8d)

diff --git a/gcc/d/d-convert.cc b/gcc/d/d-convert.cc
index ec5da6c10a6..2023245256b 100644
--- a/gcc/d/d-convert.cc
+++ b/gcc/d/d-convert.cc
@@ -620,7 +620,7 @@ convert_expr (tree exp, Type *etype, Type *totype)
   return result ? result : convert (build_ctype (totype), exp);
 }
 
-/* Return a TREE represenwation of EXPR, whose type has been converted from
+/* Return a TREE representation of EXPR, whose type has been converted from
  * ETYPE to TOTYPE, and is being used in an rvalue context.  */
 
 tree
@@ -635,20 +635,27 @@ convert_for_rvalue (tree expr, Type *etype, Type *totype)
     {
       /* If casting from bool, the result is either 0 or 1, any other value
 	 violates @safe code, so enforce that it is never invalid.  */
-      if (CONSTANT_CLASS_P (expr))
-	result = d_truthvalue_conversion (expr);
-      else
+      for (tree ref = expr; TREE_CODE (ref) == COMPONENT_REF;
+	   ref = TREE_OPERAND (ref, 0))
 	{
-	  /* Reinterpret the boolean as an integer and test the first bit.
-	     The generated code should end up being equivalent to:
+	  /* If the expression is a field that's part of a union, reinterpret
+	     the boolean as an integer and test the first bit.  The generated
+	     code should end up being equivalent to:
 		*cast(ubyte *)&expr & 1;  */
-	  machine_mode bool_mode = TYPE_MODE (TREE_TYPE (expr));
-	  tree mtype = lang_hooks.types.type_for_mode (bool_mode, 1);
-	  result = fold_build2 (BIT_AND_EXPR, mtype,
-				build_vconvert (mtype, expr),
-				build_one_cst (mtype));
+	  if (TREE_CODE (TREE_TYPE (TREE_OPERAND (ref, 0))) == UNION_TYPE)
+	    {
+	      machine_mode bool_mode = TYPE_MODE (TREE_TYPE (expr));
+	      tree mtype = lang_hooks.types.type_for_mode (bool_mode, 1);
+	      result = fold_build2 (BIT_AND_EXPR, mtype,
+				    build_vconvert (mtype, expr),
+				    build_one_cst (mtype));
+	      break;
+	    }
 	}
 
+      if (result == NULL_TREE)
+	result = d_truthvalue_conversion (expr);
+
       result = convert (build_ctype (tbtype), result);
     }
 
@@ -845,7 +852,7 @@ convert_for_condition (tree expr, Type *type)
       break;
 
     default:
-      result = expr;
+      result = convert_for_rvalue (expr, type, type);
       break;
     }
 
diff --git a/gcc/testsuite/gdc.dg/pr110359.d b/gcc/testsuite/gdc.dg/pr110359.d
new file mode 100644
index 00000000000..bf69201d9a5
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr110359.d
@@ -0,0 +1,22 @@
+// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110359
+// { dg-do compile }
+// { dg-options "-fdump-tree-original" }
+double pow(in double x, in ulong p)
+{
+    import gcc.builtins : __builtin_expect;
+    if (__builtin_expect(p == 0, false))
+        return 1;
+    if (__builtin_expect(p == 1, false))
+        return x;
+
+    double s = x;
+    double v = 1;
+    for (ulong i = p; i > 1; i >>= 1)
+    {
+        v = (i & 0x1) ? s * v : v;
+        s = s * s;
+    }
+    return v * s;
+}
+// { dg-final { scan-tree-dump "if \\(__builtin_expect \\(p == 0, 0\\) != 0\\)" "original" } }
+// { dg-final { scan-tree-dump "if \\(__builtin_expect \\(p == 1, 0\\) != 0\\)" "original" } }

commit 41cc784882428922c73691ed6811be41cdb4a583
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 27 02:21:48 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2cf61a4ffbf..36a241c62ca 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230626
+20230627
diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog
index e6f4cea8e7b..9f7e4b0545e 100644
--- a/gcc/d/ChangeLog
+++ b/gcc/d/ChangeLog
@@ -1,3 +1,22 @@
+2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110359
+	* d-convert.cc (convert_for_rvalue): Only apply the @safe boolean
+	conversion to boolean fields of a union.
+	(convert_for_condition): Call convert_for_rvalue in the default case.
+
+2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110113
+	* dmd/escape.d (checkMutableArguments): Always allocate new buffer for
+	computing escapeBy.
+
 2023-06-06  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	* dmd/MERGE: Merge upstream dmd 316b89f1e3.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ec39d336379..594967ea5a3 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110359
+	* gdc.dg/pr110359.d: New test.
+
+2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110113
+	* gdc.test/compilable/test23978.d: New test.
+
 2023-06-23  Richard Biener  <rguenther@suse.de>
 
 	Backported from master:

commit ee3bb7cb5d2ecfc64adcfd61afb390e72cc08661
Author: Andrew Pinski <apinski@marvell.com>
Date:   Tue Jun 27 02:14:06 2023

    Mark asm goto with outputs as volatile
    
    The manual references asm goto as being implicitly volatile already
    and that was done when asm goto could not have outputs. When outputs
    were added to `asm goto`, only asm goto without outputs were still being
    marked as volatile. Now some parts of GCC decide, removing the `asm goto`
    is ok if the output is not used, though not updating the CFG (this happens
    on both the RTL level and the gimple level). Since the biggest user of `asm goto`
    is the Linux kernel and they expect them to be volatile (they use them to
    copy to/from userspace), we should just mark the inline-asm as volatile.
    
    OK? Bootstrapped and tested on x86_64-linux-gnu.
    
            PR middle-end/110420
            PR middle-end/103979
            PR middle-end/98619
    
    gcc/ChangeLog:
    
            * gimplify.cc (gimplify_asm_expr): Mark asm with labels as volatile.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.c-torture/compile/asmgoto-6.c: New test.
    
    (cherry picked from commit 478840a2ca491fbff44371caee4983d1e7b7b7cf)

diff --git a/gcc/gimplify.cc b/gcc/gimplify.cc
index a551c574a2d..947fe570e1e 100644
--- a/gcc/gimplify.cc
+++ b/gcc/gimplify.cc
@@ -6847,7 +6847,12 @@ gimplify_asm_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p)
       stmt = gimple_build_asm_vec (TREE_STRING_POINTER (ASM_STRING (expr)),
 				   inputs, outputs, clobbers, labels);
 
-      gimple_asm_set_volatile (stmt, ASM_VOLATILE_P (expr) || noutputs == 0);
+      /* asm is volatile if it was marked by the user as volatile or
+	 there are no outputs or this is an asm goto.  */
+      gimple_asm_set_volatile (stmt,
+			       ASM_VOLATILE_P (expr)
+			       || noutputs == 0
+			       || labels);
       gimple_asm_set_input (stmt, ASM_INPUT_P (expr));
       gimple_asm_set_inline (stmt, ASM_INLINE_P (expr));
 
diff --git a/gcc/testsuite/gcc.c-torture/compile/asmgoto-6.c b/gcc/testsuite/gcc.c-torture/compile/asmgoto-6.c
new file mode 100644
index 00000000000..0652bd4e4e1
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/asmgoto-6.c
@@ -0,0 +1,26 @@
+
+/* { dg-do compile } */
+/* PR middle-end/110420 */
+/* PR middle-end/103979 */
+/* PR middle-end/98619 */
+/* Test that the middle-end does not remove the asm goto
+   with an output. */
+
+static int t;
+void g(void);
+
+void f(void)
+{
+  int  __gu_val;
+  asm goto("#my asm "
+     : "=&r"(__gu_val)
+     :
+     :
+     : Efault);
+  t = __gu_val;
+  g();
+Efault:
+}
+
+/* Make sure "my asm " is still in the assembly. */
+/* { dg-final { scan-assembler "my asm " } } */

commit 5b9b636513cd17447ea708f2dba21978cb96909b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 28 02:21:28 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8979d546020..12a489ae62d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-27  Andrew Pinski  <apinski@marvell.com>
+
+	Backported from master:
+	2023-06-27  Andrew Pinski  <apinski@marvell.com>
+
+	PR middle-end/110420
+	PR middle-end/103979
+	PR middle-end/98619
+	* gimplify.cc (gimplify_asm_expr): Mark asm with labels as volatile.
+
 2023-06-23  Richard Biener  <rguenther@suse.de>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 36a241c62ca..fff3166d023 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230627
+20230628
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 594967ea5a3..960594bcc9e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-27  Andrew Pinski  <apinski@marvell.com>
+
+	Backported from master:
+	2023-06-27  Andrew Pinski  <apinski@marvell.com>
+
+	PR middle-end/110420
+	PR middle-end/103979
+	PR middle-end/98619
+	* gcc.c-torture/compile/asmgoto-6.c: New test.
+
 2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	Backported from master:

commit 41b037966ce4ad9b6381def1e4933111d1974da1
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Jun 26 03:50:25 2023

    Make option mvzeroupper independent of optimization level.
    
    pass_insert_vzeroupper is under condition
    
    TARGET_AVX && TARGET_VZEROUPPER
    && flag_expensive_optimizations && !optimize_size
    
    But the document of mvzeroupper doesn't mention the insertion
    required -O2 and above, it may confuse users when they explicitly
    use -Os -mvzeroupper.
    
    ------------
    mvzeroupper
    Target Mask(VZEROUPPER) Save
    Generate vzeroupper instruction before a transfer of control flow out of
    the function.
    ------------
    
    The patch moves flag_expensive_optimizations && !optimize_size to
    ix86_option_override_internal. It makes -mvzeroupper independent of
    optimization level, but still keeps the behavior of architecture
    tuning(emit_vzeroupper) unchanged.
    
    gcc/ChangeLog:
    
            * config/i386/i386-features.cc (pass_insert_vzeroupper:gate):
            Move flag_expensive_optimizations && !optimize_size to ..
            * config/i386/i386-options.cc (ix86_option_override_internal):
            .. this, it makes -mvzeroupper independent of optimization
            level, but still keeps the behavior of architecture
            tuning(emit_vzeroupper) unchanged.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/avx-vzeroupper-29.c: New testcase.
            * gcc.target/i386/avx-vzeroupper-12.c: Adjust testcase.
            * gcc.target/i386/avx-vzeroupper-7.c: Ditto.
            * gcc.target/i386/avx-vzeroupper-9.c: Ditto.

diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc
index 6fe41c3c24f..6a2444eb6b6 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -1875,8 +1875,7 @@ public:
   /* opt_pass methods: */
   virtual bool gate (function *)
     {
-      return TARGET_AVX && TARGET_VZEROUPPER
-	&& flag_expensive_optimizations && !optimize_size;
+      return TARGET_AVX && TARGET_VZEROUPPER;
     }
 
   virtual unsigned int execute (function *)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 099cec4b610..70ddcd284c4 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -2676,7 +2676,9 @@ ix86_option_override_internal (bool main_args_p,
     sorry ("%<-mcall-ms2sysv-xlogues%> isn%'t currently supported with SEH");
 
   if (!(opts_set->x_target_flags & MASK_VZEROUPPER)
-      && TARGET_EMIT_VZEROUPPER)
+      && TARGET_EMIT_VZEROUPPER
+      && flag_expensive_optimizations
+      && !optimize_size)
     opts->x_target_flags |= MASK_VZEROUPPER;
   if (!(opts_set->x_target_flags & MASK_STV))
     opts->x_target_flags |= MASK_STV;
diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c
index e694d4048bd..5a40e87832c 100644
--- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c
+++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c
@@ -16,5 +16,6 @@ foo ()
   _mm256_zeroupper ();
 }
 
-/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 5 { target { ! ia32 } } } } */
 /* { dg-final { scan-assembler-times "\\*avx_vzeroall" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-29.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-29.c
new file mode 100644
index 00000000000..4af637757f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-29.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mtune=generic -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  x = y;
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c
index ab6d68779b3..75fe5889783 100644
--- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c
+++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c
@@ -12,4 +12,5 @@ foo ()
   _mm256_zeroupper ();
 }
 
-/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 2 { target { ! ia32 } } } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c
index 974e1626a6d..fa0a6dfcaac 100644
--- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c
+++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c
@@ -15,4 +15,5 @@ foo ()
   _mm256_zeroupper ();
 }
 
-/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 5 { target { ! ia32 } } } } */

commit 91cf372463a26e62f83276074dda7a0b7405b0ab
Author: Paul E. Murphy <murphyp@linux.ibm.com>
Date:   Fri Jun 23 00:53:46 2023

    go: Update usage of TARGET_AIX to TARGET_AIX_OS
    
    TARGET_AIX is defined to a non-zero value on linux and maybe other
    powerpc64le targets.  This leads to unexpected behavior such as
    dropping the .go_export section when linking a shared library
    on linux/powerpc64le.
    
    Instead, use TARGET_AIX_OS to toggle AIX specific behavior.
    
    Fixes golang/go#60798.
    
    2023-06-22  Paul E. Murphy  <murphyp@linux.ibm.com>
    
    gcc/go/
            * go-backend.cc [TARGET_AIX]: Rename and update usage to TARGET_AIX_OS.
            * go-lang.cc: Likewise.
    
    (cherry picked from commit b76cd1ec361712e1ac9ca5e0246da24ea2b78916)

diff --git a/gcc/go/go-backend.cc b/gcc/go/go-backend.cc
index 7eed943416a..0a05a0b0645 100644
--- a/gcc/go/go-backend.cc
+++ b/gcc/go/go-backend.cc
@@ -45,8 +45,8 @@ along with GCC; see the file COPYING3.  If not see
 #define GO_EXPORT_SECTION_NAME ".go_export"
 #endif
 
-#ifndef TARGET_AIX
-#define TARGET_AIX 0
+#ifndef TARGET_AIX_OS
+#define TARGET_AIX_OS 0
 #endif
 
 /* This file holds all the cases where the Go frontend needs
@@ -107,7 +107,7 @@ go_write_export_data (const char *bytes, unsigned int size)
     {
       gcc_assert (targetm_common.have_named_sections);
       sec = get_section (GO_EXPORT_SECTION_NAME,
-			 TARGET_AIX ? SECTION_EXCLUDE : SECTION_DEBUG,
+			 TARGET_AIX_OS ? SECTION_EXCLUDE : SECTION_DEBUG,
 			 NULL);
     }
 
diff --git a/gcc/go/go-lang.cc b/gcc/go/go-lang.cc
index c8365d2590a..89fba02026a 100644
--- a/gcc/go/go-lang.cc
+++ b/gcc/go/go-lang.cc
@@ -39,8 +39,8 @@ along with GCC; see the file COPYING3.  If not see
 #include "go-c.h"
 #include "go-gcc.h"
 
-#ifndef TARGET_AIX
-#define TARGET_AIX 0
+#ifndef TARGET_AIX_OS
+#define TARGET_AIX_OS 0
 #endif
 
 /* Language-dependent contents of a type.  */
@@ -119,9 +119,9 @@ go_langhook_init (void)
   args.compiling_runtime = go_compiling_runtime;
   args.debug_escape_level = go_debug_escape_level;
   args.debug_escape_hash = go_debug_escape_hash;
-  args.nil_check_size_threshold = TARGET_AIX ? -1 : 4096;
+  args.nil_check_size_threshold = TARGET_AIX_OS ? -1 : 4096;
   args.debug_optimization = go_debug_optimization;
-  args.need_eqtype = TARGET_AIX ? true : false;
+  args.need_eqtype = TARGET_AIX_OS ? true : false;
   args.linemap = go_get_linemap();
   args.backend = go_get_backend();
   go_create_gogo (&args);

commit a3d6d29656392195fe9b31e340dd6d23fc9d2ce5
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Thu May 4 09:07:35 2023

    libgomp C++ testsuite: Use 'lang_include_flags' instead of 'libstdcxx_includes'
    
    With nvptx offloading configured, and supported, and CUDA available:
    
        $ make check-target-libgomp RUNTESTFLAGS="--all c.exp=context-1.c c++.exp=context-1.c"
        [...]
        Running [...]/libgomp.oacc-c/c.exp ...
        PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O0  (test for excess errors)
        PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O0  execution test
        PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O2  (test for excess errors)
        PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O2  execution test
        UNSUPPORTED: libgomp.oacc-c/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2
        Running [...]/libgomp.oacc-c++/c++.exp ...
        PASS: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O0  (test for excess errors)
        PASS: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O0  execution test
        PASS: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O2  (test for excess errors)
        PASS: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O2  execution test
        UNSUPPORTED: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2
        [...]
    
    ..., but for 'c++.exp=context-1.c' alone, we currently get all-UNSUPPORTED:
    
        $ make check-target-libgomp RUNTESTFLAGS_="--all c++.exp=context-1.c"
        [...]
        Running [...]/libgomp.oacc-c++/c++.exp ...
        UNSUPPORTED: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O0
        UNSUPPORTED: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none  -O2
        UNSUPPORTED: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/context-1.c -DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2
        [...]
    
    That is, if 'c.exp' executes first, it does successfully evaluate
    'dg-require-effective-target openacc_cublas' -- and does cache this result (so
    it isn't reevaluated for 'c++.exp').  However, for 'c++.exp' alone (that is,
    without the 'c.exp' result cached), we run into:
    
        spawn -ignore SIGHUP [xgcc] [...] -x c++ openacc_cublas2311907.c [...]
        In file included from /usr/include/cuda_fp16.h:3673,
                         from /usr/include/cublas_api.h:75,
                         from /usr/include/cublas_v2.h:65,
                         from openacc_cublas2311907.c:3:
        /usr/include/cuda_fp16.hpp:67:10: fatal error: utility: No such file or directory
    
    We're missing include paths to C++/libstdc++ build-tree headers.
    
    Fix this by using the mechanism introduced for Fortran in
    r212268 (commit f707da16f714f7fe5a42391748212c84dfec639b) re
    "libgomp.fortran/fortran.exp - add -fintrinsic-modules-path ${blddir}".
    
            libgomp/
            * testsuite/libgomp.c++/c++.exp: Use 'lang_include_flags' instead
            of 'libstdcxx_includes'.
            * testsuite/libgomp.oacc-c++/c++.exp: Likewise.
    
    (cherry picked from commit 1b93b9191d073bf9e867ab8bfc8e4b59ba5af1f3)

diff --git a/libgomp/testsuite/libgomp.c++/c++.exp b/libgomp/testsuite/libgomp.c++/c++.exp
index f4884e2ffa7..5b9a5924ff3 100644
--- a/libgomp/testsuite/libgomp.c++/c++.exp
+++ b/libgomp/testsuite/libgomp.c++/c++.exp
@@ -66,13 +66,12 @@ if { $lang_test_file_found } {
 
     set flags_file "${blddir}/../libstdc++-v3/scripts/testsuite_flags"
     if { [file exists $flags_file] } {
-	set libstdcxx_includes [exec sh $flags_file --build-includes]
-    } else {
-	set libstdcxx_includes ""
+	set lang_source_re {^.*\.[cC]$}
+	set lang_include_flags [exec sh $flags_file --build-includes]
     }
 
     # Main loop.
-    dg-runtest $tests "" "$libstdcxx_includes $DEFAULT_CFLAGS"
+    dg-runtest $tests "" $DEFAULT_CFLAGS
 }
 
 # See above.
diff --git a/libgomp/testsuite/libgomp.oacc-c++/c++.exp b/libgomp/testsuite/libgomp.oacc-c++/c++.exp
index 42e0395f9a5..0b235ba47f3 100644
--- a/libgomp/testsuite/libgomp.oacc-c++/c++.exp
+++ b/libgomp/testsuite/libgomp.oacc-c++/c++.exp
@@ -72,9 +72,8 @@ if { $lang_test_file_found } {
 
     set flags_file "${blddir}/../libstdc++-v3/scripts/testsuite_flags"
     if { [file exists $flags_file] } {
-	set libstdcxx_includes [exec sh $flags_file --build-includes]
-    } else {
-	set libstdcxx_includes ""
+	set lang_source_re {^.*\.[cC]$}
+	set lang_include_flags [exec sh $flags_file --build-includes]
     }
 
     # Test with all available offload targets, and with offloading disabled.
@@ -147,7 +146,7 @@ if { $lang_test_file_found } {
 	    }
 	}
 
-	gcc-dg-runtest $tests "$tagopt" "$libstdcxx_includes"
+	gcc-dg-runtest $tests "$tagopt" ""
     }
     unset offload_target
 } else {

commit 66df913899d32e7726f986afb61c5c5615eb2a36
Author: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
Date:   Thu May 7 13:26:57 2015

    Support parallel testing in libgomp, part I [PR66005]
    
    ..., while still hard-coding the number of parallel slots to one.
    
            PR testsuite/66005
            libgomp/
            * testsuite/Makefile.am (PWD_COMMAND): New variable.
            (%/site.exp): New target.
            (check_p_numbers0, check_p_numbers1, check_p_numbers2)
            (check_p_numbers3, check_p_numbers4, check_p_numbers5)
            (check_p_numbers6, check_p_numbers, gcc_test_parallel_slots)
            (check_p_subdirs)
            (check_DEJAGNU_libgomp_targets): New variables.
            ($(check_DEJAGNU_libgomp_targets)): New target.
            ($(check_DEJAGNU_libgomp_targets)): New dependency.
            (check-DEJAGNU $(check_DEJAGNU_libgomp_targets)): New targets.
            * testsuite/Makefile.in: Regenerate.
            * testsuite/lib/libgomp.exp: For parallel testing,
            'load_file ../libgomp-test-support.exp'.
    
    Co-authored-by: Thomas Schwinge <thomas@codesourcery.com>
    (cherry picked from commit e797db5c744f7b4e110f23a495fca8e6b8aebe83)

diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am
index 655a413c160..eef02f4a8c2 100644
--- a/libgomp/testsuite/Makefile.am
+++ b/libgomp/testsuite/Makefile.am
@@ -12,6 +12,8 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
 	     echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
 RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir
 
+PWD_COMMAND = $${PWDCMD-pwd}
+
 EXTRA_DEJAGNU_SITE_CONFIG = libgomp-site-extra.exp
 
 # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the
@@ -25,17 +27,6 @@ libgomp-test-support.exp: libgomp-test-support.pt.exp Makefile
 	  'set offload_additional_lib_paths "$(offload_additional_lib_paths)"'
 	mv $@.tmp $@
 
-check-DEJAGNU: site.exp
-	srcdir='$(srcdir)'; export srcdir; \
-	EXPECT=$(EXPECT); export EXPECT; \
-	if $(SHELL) -c "$(_RUNTEST) --version" > /dev/null 2>&1; then \
-	  exit_status=0; l='$(PACKAGE)'; for tool in $$l; do \
-	    if $(_RUNTEST) $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \
-	    then :; else exit_status=1; fi; \
-	  done; \
-	else echo "WARNING: could not find '$(_RUNTEST)'" 1>&2; :;\
-	fi; \
-	exit $$exit_status
 site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG)
 	@echo 'Making a new site.exp file ...'
 	@echo '## these variables are automatically generated by make ##' >site.tmp
@@ -63,6 +54,71 @@ site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG)
 	@test ! -f site.exp || mv site.exp site.bak
 	@mv site.tmp site.exp
 
+%/site.exp: site.exp
+	-@test -d $* || mkdir $*
+	@srcdir=`cd $(srcdir); ${PWD_COMMAND}`;
+	@objdir=`${PWD_COMMAND}`/$*; \
+	sed -e "s|^set srcdir .*$$|set srcdir $$srcdir|" \
+	    -e "s|^set objdir .*$$|set objdir $$objdir|" \
+	    site.exp > $*/site.exp.tmp
+	@-rm -f $*/site.bak
+	@test ! -f $*/site.exp || mv $*/site.exp $*/site.bak
+	@mv $*/site.exp.tmp $*/site.exp
+
+check_p_numbers0:=1 2 3 4 5 6 7 8 9
+check_p_numbers1:=0 $(check_p_numbers0)
+check_p_numbers2:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers1)))
+check_p_numbers3:=$(addprefix 0,$(check_p_numbers1)) $(check_p_numbers2)
+check_p_numbers4:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers3)))
+check_p_numbers5:=$(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4)
+check_p_numbers6:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5)))
+check_p_numbers:=$(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6)
+gcc_test_parallel_slots:=1
+check_p_subdirs=$(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers))
+check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs))
+$(check_DEJAGNU_libgomp_targets): check-DEJAGNUlibgomp%: libgomp%/site.exp
+
+check-DEJAGNU $(check_DEJAGNU_libgomp_targets): check-DEJAGNU%: site.exp
+	$(if $*,@)AR="$(AR)"; export AR; \
+	RANLIB="$(RANLIB)"; export RANLIB; \
+	if [ -z "$*" ] && [ -n "$(filter -j%, $(MFLAGS))" ]; then \
+	  rm -rf libgomp-parallel || true; \
+	  mkdir libgomp-parallel; \
+	  $(MAKE) $(AM_MAKEFLAGS) $(check_DEJAGNU_libgomp_targets); \
+	  rm -rf libgomp-parallel || true; \
+	  for idx in $(check_p_subdirs); do \
+	    if [ -d libgomp$$idx ]; then \
+	      mv -f libgomp$$idx/libgomp.sum libgomp$$idx/libgomp.sum.sep; \
+	      mv -f libgomp$$idx/libgomp.log libgomp$$idx/libgomp.log.sep; \
+	    fi; \
+	  done; \
+	  $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh \
+	    libgomp[0-9]*/libgomp.sum.sep > libgomp.sum; \
+	  $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh -L \
+	    libgomp[0-9]*/libgomp.log.sep > libgomp.log; \
+	  exit 0; \
+	fi; \
+	srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \
+	EXPECT=$(EXPECT); export EXPECT; \
+	runtest=$(_RUNTEST); \
+	if [ -z "$$runtest" ]; then runtest=runtest; fi; \
+	tool=libgomp; \
+	if [ -n "$*" ]; then \
+	  if [ -f libgomp-parallel/finished ]; then rm -rf "$*"; exit 0; fi; \
+	  GCC_RUNTEST_PARALLELIZE_DIR=`${PWD_COMMAND}`/libgomp-parallel; \
+	  export GCC_RUNTEST_PARALLELIZE_DIR; \
+	  cd "$*"; \
+	fi; \
+	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+	  $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+		    $(RUNTESTFLAGS); \
+	  if [ -n "$*" ]; then \
+	    touch $$GCC_RUNTEST_PARALLELIZE_DIR/finished; \
+	  fi; \
+	else \
+	  echo "WARNING: could not find \`runtest'" 1>&2; :;\
+	fi
+
 distclean-DEJAGNU:
 	-rm -f site.exp site.bak
 	-l='$(PACKAGE)'; for tool in $$l; do \
diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in
index e48c3f2f9b0..c29c16c1e7f 100644
--- a/libgomp/testsuite/Makefile.in
+++ b/libgomp/testsuite/Makefile.in
@@ -310,7 +310,19 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
 	     echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
 
 RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir
+PWD_COMMAND = $${PWDCMD-pwd}
 EXTRA_DEJAGNU_SITE_CONFIG = libgomp-site-extra.exp
+check_p_numbers0 := 1 2 3 4 5 6 7 8 9
+check_p_numbers1 := 0 $(check_p_numbers0)
+check_p_numbers2 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers1)))
+check_p_numbers3 := $(addprefix 0,$(check_p_numbers1)) $(check_p_numbers2)
+check_p_numbers4 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers3)))
+check_p_numbers5 := $(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4)
+check_p_numbers6 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5)))
+check_p_numbers := $(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6)
+gcc_test_parallel_slots := 1
+check_p_subdirs = $(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers))
+check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs))
 all: all-am
 
 .SUFFIXES:
@@ -485,17 +497,6 @@ libgomp-test-support.exp: libgomp-test-support.pt.exp Makefile
 	  'set offload_additional_lib_paths "$(offload_additional_lib_paths)"'
 	mv $@.tmp $@
 
-check-DEJAGNU: site.exp
-	srcdir='$(srcdir)'; export srcdir; \
-	EXPECT=$(EXPECT); export EXPECT; \
-	if $(SHELL) -c "$(_RUNTEST) --version" > /dev/null 2>&1; then \
-	  exit_status=0; l='$(PACKAGE)'; for tool in $$l; do \
-	    if $(_RUNTEST) $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \
-	    then :; else exit_status=1; fi; \
-	  done; \
-	else echo "WARNING: could not find '$(_RUNTEST)'" 1>&2; :;\
-	fi; \
-	exit $$exit_status
 site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG)
 	@echo 'Making a new site.exp file ...'
 	@echo '## these variables are automatically generated by make ##' >site.tmp
@@ -523,6 +524,59 @@ site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG)
 	@test ! -f site.exp || mv site.exp site.bak
 	@mv site.tmp site.exp
 
+%/site.exp: site.exp
+	-@test -d $* || mkdir $*
+	@srcdir=`cd $(srcdir); ${PWD_COMMAND}`;
+	@objdir=`${PWD_COMMAND}`/$*; \
+	sed -e "s|^set srcdir .*$$|set srcdir $$srcdir|" \
+	    -e "s|^set objdir .*$$|set objdir $$objdir|" \
+	    site.exp > $*/site.exp.tmp
+	@-rm -f $*/site.bak
+	@test ! -f $*/site.exp || mv $*/site.exp $*/site.bak
+	@mv $*/site.exp.tmp $*/site.exp
+$(check_DEJAGNU_libgomp_targets): check-DEJAGNUlibgomp%: libgomp%/site.exp
+
+check-DEJAGNU $(check_DEJAGNU_libgomp_targets): check-DEJAGNU%: site.exp
+	$(if $*,@)AR="$(AR)"; export AR; \
+	RANLIB="$(RANLIB)"; export RANLIB; \
+	if [ -z "$*" ] && [ -n "$(filter -j%, $(MFLAGS))" ]; then \
+	  rm -rf libgomp-parallel || true; \
+	  mkdir libgomp-parallel; \
+	  $(MAKE) $(AM_MAKEFLAGS) $(check_DEJAGNU_libgomp_targets); \
+	  rm -rf libgomp-parallel || true; \
+	  for idx in $(check_p_subdirs); do \
+	    if [ -d libgomp$$idx ]; then \
+	      mv -f libgomp$$idx/libgomp.sum libgomp$$idx/libgomp.sum.sep; \
+	      mv -f libgomp$$idx/libgomp.log libgomp$$idx/libgomp.log.sep; \
+	    fi; \
+	  done; \
+	  $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh \
+	    libgomp[0-9]*/libgomp.sum.sep > libgomp.sum; \
+	  $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh -L \
+	    libgomp[0-9]*/libgomp.log.sep > libgomp.log; \
+	  exit 0; \
+	fi; \
+	srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \
+	EXPECT=$(EXPECT); export EXPECT; \
+	runtest=$(_RUNTEST); \
+	if [ -z "$$runtest" ]; then runtest=runtest; fi; \
+	tool=libgomp; \
+	if [ -n "$*" ]; then \
+	  if [ -f libgomp-parallel/finished ]; then rm -rf "$*"; exit 0; fi; \
+	  GCC_RUNTEST_PARALLELIZE_DIR=`${PWD_COMMAND}`/libgomp-parallel; \
+	  export GCC_RUNTEST_PARALLELIZE_DIR; \
+	  cd "$*"; \
+	fi; \
+	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+	  $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+		    $(RUNTESTFLAGS); \
+	  if [ -n "$*" ]; then \
+	    touch $$GCC_RUNTEST_PARALLELIZE_DIR/finished; \
+	  fi; \
+	else \
+	  echo "WARNING: could not find \`runtest'" 1>&2; :;\
+	fi
+
 distclean-DEJAGNU:
 	-rm -f site.exp site.bak
 	-l='$(PACKAGE)'; for tool in $$l; do \
diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp
index 8c5ecfff0ac..d1441593354 100644
--- a/libgomp/testsuite/lib/libgomp.exp
+++ b/libgomp/testsuite/lib/libgomp.exp
@@ -40,7 +40,12 @@ load_gcc_lib torture-options.exp
 load_gcc_lib fortran-modules.exp
 
 # Try to load a test support file, built during libgomp configuration.
-load_file libgomp-test-support.exp
+# Search in '..' vs. '.' to support parallel vs. sequential testing.
+if [info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] {
+    load_file ../libgomp-test-support.exp
+} else {
+    load_file libgomp-test-support.exp
+}
 
 set dg-do-what-default run
 

commit 5c6515076f2ba55a31149085d3826e975c114fe5
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Tue Apr 25 23:53:12 2023

    Support parallel testing in libgomp, part II [PR66005]
    
    ..., and enable if 'flock' is available for serializing execution testing.
    
    Regarding the default of 19 parallel slots, this turned out to be a local
    minimum for wall time when testing this on:
    
        $ uname -srvi
        Linux 4.2.0-42-generic #49~14.04.1-Ubuntu SMP Wed Jun 29 20:22:11 UTC 2016 x86_64
        $ grep '^model name' < /proc/cpuinfo | uniq -c
             32 model name      : Intel(R) Xeon(R) CPU E5-2640 v3 @ 2.60GHz
    
    ... in two configurations: case (a) standard configuration, no offloading
    configured, case (b) offloading for GCN and nvptx configured but no devices
    available.  For both cases, default plus '-m32' variant.
    
        $ \time make check-target-libgomp RUNTESTFLAGS="--target_board=unix\{,-m32\}"
    
    Case (a), baseline:
    
        6432.23user 332.38system 47:32.28elapsed 237%CPU (0avgtext+0avgdata 505044maxresident)k
        6382.43user 319.21system 47:06.04elapsed 237%CPU (0avgtext+0avgdata 505172maxresident)k
    
    This is what people have been complaining about, rightly so, in
    <https://gcc.gnu.org/PR66005> "libgomp make check time is excessive" and
    elsewhere.
    
    Case (a), parallelized:
    
        -j12 GCC_TEST_PARALLEL_SLOTS=10
        3088.49user 267.74system 6:43.82elapsed 831%CPU (0avgtext+0avgdata 505188maxresident)k
        -j15 GCC_TEST_PARALLEL_SLOTS=15
        3308.08user 294.79system 5:56.04elapsed 1011%CPU (0avgtext+0avgdata 505360maxresident)k
        -j17 GCC_TEST_PARALLEL_SLOTS=17
        3539.93user 298.99system 5:27.86elapsed 1170%CPU (0avgtext+0avgdata 505112maxresident)k
        -j18 GCC_TEST_PARALLEL_SLOTS=18
        3697.50user 317.18system 5:14.63elapsed 1275%CPU (0avgtext+0avgdata 505360maxresident)k
        -j19 GCC_TEST_PARALLEL_SLOTS=19
        3765.94user 324.27system 5:13.22elapsed 1305%CPU (0avgtext+0avgdata 505128maxresident)k
        -j20 GCC_TEST_PARALLEL_SLOTS=20
        3684.66user 312.32system 5:15.26elapsed 1267%CPU (0avgtext+0avgdata 505100maxresident)k
        -j23 GCC_TEST_PARALLEL_SLOTS=23
        4040.59user 347.10system 5:29.12elapsed 1333%CPU (0avgtext+0avgdata 505200maxresident)k
        -j26 GCC_TEST_PARALLEL_SLOTS=26
        3973.24user 377.96system 5:24.70elapsed 1340%CPU (0avgtext+0avgdata 505160maxresident)k
        -j32 GCC_TEST_PARALLEL_SLOTS=32
        4004.42user 346.10system 5:16.11elapsed 1376%CPU (0avgtext+0avgdata 505160maxresident)k
    
    Yay!
    
    Case (b), baseline; 2+ h:
    
        7227.58user 700.54system 2:14:33elapsed 98%CPU (0avgtext+0avgdata 994264maxresident)k
    
    Case (b), parallelized:
    
        -j12 GCC_TEST_PARALLEL_SLOTS=10
        7377.46user 777.52system 16:06.63elapsed 843%CPU (0avgtext+0avgdata 994344maxresident)k
        -j15 GCC_TEST_PARALLEL_SLOTS=15
        8019.18user 721.42system 12:13.56elapsed 1191%CPU (0avgtext+0avgdata 994228maxresident)k
        -j17 GCC_TEST_PARALLEL_SLOTS=17
        8530.11user 716.95system 10:45.92elapsed 1431%CPU (0avgtext+0avgdata 994176maxresident)k
        -j18 GCC_TEST_PARALLEL_SLOTS=18
        8776.79user 645.89system 10:27.20elapsed 1502%CPU (0avgtext+0avgdata 994248maxresident)k
        -j19 GCC_TEST_PARALLEL_SLOTS=19
        9332.37user 641.76system 10:15.09elapsed 1621%CPU (0avgtext+0avgdata 994260maxresident)k
        -j20 GCC_TEST_PARALLEL_SLOTS=20
        9609.54user 789.88system 10:26.94elapsed 1658%CPU (0avgtext+0avgdata 994284maxresident)k
        -j23 GCC_TEST_PARALLEL_SLOTS=23
        10362.40user 911.14system 10:44.47elapsed 1749%CPU (0avgtext+0avgdata 994208maxresident)k
        -j26 GCC_TEST_PARALLEL_SLOTS=26
        11159.44user 850.99system 11:09.25elapsed 1794%CPU (0avgtext+0avgdata 994256maxresident)k
        -j32 GCC_TEST_PARALLEL_SLOTS=32
        11453.50user 939.52system 11:00.38elapsed 1876%CPU (0avgtext+0avgdata 994240maxresident)k
    
    On my Dell Precision 7530 laptop:
    
        $ uname -srvi
        Linux 5.15.0-71-generic #78-Ubuntu SMP Tue Apr 18 09:00:29 UTC 2023 x86_64
        $ grep '^model name' < /proc/cpuinfo | uniq -c
             12 model name      : Intel(R) Core(TM) i7-8850H CPU @ 2.60GHz
        $ nvidia-smi -L
        GPU 0: Quadro P1000 (UUID: GPU-e043973b-b52a-d02b-c066-a8fdbf64e8ea)
    
    ... in two configurations: case (c) standard configuration, no offloading
    configured, case (d) offloading for nvptx configured and device available.
    For both cases, only default variant, no '-m32'.
    
        $ \time make check-target-libgomp
    
    Case (c), baseline; roughly half of case (a) (just one variant):
    
        1180.98user 110.80system 19:36.40elapsed 109%CPU (0avgtext+0avgdata 505148maxresident)k
        1133.22user 111.08system 19:35.75elapsed 105%CPU (0avgtext+0avgdata 505212maxresident)k
    
    Case (c), parallelized:
    
        -j12 GCC_TEST_PARALLEL_SLOTS=2
        1143.83user 110.76system 10:20.46elapsed 202%CPU (0avgtext+0avgdata 505216maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=6
        1737.08user 143.94system 4:59.48elapsed 628%CPU (0avgtext+0avgdata 505200maxresident)k
        1730.31user 143.02system 4:58.75elapsed 627%CPU (0avgtext+0avgdata 505152maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=8
        2192.63user 169.34system 4:52.96elapsed 806%CPU (0avgtext+0avgdata 505216maxresident)k
        2219.04user 167.67system 4:53.19elapsed 814%CPU (0avgtext+0avgdata 505152maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=10
        2463.93user 184.98system 4:48.39elapsed 918%CPU (0avgtext+0avgdata 505200maxresident)k
        2455.62user 183.68system 4:47.40elapsed 918%CPU (0avgtext+0avgdata 505216maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=12
        2591.04user 192.64system 4:44.98elapsed 976%CPU (0avgtext+0avgdata 505216maxresident)k
        2581.23user 195.21system 4:47.51elapsed 965%CPU (0avgtext+0avgdata 505212maxresident)k
        -j20 GCC_TEST_PARALLEL_SLOTS=20 [oversubscribe]
        2613.18user 199.51system 4:44.06elapsed 990%CPU (0avgtext+0avgdata 505216maxresident)k
    
    Case (d), baseline (compared to case (b): only nvptx offloading compilation,
    but also nvptx offloading execution); ~1 h:
    
        2841.93user 653.68system 1:02:26elapsed 93%CPU (0avgtext+0avgdata 909792maxresident)k
        2842.03user 654.39system 1:02:24elapsed 93%CPU (0avgtext+0avgdata 909880maxresident)k
    
    Case (d), parallelized:
    
        -j12 GCC_TEST_PARALLEL_SLOTS=2
        2856.39user 606.87system 33:58.64elapsed 169%CPU (0avgtext+0avgdata 909948maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=6
        3444.90user 666.86system 18:37.57elapsed 367%CPU (0avgtext+0avgdata 909856maxresident)k
        3462.13user 667.13system 18:36.87elapsed 369%CPU (0avgtext+0avgdata 909872maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=8
        3929.74user 716.22system 18:02.36elapsed 429%CPU (0avgtext+0avgdata 909832maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=10
        4152.84user 736.16system 17:43.05elapsed 459%CPU (0avgtext+0avgdata 909872maxresident)k
        -j12 GCC_TEST_PARALLEL_SLOTS=12
        4209.60user 749.00system 17:35.20elapsed 469%CPU (0avgtext+0avgdata 909840maxresident)k
        -j20 GCC_TEST_PARALLEL_SLOTS=20 [oversubscribe]
        4255.54user 756.78system 17:29.06elapsed 477%CPU (0avgtext+0avgdata 909868maxresident)k
    
    Worth noting is that with nvptx offloading, there is one execution test case
    that times out ('libgomp.fortran/reverse-offload-5.f90').  This effectively
    stalls progress for almost 5 min: quickly other executions test cases queue up
    on the lock for all parallel slots.  That's working as expected; just noting
    this as it accordingly does skew the wall time numbers.
    
            PR testsuite/66005
            libgomp/
            * configure.ac: Look for 'flock'.
            * testsuite/Makefile.am (gcc_test_parallel_slots): Enable parallel testing.
            * testsuite/config/default.exp: Don't 'load_lib "standard.exp"' here...
            * testsuite/lib/libgomp.exp: ... but here, instead.
            (libgomp_load): Override for parallel testing.
            * testsuite/libgomp-site-extra.exp.in (FLOCK): Set.
            * configure: Regenerate.
            * Makefile.in: Regenerate.
            * testsuite/Makefile.in: Regenerate.
    
    (cherry picked from commit 6c3b30ef9e0578509bdaf59c13da4a212fe6c2ba)

diff --git a/libgomp/Makefile.in b/libgomp/Makefile.in
index 6f0cb716135..31ad7aa4b48 100644
--- a/libgomp/Makefile.in
+++ b/libgomp/Makefile.in
@@ -384,6 +384,7 @@ EXEEXT = @EXEEXT@
 FC = @FC@
 FCFLAGS = @FCFLAGS@
 FGREP = @FGREP@
+FLOCK = @FLOCK@
 GREP = @GREP@
 HSA_RUNTIME_INCLUDE = @HSA_RUNTIME_INCLUDE@
 HSA_RUNTIME_LIB = @HSA_RUNTIME_LIB@
diff --git a/libgomp/configure b/libgomp/configure
index 85fdb4d3f48..b67b35a589c 100755
--- a/libgomp/configure
+++ b/libgomp/configure
@@ -656,6 +656,7 @@ tmake_file
 XLDFLAGS
 XCFLAGS
 config_path
+FLOCK
 CPU_COUNT
 LIBGOMP_BUILD_VERSIONED_SHLIB_SUN_FALSE
 LIBGOMP_BUILD_VERSIONED_SHLIB_SUN_TRUE
@@ -11431,7 +11432,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 11434 "configure"
+#line 11435 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -11537,7 +11538,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 11540 "configure"
+#line 11541 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -16663,6 +16664,49 @@ $as_echo "unable to detect (assuming 1)" >&6; }
 fi
 
 
+for ac_prog in flock
+do
+  # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_FLOCK+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$FLOCK"; then
+  ac_cv_prog_FLOCK="$FLOCK" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_FLOCK="$ac_prog"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+FLOCK=$ac_cv_prog_FLOCK
+if test -n "$FLOCK"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $FLOCK" >&5
+$as_echo "$FLOCK" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  test -n "$FLOCK" && break
+done
+
+
 # Get target configury.
 . ${srcdir}/configure.tgt
 CFLAGS="$save_CFLAGS $XCFLAGS"
diff --git a/libgomp/configure.ac b/libgomp/configure.ac
index a9b1f3973f7..0fab7168cfa 100644
--- a/libgomp/configure.ac
+++ b/libgomp/configure.ac
@@ -339,6 +339,8 @@ fi
 AX_COUNT_CPUS
 AC_SUBST(CPU_COUNT)
 
+AC_CHECK_PROGS(FLOCK, flock)
+
 # Get target configury.
 . ${srcdir}/configure.tgt
 CFLAGS="$save_CFLAGS $XCFLAGS"
diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am
index eef02f4a8c2..0cc91ccc4d1 100644
--- a/libgomp/testsuite/Makefile.am
+++ b/libgomp/testsuite/Makefile.am
@@ -73,7 +73,8 @@ check_p_numbers4:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_num
 check_p_numbers5:=$(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4)
 check_p_numbers6:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5)))
 check_p_numbers:=$(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6)
-gcc_test_parallel_slots:=1
+# If unable to serialize execution testing, use just one parallel slot.
+gcc_test_parallel_slots:=$(if $(FLOCK),$(if $(GCC_TEST_PARALLEL_SLOTS),$(GCC_TEST_PARALLEL_SLOTS),19),1)
 check_p_subdirs=$(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers))
 check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs))
 $(check_DEJAGNU_libgomp_targets): check-DEJAGNUlibgomp%: libgomp%/site.exp
diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in
index c29c16c1e7f..cd318e3c392 100644
--- a/libgomp/testsuite/Makefile.in
+++ b/libgomp/testsuite/Makefile.in
@@ -162,6 +162,7 @@ EXEEXT = @EXEEXT@
 FC = @FC@
 FCFLAGS = @FCFLAGS@
 FGREP = @FGREP@
+FLOCK = @FLOCK@
 GREP = @GREP@
 HSA_RUNTIME_INCLUDE = @HSA_RUNTIME_INCLUDE@
 HSA_RUNTIME_LIB = @HSA_RUNTIME_LIB@
@@ -320,7 +321,8 @@ check_p_numbers4 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_n
 check_p_numbers5 := $(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4)
 check_p_numbers6 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5)))
 check_p_numbers := $(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6)
-gcc_test_parallel_slots := 1
+# If unable to serialize execution testing, use just one parallel slot.
+gcc_test_parallel_slots := $(if $(FLOCK),$(if $(GCC_TEST_PARALLEL_SLOTS),$(GCC_TEST_PARALLEL_SLOTS),19),1)
 check_p_subdirs = $(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers))
 check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs))
 all: all-am
diff --git a/libgomp/testsuite/config/default.exp b/libgomp/testsuite/config/default.exp
index 7ac3f31d1a2..1c8c47bf13d 100644
--- a/libgomp/testsuite/config/default.exp
+++ b/libgomp/testsuite/config/default.exp
@@ -13,5 +13,3 @@
 # You should have received a copy of the GNU General Public License
 # along with this program; see the file COPYING3.  If not see
 # <http://www.gnu.org/licenses/>.
-
-load_lib "standard.exp"
diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp
index d1441593354..a88768f4e29 100644
--- a/libgomp/testsuite/lib/libgomp.exp
+++ b/libgomp/testsuite/lib/libgomp.exp
@@ -9,6 +9,7 @@ proc load_gcc_lib { filename } {
 }
 
 load_lib dg.exp
+load_lib standard.exp
 
 # Required to use gcc-dg.exp - however, the latter should NOT be
 # loaded until ${tool}_target_compile is defined since it uses that
@@ -324,6 +325,34 @@ proc libgomp_option_proc { option } {
     }
 }
 
+if ![info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] {
+    # No parallel testing.
+} elseif { $FLOCK == "" } {
+    # Using just one parallel slot.
+} else {
+    # Using several parallel slots.  Override DejaGnu
+    # 'standard.exp:${tool}_load'...
+    rename libgomp_load standard_libgomp_load
+    proc libgomp_load { program args } {
+	# ... in order to serialize execution testing via an exclusive lock.
+	set lock_file ../lock
+	set lock_kind --exclusive
+	set lock_fd [open $lock_file a+]
+	set lock_clock_begin [clock seconds]
+	global FLOCK
+	exec $FLOCK $lock_kind 0 <@ $lock_fd
+	set lock_clock_end [clock seconds]
+	verbose -log "Got ${FLOCK}('$lock_file', '$lock_kind') at [clock format $lock_clock_end] after [expr $lock_clock_end - $lock_clock_begin] s" 2
+
+	set result [standard_libgomp_load $program $args]
+
+	# Unlock (implicit with 'close').
+	close $lock_fd
+
+	return $result
+    }
+}
+
 # Translate offload target to OpenACC device type.  Return the empty string if
 # not supported, and 'host' for offload target 'disable'.
 proc offload_target_to_openacc_device_type { offload_target } {
diff --git a/libgomp/testsuite/libgomp-site-extra.exp.in b/libgomp/testsuite/libgomp-site-extra.exp.in
index c0d26660bad..0a3ba059c21 100644
--- a/libgomp/testsuite/libgomp-site-extra.exp.in
+++ b/libgomp/testsuite/libgomp-site-extra.exp.in
@@ -1 +1,2 @@
+set FLOCK {@FLOCK@}
 set GCC_UNDER_TEST {@CC@}

commit b4561b782427cdfe0fac1a869e79a49187817ffe
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Mon May 15 20:00:07 2023

    Support parallel testing in libgomp: fallback Perl 'flock' [PR66005]
    
    Follow-up to commit 6c3b30ef9e0578509bdaf59c13da4a212fe6c2ba
    "Support parallel testing in libgomp, part II [PR66005]"
    ("..., and enable if 'flock' is available for serializing execution testing"),
    where we saw:
    
    > On my Dell Precision 7530 laptop:
    >
    >     $ uname -srvi
    >     Linux 5.15.0-71-generic #78-Ubuntu SMP Tue Apr 18 09:00:29 UTC 2023 x86_64
    >     $ grep '^model name' < /proc/cpuinfo | uniq -c
    >          12 model name      : Intel(R) Core(TM) i7-8850H CPU @ 2.60GHz
    >     $ nvidia-smi -L
    >     GPU 0: Quadro P1000 (UUID: GPU-e043973b-b52a-d02b-c066-a8fdbf64e8ea)
    >
    > ... [...]: case (c) standard configuration, no offloading
    > configured, [...]
    
    >     $ \time make check-target-libgomp
    >
    > Case (c), baseline; [...]:
    >
    >     1180.98user 110.80system 19:36.40elapsed 109%CPU (0avgtext+0avgdata 505148maxresident)k
    >     1133.22user 111.08system 19:35.75elapsed 105%CPU (0avgtext+0avgdata 505212maxresident)k
    >
    > Case (c), parallelized [using 'flock']:
    >
    > [...]
    >     -j12 GCC_TEST_PARALLEL_SLOTS=12
    >     2591.04user 192.64system 4:44.98elapsed 976%CPU (0avgtext+0avgdata 505216maxresident)k
    >     2581.23user 195.21system 4:47.51elapsed 965%CPU (0avgtext+0avgdata 505212maxresident)k
    
    Quite the same when instead of 'flock' using this fallback Perl 'flock':
    
        2565.23user 194.35system 4:46.77elapsed 962%CPU (0avgtext+0avgdata 505216maxresident)k
        2549.38user 200.20system 4:46.08elapsed 961%CPU (0avgtext+0avgdata 505216maxresident)k
    
            PR testsuite/66005
            gcc/
            * doc/install.texi: Document (optional) Perl usage for parallel
            testing of libgomp.
            libgomp/
            * testsuite/lib/libgomp.exp: 'flock' through stdout.
            * testsuite/flock: New.
            * configure.ac (FLOCK): Point to that if no 'flock' available, but
            'perl' is.
            * configure: Regenerate.
    
    (cherry picked from commit 04abe1944d30eb18a2060cfcd9695d085f7b4752)

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 19d073256a9..d488b768987 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -375,6 +375,9 @@ tables.
 
 Used by @command{automake}.
 
+If available, enables parallel testing of @samp{libgomp} in case that
+@command{flock} is not available.
+
 @end table
 
 Several support libraries are necessary to build GCC, some are required,
diff --git a/libgomp/configure b/libgomp/configure
index b67b35a589c..be2c5a63d69 100755
--- a/libgomp/configure
+++ b/libgomp/configure
@@ -16664,6 +16664,8 @@ $as_echo "unable to detect (assuming 1)" >&6; }
 fi
 
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for flock implementation" >&5
+$as_echo "$as_me: checking for flock implementation" >&6;}
 for ac_prog in flock
 do
   # Extract the first word of "$ac_prog", so it can be a program name with args.
@@ -16706,6 +16708,46 @@ fi
   test -n "$FLOCK" && break
 done
 
+# Fallback if 'perl' is available.
+if test -z "$FLOCK"; then
+  # Extract the first word of "perl", so it can be a program name with args.
+set dummy perl; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_FLOCK+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$FLOCK"; then
+  ac_cv_prog_FLOCK="$FLOCK" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_FLOCK="$srcdir/testsuite/flock"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+FLOCK=$ac_cv_prog_FLOCK
+if test -n "$FLOCK"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $FLOCK" >&5
+$as_echo "$FLOCK" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
 
 # Get target configury.
 . ${srcdir}/configure.tgt
diff --git a/libgomp/configure.ac b/libgomp/configure.ac
index 0fab7168cfa..cc96e5b753b 100644
--- a/libgomp/configure.ac
+++ b/libgomp/configure.ac
@@ -339,7 +339,12 @@ fi
 AX_COUNT_CPUS
 AC_SUBST(CPU_COUNT)
 
+AC_MSG_NOTICE([checking for flock implementation])
 AC_CHECK_PROGS(FLOCK, flock)
+# Fallback if 'perl' is available.
+if test -z "$FLOCK"; then
+  AC_CHECK_PROG(FLOCK, perl, $srcdir/testsuite/flock)
+fi
 
 # Get target configury.
 . ${srcdir}/configure.tgt
diff --git a/libgomp/testsuite/flock b/libgomp/testsuite/flock
new file mode 100755
index 00000000000..71878b104f1
--- /dev/null
+++ b/libgomp/testsuite/flock
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+
+use strict;
+use warnings;
+
+# Only arguments '--exclusive 1' exactly are supported.
+(@ARGV == 2) or die;
+my $mode = shift;
+($mode eq "--exclusive") or die;
+my $fd = shift;
+($fd eq "1") or die;
+
+use Fcntl ':flock';
+
+open(my $fh, '>&=', 1) or die "open: $!";
+
+flock($fh, LOCK_EX) or die "flock: $!";
diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp
index a88768f4e29..17d173ac8d7 100644
--- a/libgomp/testsuite/lib/libgomp.exp
+++ b/libgomp/testsuite/lib/libgomp.exp
@@ -335,12 +335,14 @@ if ![info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] {
     rename libgomp_load standard_libgomp_load
     proc libgomp_load { program args } {
 	# ... in order to serialize execution testing via an exclusive lock.
+	# We use stdout, as per <https://perldoc.perl.org/functions/flock>
+	# "[...] FILEHANDLE [...] be open with write intent to use LOCK_EX".
 	set lock_file ../lock
 	set lock_kind --exclusive
 	set lock_fd [open $lock_file a+]
 	set lock_clock_begin [clock seconds]
 	global FLOCK
-	exec $FLOCK $lock_kind 0 <@ $lock_fd
+	exec $FLOCK $lock_kind 1 >@ $lock_fd
 	set lock_clock_end [clock seconds]
 	verbose -log "Got ${FLOCK}('$lock_file', '$lock_kind') at [clock format $lock_clock_end] after [expr $lock_clock_end - $lock_clock_begin] s" 2
 

commit c6f1968b85aa5a0952ec5fab88982ff4c7e3cce8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 29 02:21:03 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 12a489ae62d..de477f96275 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2023-06-28  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2023-06-02  Thomas Schwinge  <thomas@codesourcery.com>
+
+	PR testsuite/66005
+	* doc/install.texi: Document (optional) Perl usage for parallel
+	testing of libgomp.
+
+2023-06-28  liuhongt  <hongtao.liu@intel.com>
+
+	* config/i386/i386-features.cc (pass_insert_vzeroupper:gate):
+	Move flag_expensive_optimizations && !optimize_size to ..
+	* config/i386/i386-options.cc (ix86_option_override_internal):
+	.. this, it makes -mvzeroupper independent of optimization
+	level, but still keeps the behavior of architecture
+	tuning(emit_vzeroupper) unchanged.
+
 2023-06-27  Andrew Pinski  <apinski@marvell.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index fff3166d023..d3dd503874a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230628
+20230629
diff --git a/gcc/go/ChangeLog b/gcc/go/ChangeLog
index 9d5675465a7..e0df7a5dfeb 100644
--- a/gcc/go/ChangeLog
+++ b/gcc/go/ChangeLog
@@ -1,3 +1,11 @@
+2023-06-28  Paul E. Murphy  <murphyp@linux.ibm.com>
+
+	Backported from master:
+	2023-06-22  Paul E. Murphy  <murphyp@linux.ibm.com>
+
+	* go-backend.cc [TARGET_AIX]: Rename and update usage to TARGET_AIX_OS.
+	* go-lang.cc: Likewise.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 960594bcc9e..cdfe12ff55e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2023-06-28  liuhongt  <hongtao.liu@intel.com>
+
+	* gcc.target/i386/avx-vzeroupper-29.c: New testcase.
+	* gcc.target/i386/avx-vzeroupper-12.c: Adjust testcase.
+	* gcc.target/i386/avx-vzeroupper-7.c: Ditto.
+	* gcc.target/i386/avx-vzeroupper-9.c: Ditto.
+
 2023-06-27  Andrew Pinski  <apinski@marvell.com>
 
 	Backported from master:
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 8962addec63..ba7c0ade8f4 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,61 @@
+2023-06-28  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2023-06-02  Thomas Schwinge  <thomas@codesourcery.com>
+
+	PR testsuite/66005
+	* testsuite/lib/libgomp.exp: 'flock' through stdout.
+	* testsuite/flock: New.
+	* configure.ac (FLOCK): Point to that if no 'flock' available, but
+	'perl' is.
+	* configure: Regenerate.
+
+2023-06-28  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2023-05-15  Thomas Schwinge  <thomas@codesourcery.com>
+
+	PR testsuite/66005
+	* configure.ac: Look for 'flock'.
+	* testsuite/Makefile.am (gcc_test_parallel_slots): Enable parallel testing.
+	* testsuite/config/default.exp: Don't 'load_lib "standard.exp"' here...
+	* testsuite/lib/libgomp.exp: ... but here, instead.
+	(libgomp_load): Override for parallel testing.
+	* testsuite/libgomp-site-extra.exp.in (FLOCK): Set.
+	* configure: Regenerate.
+	* Makefile.in: Regenerate.
+	* testsuite/Makefile.in: Regenerate.
+
+2023-06-28  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	Backported from master:
+	2023-05-15  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+		    Thomas Schwinge  <thomas@codesourcery.com>
+
+	PR testsuite/66005
+	* testsuite/Makefile.am (PWD_COMMAND): New variable.
+	(%/site.exp): New target.
+	(check_p_numbers0, check_p_numbers1, check_p_numbers2)
+	(check_p_numbers3, check_p_numbers4, check_p_numbers5)
+	(check_p_numbers6, check_p_numbers, gcc_test_parallel_slots)
+	(check_p_subdirs)
+	(check_DEJAGNU_libgomp_targets): New variables.
+	($(check_DEJAGNU_libgomp_targets)): New target.
+	($(check_DEJAGNU_libgomp_targets)): New dependency.
+	(check-DEJAGNU $(check_DEJAGNU_libgomp_targets)): New targets.
+	* testsuite/Makefile.in: Regenerate.
+	* testsuite/lib/libgomp.exp: For parallel testing,
+	'load_file ../libgomp-test-support.exp'.
+
+2023-06-28  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2023-05-08  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* testsuite/libgomp.c++/c++.exp: Use 'lang_include_flags' instead
+	of 'libstdcxx_includes'.
+	* testsuite/libgomp.oacc-c++/c++.exp: Likewise.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.

commit ff54abd2beebaa309762603bb7bf8f46ea530388
Author: Hongyu Wang <hongyu.wang@intel.com>
Date:   Sun Jun 25 03:50:21 2023

    i386: Sync tune_string with arch_string for target attribute arch=*
    
    For function with target attribute arch=*, current logic will set its
    tune to -mtune from command line so all target_clones will get same
    tuning flags which would affect the performance for each clone. Override
    tune with arch if tune was not explicitly specified to get proper tuning
    flags for target_clones.
    
    gcc/ChangeLog:
    
            * config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
            Override tune_string with arch_string if tune_string is not
            explicitly specified.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/mvc17.c: New test.
    
    (cherry picked from commit 2916278d14e9ac28c361c396a67256acbebda6e8)

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 70ddcd284c4..27d16986a2f 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1378,7 +1378,11 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
       if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
 	opts->x_ix86_tune_string
 	  = ggc_strdup (option_strings[IX86_FUNCTION_SPECIFIC_TUNE]);
-      else if (orig_tune_defaulted)
+      /* If we have explicit arch string and no tune string specified, set
+	 tune_string to NULL and later it will be overriden by arch_string
+	 so target clones can get proper optimization.  */
+      else if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
+	       || orig_tune_defaulted)
 	opts->x_ix86_tune_string = NULL;
 
       /* If fpmath= is not set, and we now have sse2 on 32-bit, use it.  */
diff --git a/gcc/testsuite/gcc.target/i386/mvc17.c b/gcc/testsuite/gcc.target/i386/mvc17.c
new file mode 100644
index 00000000000..8b83c1aecb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mvc17.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-ifunc "" } */
+/* { dg-options "-O2 -march=x86-64" } */
+/* { dg-final { scan-assembler-times "rep mov" 1 } } */
+
+__attribute__((target_clones("default","arch=icelake-server")))
+void
+foo (char *a, char *b, int size)
+{
+  __builtin_memcpy (a, b, size & 0x7F);
+}

commit 1f5591a9578b8cacda9d4c73a25d93598d68e028
Author: liuhongt <hongtao.liu@intel.com>
Date:   Tue Jun 20 09:41:00 2023

    Refine maskloadmn pattern with UNSPEC_MASKLOAD.
    
    If mem_addr points to a memory region with less than whole vector size
    bytes of accessible memory and k is a mask that would prevent reading
    the inaccessible bytes from mem_addr, add UNSPEC_MASKLOAD to prevent
    it to be transformed to vpblendd.
    
    gcc/ChangeLog:
    
            PR target/110309
            * config/i386/sse.md (maskload<mode><avx512fmaskmodelower>):
            Refine pattern with UNSPEC_MASKLOAD.
            (maskload<mode><avx512fmaskmodelower>): Ditto.
            (*<avx512>_load<mode>_mask): Extend mode iterator to
            VI12HF_AVX512VL.
            (*<avx512>_load<mode>): Ditto.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/pr110309.c: New test.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index eb767e56ca4..b30e96cb1ab 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1411,12 +1411,12 @@
 })
 
 (define_insn "*<avx512>_load<mode>_mask"
-  [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI12_AVX512VL
-	  (unspec:VI12_AVX512VL
-	    [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")]
+  [(set (match_operand:VI12HF_AVX512VL 0 "register_operand" "=v")
+	(vec_merge:VI12HF_AVX512VL
+	  (unspec:VI12HF_AVX512VL
+	    [(match_operand:VI12HF_AVX512VL 1 "memory_operand" "m")]
 	    UNSPEC_MASKLOAD)
-	  (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C")
+	  (match_operand:VI12HF_AVX512VL 2 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
   "TARGET_AVX512BW"
   "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
@@ -1425,9 +1425,9 @@
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn_and_split "*<avx512>_load<mode>"
-  [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
-	(unspec:VI12_AVX512VL
-	  [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")]
+  [(set (match_operand:VI12HF_AVX512VL 0 "register_operand" "=v")
+	(unspec:VI12HF_AVX512VL
+	  [(match_operand:VI12HF_AVX512VL 1 "memory_operand" "m")]
 	  UNSPEC_MASKLOAD))]
   "TARGET_AVX512BW"
   "#"
@@ -25973,17 +25973,21 @@
   "TARGET_AVX")
 
 (define_expand "maskload<mode><avx512fmaskmodelower>"
-  [(set (match_operand:V48H_AVX512VL 0 "register_operand")
-	(vec_merge:V48H_AVX512VL
-	  (match_operand:V48H_AVX512VL 1 "memory_operand")
+  [(set (match_operand:V48_AVX512VL 0 "register_operand")
+	(vec_merge:V48_AVX512VL
+	  (unspec:V48_AVX512VL
+	    [(match_operand:V48_AVX512VL 1 "memory_operand")]
+	    UNSPEC_MASKLOAD)
 	  (match_dup 0)
 	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
   "TARGET_AVX512F")
 
 (define_expand "maskload<mode><avx512fmaskmodelower>"
-  [(set (match_operand:VI12_AVX512VL 0 "register_operand")
-	(vec_merge:VI12_AVX512VL
-	  (match_operand:VI12_AVX512VL 1 "memory_operand")
+  [(set (match_operand:VI12HF_AVX512VL 0 "register_operand")
+	(vec_merge:VI12HF_AVX512VL
+	  (unspec:VI12HF_AVX512VL
+	    [(match_operand:VI12HF_AVX512VL 1 "memory_operand")]
+	    UNSPEC_MASKLOAD)
 	  (match_dup 0)
 	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
   "TARGET_AVX512BW")
diff --git a/gcc/testsuite/gcc.target/i386/pr110309.c b/gcc/testsuite/gcc.target/i386/pr110309.c
new file mode 100644
index 00000000000..f6e9e9c3c61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr110309.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 --param vect-partial-vector-usage=1 -march=znver4 -mprefer-vector-width=256" } */
+/* { dg-final { scan-assembler-not {(?n)vpblendd.*ymm} } } */
+
+
+void foo (int * __restrict a, int *b)
+{
+  for (int i = 0; i < 6; ++i)
+    a[i] = b[i] + 42;
+}

commit a435939ba7e5e489a422071014f943c1a577bfe6
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Jun 26 15:07:09 2023

    Refine maskstore patterns with UNSPEC_MASKMOV.
    
    Similar like r14-2070-gc79476da46728e
    
    If mem_addr points to a memory region with less than whole vector size
    bytes of accessible memory and k is a mask that would prevent reading
    the inaccessible bytes from mem_addr, add UNSPEC_MASKMOV to prevent
    it to be transformed to any other whole memory access instructions.
    
    gcc/ChangeLog:
    
            PR rtl-optimization/110237
            * config/i386/sse.md (<avx512>_store<mode>_mask): Refine with
            UNSPEC_MASKMOV.
            (maskstore<mode><avx512fmaskmodelower): Ditto.
            (*<avx512>_store<mode>_mask): New define_insn, it's renamed
            from original <avx512>_store<mode>_mask.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b30e96cb1ab..3af15989631 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1554,7 +1554,7 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "<avx512>_store<mode>_mask"
+(define_insn "*<avx512>_store<mode>_mask"
   [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m")
 	(vec_merge:V48_AVX512VL
 	  (match_operand:V48_AVX512VL 1 "register_operand" "v")
@@ -1582,7 +1582,7 @@
    (set_attr "memory" "store")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "<avx512>_store<mode>_mask"
+(define_insn "*<avx512>_store<mode>_mask"
   [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand" "=m")
 	(vec_merge:VI12HF_AVX512VL
 	  (match_operand:VI12HF_AVX512VL 1 "register_operand" "v")
@@ -26002,21 +26002,66 @@
   "TARGET_AVX")
 
 (define_expand "maskstore<mode><avx512fmaskmodelower>"
-  [(set (match_operand:V48H_AVX512VL 0 "memory_operand")
-	(vec_merge:V48H_AVX512VL
-	  (match_operand:V48H_AVX512VL 1 "register_operand")
-	  (match_dup 0)
-	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
+  [(set (match_operand:V48_AVX512VL 0 "memory_operand")
+	(unspec:V48_AVX512VL
+	  [(match_operand:V48_AVX512VL 1 "register_operand")
+	   (match_dup 0)
+	   (match_operand:<avx512fmaskmode> 2 "register_operand")]
+	  UNSPEC_MASKMOV))]
   "TARGET_AVX512F")
 
 (define_expand "maskstore<mode><avx512fmaskmodelower>"
-  [(set (match_operand:VI12_AVX512VL 0 "memory_operand")
-	(vec_merge:VI12_AVX512VL
-	  (match_operand:VI12_AVX512VL 1 "register_operand")
-	  (match_dup 0)
-	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
+  [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand")
+	(unspec:VI12HF_AVX512VL
+	  [(match_operand:VI12HF_AVX512VL 1 "register_operand")
+	   (match_dup 0)
+	   (match_operand:<avx512fmaskmode> 2 "register_operand")]
+	  UNSPEC_MASKMOV))]
   "TARGET_AVX512BW")
 
+(define_insn "<avx512>_store<mode>_mask"
+  [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m")
+	(unspec:V48_AVX512VL
+	  [(match_operand:V48_AVX512VL 1 "register_operand" "v")
+	   (match_dup 0)
+	   (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")]
+	  UNSPEC_MASKMOV))]
+  "TARGET_AVX512F"
+{
+  if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode)))
+    {
+      if (misaligned_operand (operands[0], <MODE>mode))
+	return "vmovu<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
+      else
+	return "vmova<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
+    }
+  else
+    {
+      if (misaligned_operand (operands[0], <MODE>mode))
+	return "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
+      else
+	return "vmovdqa<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
+    }
+}
+  [(set_attr "type" "ssemov")
+   (set_attr "prefix" "evex")
+   (set_attr "memory" "store")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "<avx512>_store<mode>_mask"
+  [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand" "=m")
+	(unspec:VI12HF_AVX512VL
+	  [(match_operand:VI12HF_AVX512VL 1 "register_operand" "v")
+	   (match_dup 0)
+	   (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")]
+	   UNSPEC_MASKMOV))]
+  "TARGET_AVX512BW"
+  "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
+  [(set_attr "type" "ssemov")
+   (set_attr "prefix" "evex")
+   (set_attr "memory" "store")
+   (set_attr "mode" "<sseinsnmode>")])
+
 (define_expand "cbranch<mode>4"
   [(set (reg:CC FLAGS_REG)
 	(compare:CC (match_operand:VI48_AVX 1 "register_operand")

commit 1fb30818cf4eaa5f4cdf46dfc3b0c02dce8cd21e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 30 02:20:49 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index de477f96275..fac7bf6f173 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,31 @@
+2023-06-29  liuhongt  <hongtao.liu@intel.com>
+
+	PR rtl-optimization/110237
+	* config/i386/sse.md (<avx512>_store<mode>_mask): Refine with
+	UNSPEC_MASKMOV.
+	(maskstore<mode><avx512fmaskmodelower): Ditto.
+	(*<avx512>_store<mode>_mask): New define_insn, it's renamed
+	from original <avx512>_store<mode>_mask.
+
+2023-06-29  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/110309
+	* config/i386/sse.md (maskload<mode><avx512fmaskmodelower>):
+	Refine pattern with UNSPEC_MASKLOAD.
+	(maskload<mode><avx512fmaskmodelower>): Ditto.
+	(*<avx512>_load<mode>_mask): Extend mode iterator to
+	VI12HF_AVX512VL.
+	(*<avx512>_load<mode>): Ditto.
+
+2023-06-29  Hongyu Wang  <hongyu.wang@intel.com>
+
+	Backported from master:
+	2023-06-26  Hongyu Wang  <hongyu.wang@intel.com>
+
+	* config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
+	Override tune_string with arch_string if tune_string is not
+	explicitly specified.
+
 2023-06-28  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d3dd503874a..e742d0ec698 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230629
+20230630
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cdfe12ff55e..25926032b87 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2023-06-29  liuhongt  <hongtao.liu@intel.com>
+
+	* gcc.target/i386/pr110309.c: New test.
+
+2023-06-29  Hongyu Wang  <hongyu.wang@intel.com>
+
+	Backported from master:
+	2023-06-26  Hongyu Wang  <hongyu.wang@intel.com>
+
+	* gcc.target/i386/mvc17.c: New test.
+
 2023-06-28  liuhongt  <hongtao.liu@intel.com>
 
 	* gcc.target/i386/avx-vzeroupper-29.c: New testcase.

commit d972c592b33ec81be55539d3c524986190ed2d8a
Author: Eric Botcazou <ebotcazou@adacore.com>
Date:   Fri Jun 30 18:05:34 2023

    Fix couple of endianness issues in fold_ctor_reference
    
    fold_ctor_reference attempts to use a recursive local processing in order
    to call native_encode_expr on the leaf nodes of the constructor, before
    falling back to calling native_encode_initializer if this fails.
    
    There are a couple of issues related to endianness present in it:
      1) it does not specifically handle integral bit-fields; now these are left
    justified on big-endian platforms so cannot be treated like ordinary fields.
      2) it does not check that the constructor uses the native storage order.
    
    gcc/
            * gimple-fold.cc (fold_array_ctor_reference): Fix head comment.
            (fold_nonarray_ctor_reference): Likewise.  Specifically deal
            with integral bit-fields.
            (fold_ctor_reference): Make sure that the constructor uses the
            native storage order.
    
    gcc/testsuite/
            * gcc.c-torture/execute/20230630-1.c: New test.
            * gcc.c-torture/execute/20230630-2.c: Likewise.
            * gcc.c-torture/execute/20230630-3.c: Likewise
            * gcc.c-torture/execute/20230630-4.c: Likewise

diff --git a/gcc/gimple-fold.cc b/gcc/gimple-fold.cc
index 863ee3d3912..010be0b2b89 100644
--- a/gcc/gimple-fold.cc
+++ b/gcc/gimple-fold.cc
@@ -7770,12 +7770,11 @@ get_base_constructor (tree base, poly_int64_pod *bit_offset,
     }
 }
 
-/* CTOR is CONSTRUCTOR of an array type.  Fold a reference of SIZE bits
-   to the memory at bit OFFSET.     When non-null, TYPE is the expected
-   type of the reference; otherwise the type of the referenced element
-   is used instead. When SIZE is zero, attempt to fold a reference to
-   the entire element which OFFSET refers to.  Increment *SUBOFF by
-   the bit offset of the accessed element.  */
+/* CTOR is a CONSTRUCTOR of an array or vector type.  Fold a reference of SIZE
+   bits to the memory at bit OFFSET.  If non-null, TYPE is the expected type of
+   the reference; otherwise the type of the referenced element is used instead.
+   When SIZE is zero, attempt to fold a reference to the entire element OFFSET
+   refers to.  Increment *SUBOFF by the bit offset of the accessed element.  */
 
 static tree
 fold_array_ctor_reference (tree type, tree ctor,
@@ -7940,13 +7939,11 @@ fold_array_ctor_reference (tree type, tree ctor,
   return type ? build_zero_cst (type) : NULL_TREE;
 }
 
-/* CTOR is CONSTRUCTOR of an aggregate or vector.  Fold a reference
-   of SIZE bits to the memory at bit OFFSET.   When non-null, TYPE
-   is the expected type of the reference; otherwise the type of
-   the referenced member is used instead.  When SIZE is zero,
-   attempt to fold a reference to the entire member which OFFSET
-   refers to; in this case.  Increment *SUBOFF by the bit offset
-   of the accessed member.  */
+/* CTOR is a CONSTRUCTOR of a record or union type.  Fold a reference of SIZE
+   bits to the memory at bit OFFSET.  If non-null, TYPE is the expected type of
+   the reference; otherwise the type of the referenced member is used instead.
+   When SIZE is zero, attempt to fold a reference to the entire member OFFSET
+   refers to.  Increment *SUBOFF by the bit offset of the accessed member.  */
 
 static tree
 fold_nonarray_ctor_reference (tree type, tree ctor,
@@ -7958,8 +7955,7 @@ fold_nonarray_ctor_reference (tree type, tree ctor,
   unsigned HOST_WIDE_INT cnt;
   tree cfield, cval;
 
-  FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), cnt, cfield,
-			    cval)
+  FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), cnt, cfield, cval)
     {
       tree byte_offset = DECL_FIELD_OFFSET (cfield);
       tree field_offset = DECL_FIELD_BIT_OFFSET (cfield);
@@ -8031,6 +8027,19 @@ fold_nonarray_ctor_reference (tree type, tree ctor,
 	    return NULL_TREE;
 
 	  offset_int inner_offset = offset_int (offset) - bitoffset;
+
+	  /* Integral bit-fields are left-justified on big-endian targets, so
+	     we must arrange for native_encode_int to start at their MSB.  */
+	  if (DECL_BIT_FIELD (cfield) && INTEGRAL_TYPE_P (TREE_TYPE (cfield)))
+	    {
+	      if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
+		return NULL_TREE;
+	      const unsigned int encoding_size
+		= GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE (TREE_TYPE (cfield)));
+	      if (BYTES_BIG_ENDIAN)
+		inner_offset += encoding_size - wi::to_offset (field_size);
+	    }
+
 	  return fold_ctor_reference (type, cval,
 				      inner_offset.to_uhwi (), size,
 				      from_decl, suboff);
@@ -8043,7 +8052,7 @@ fold_nonarray_ctor_reference (tree type, tree ctor,
   return build_zero_cst (type);
 }
 
-/* CTOR is value initializing memory.  Fold a reference of TYPE and
+/* CTOR is a value initializing memory.  Fold a reference of TYPE and
    bit size POLY_SIZE to the memory at bit POLY_OFFSET.  When POLY_SIZE
    is zero, attempt to fold a reference to the entire subobject
    which OFFSET refers to.  This is used when folding accesses to
@@ -8084,7 +8093,8 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset,
 	}
       return ret;
     }
-  /* For constants and byte-aligned/sized reads try to go through
+
+  /* For constants and byte-aligned/sized reads, try to go through
      native_encode/interpret.  */
   if (CONSTANT_CLASS_P (ctor)
       && BITS_PER_UNIT == 8
@@ -8100,7 +8110,12 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset,
       if (len > 0)
 	return native_interpret_expr (type, buf, len);
     }
-  if (TREE_CODE (ctor) == CONSTRUCTOR)
+
+  /* For constructors, try first a recursive local processing, but in any case
+     this requires the native storage order.  */
+  if (TREE_CODE (ctor) == CONSTRUCTOR
+      && !(AGGREGATE_TYPE_P (TREE_TYPE (ctor))
+	   && TYPE_REVERSE_STORAGE_ORDER (TREE_TYPE (ctor))))
     {
       unsigned HOST_WIDE_INT dummy = 0;
       if (!suboff)
@@ -8115,9 +8130,9 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset,
 	ret = fold_nonarray_ctor_reference (type, ctor, offset, size,
 					    from_decl, suboff);
 
-      /* Fall back to native_encode_initializer.  Needs to be done
-	 only in the outermost fold_ctor_reference call (because it itself
-	 recurses into CONSTRUCTORs) and doesn't update suboff.  */
+      /* Otherwise fall back to native_encode_initializer.  This may be done
+	 only from the outermost fold_ctor_reference call (because it itself
+	 recurses into CONSTRUCTORs and doesn't update suboff).  */
       if (ret == NULL_TREE
 	  && suboff == &dummy
 	  && BITS_PER_UNIT == 8
diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-1.c b/gcc/testsuite/gcc.c-torture/execute/20230630-1.c
new file mode 100644
index 00000000000..7c1f15c177f
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20230630-1.c
@@ -0,0 +1,23 @@
+struct S {
+  short int i : 12;
+  char c1 : 1;
+  char c2 : 1;
+  char c3 : 1;
+  char c4 : 1;
+};
+
+int main (void)
+{
+  struct S s0 = { 341, 1, 1, 1, 1 };
+  char *p = (char *) &s0;
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  if (*p != 85)
+    __builtin_abort ();
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+  if (*p != 21)
+    __builtin_abort ();
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-2.c b/gcc/testsuite/gcc.c-torture/execute/20230630-2.c
new file mode 100644
index 00000000000..c05c1666516
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20230630-2.c
@@ -0,0 +1,29 @@
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define REVERSE_SSO __attribute__((scalar_storage_order("big-endian")));
+#else
+#define REVERSE_SSO __attribute__((scalar_storage_order("little-endian")));
+#endif
+
+struct S {
+  short int i : 12;
+  char c1 : 1;
+  char c2 : 1;
+  char c3 : 1;
+  char c4 : 1;
+} REVERSE_SSO;
+
+int main (void)
+{
+  struct S s0 = { 341, 1, 1, 1, 1 };
+  char *p = (char *) &s0;
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  if (*p != 21)
+    __builtin_abort ();
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+  if (*p != 85)
+    __builtin_abort ();
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-3.c b/gcc/testsuite/gcc.c-torture/execute/20230630-3.c
new file mode 100644
index 00000000000..fc106c97b5b
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20230630-3.c
@@ -0,0 +1,27 @@
+struct S {
+  int i : 24;
+  char c1 : 1;
+  char c2 : 1;
+  char c3 : 1;
+  char c4 : 1;
+  char c5 : 1;
+  char c6 : 1;
+  char c7 : 1;
+  char c8 : 1;
+};
+
+int main (void)
+{
+  struct S s0 = { 1193046, 1, 1, 1, 1, 1, 1, 1, 1 };
+  char *p = (char *) &s0;
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  if (*p != 86)
+    __builtin_abort ();
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+  if (*p != 18)
+    __builtin_abort ();
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-4.c b/gcc/testsuite/gcc.c-torture/execute/20230630-4.c
new file mode 100644
index 00000000000..df33c18a8cd
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20230630-4.c
@@ -0,0 +1,33 @@
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define REVERSE_SSO __attribute__((scalar_storage_order("big-endian")));
+#else
+#define REVERSE_SSO __attribute__((scalar_storage_order("little-endian")));
+#endif
+
+struct S {
+  int i : 24;
+  char c1 : 1;
+  char c2 : 1;
+  char c3 : 1;
+  char c4 : 1;
+  char c5 : 1;
+  char c6 : 1;
+  char c7 : 1;
+  char c8 : 1;
+} REVERSE_SSO;
+
+int main (void)
+{
+  struct S s0 = { 1193046, 1, 1, 1, 1, 1, 1, 1, 1 };
+  char *p = (char *) &s0;
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  if (*p != 18)
+    __builtin_abort ();
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+  if (*p != 86)
+    __builtin_abort ();
+#endif
+
+  return 0;
+}

commit 3fd9e4742a943d358d326afbba90a807ef5f374f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 1 02:22:01 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fac7bf6f173..619ad3f14e6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2023-06-30  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gimple-fold.cc (fold_array_ctor_reference): Fix head comment.
+	(fold_nonarray_ctor_reference): Likewise.  Specifically deal
+	with integral bit-fields.
+	(fold_ctor_reference): Make sure that the constructor uses the
+	native storage order.
+
 2023-06-29  liuhongt  <hongtao.liu@intel.com>
 
 	PR rtl-optimization/110237
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e742d0ec698..41f22081742 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230630
+20230701
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 25926032b87..f5663000107 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2023-06-30  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gcc.c-torture/execute/20230630-1.c: New test.
+	* gcc.c-torture/execute/20230630-2.c: Likewise.
+	* gcc.c-torture/execute/20230630-3.c: Likewise
+	* gcc.c-torture/execute/20230630-4.c: Likewise
+
 2023-06-29  liuhongt  <hongtao.liu@intel.com>
 
 	* gcc.target/i386/pr110309.c: New test.

commit 750526ee180ae2af66ee07db95c9787e8d86ed4b
Author: Iain Buclaw <ibuclaw@gdcproject.org>
Date:   Sat Jul 1 23:32:53 2023

    d: Fix accesses of immutable arrays using constant index still bounds checked
    
    Starts setting TREE_READONLY against specific kinds of VAR_DECLs, so
    that the middle-end/optimization passes can more aggressively constant
    fold D code that makes use of `immutable' or `const'.
    
            PR d/110514
    
    gcc/d/ChangeLog:
    
            * decl.cc (get_symbol_decl): Set TREE_READONLY on certain kinds of
            const and immutable variables.
            * expr.cc (ExprVisitor::visit (ArrayLiteralExp *)): Set TREE_READONLY
            on immutable dynamic array literals.
    
    gcc/testsuite/ChangeLog:
    
            * gdc.dg/pr110514a.d: New test.
            * gdc.dg/pr110514b.d: New test.
            * gdc.dg/pr110514c.d: New test.
            * gdc.dg/pr110514d.d: New test.
    
    (cherry picked from commit 61b1c562f8c703bff045e91257120e42b7fae523)

diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc
index 1cdfc24666e..de1dfd14189 100644
--- a/gcc/d/decl.cc
+++ b/gcc/d/decl.cc
@@ -1264,6 +1264,20 @@ get_symbol_decl (Declaration *decl)
 		DECL_INITIAL (decl->csym) = build_expr (ie, true);
 	    }
 	}
+
+      /* [type-qualifiers/const-and-immutable]
+
+	 `immutable` applies to data that cannot change. Immutable data values,
+	 once constructed, remain the same for the duration of the program's
+	 execution.  */
+      if (vd->isImmutable () && !vd->setInCtorOnly ())
+	TREE_READONLY (decl->csym) = 1;
+
+      /* `const` applies to data that cannot be changed by the const reference
+	 to that data. It may, however, be changed by another reference to that
+	 same data.  */
+      if (vd->isConst () && !vd->isDataseg ())
+	TREE_READONLY (decl->csym) = 1;
     }
 
   /* Set the declaration mangled identifier if static.  */
diff --git a/gcc/d/expr.cc b/gcc/d/expr.cc
index 6654244292e..46d94f81fa2 100644
--- a/gcc/d/expr.cc
+++ b/gcc/d/expr.cc
@@ -2708,6 +2708,10 @@ public:
 	    if (tb->ty == TY::Tarray)
 	      ctor = d_array_value (type, size_int (e->elements->length), ctor);
 
+	    /* Immutable literals can be placed in rodata.  */
+	    if (tb->isImmutable ())
+	      TREE_READONLY (decl) = 1;
+
 	    d_pushdecl (decl);
 	    rest_of_decl_compilation (decl, 1, 0);
 	  }
diff --git a/gcc/testsuite/gdc.dg/pr110514a.d b/gcc/testsuite/gdc.dg/pr110514a.d
new file mode 100644
index 00000000000..46e370527d3
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr110514a.d
@@ -0,0 +1,9 @@
+// { dg-do "compile" }
+// { dg-options "-O -fdump-tree-optimized" }
+immutable uint[] imm_arr = [1,2,3];
+int test_imm(immutable uint[] ptr)
+{
+    return imm_arr[2] == 3 ? 123 : 456;
+}
+// { dg-final { scan-assembler-not "_d_arraybounds_indexp" } }
+// { dg-final { scan-tree-dump "return 123;" optimized } }
diff --git a/gcc/testsuite/gdc.dg/pr110514b.d b/gcc/testsuite/gdc.dg/pr110514b.d
new file mode 100644
index 00000000000..86aeb485c34
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr110514b.d
@@ -0,0 +1,8 @@
+// { dg-do "compile" }
+// { dg-options "-O" }
+immutable uint[] imm_ctor_arr;
+int test_imm_ctor(immutable uint[] ptr)
+{
+    return imm_ctor_arr[2] == 3;
+}
+// { dg-final { scan-assembler "_d_arraybounds_indexp" } }
diff --git a/gcc/testsuite/gdc.dg/pr110514c.d b/gcc/testsuite/gdc.dg/pr110514c.d
new file mode 100644
index 00000000000..94779e123a4
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr110514c.d
@@ -0,0 +1,8 @@
+// { dg-do "compile" }
+// { dg-options "-O" }
+const uint[] cst_arr = [1,2,3];
+int test_cst(const uint[] ptr)
+{
+    return cst_arr[2] == 3;
+}
+// { dg-final { scan-assembler "_d_arraybounds_indexp" } }
diff --git a/gcc/testsuite/gdc.dg/pr110514d.d b/gcc/testsuite/gdc.dg/pr110514d.d
new file mode 100644
index 00000000000..56e9a3139ea
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr110514d.d
@@ -0,0 +1,8 @@
+// { dg-do "compile" }
+// { dg-options "-O" }
+const uint[] cst_ctor_arr;
+int test_cst_ctor(const uint[] ptr)
+{
+    return cst_ctor_arr[2] == 3;
+}
+// { dg-final { scan-assembler "_d_arraybounds_indexp" } }

commit 6f47eb40bdbb7690bcf8faa505c3200fae5fe7b8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 2 02:19:38 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 41f22081742..ae3ab38a574 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230701
+20230702
diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog
index 9f7e4b0545e..17c5f25cacb 100644
--- a/gcc/d/ChangeLog
+++ b/gcc/d/ChangeLog
@@ -1,3 +1,14 @@
+2023-07-01  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-07-01  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110514
+	* decl.cc (get_symbol_decl): Set TREE_READONLY on certain kinds of
+	const and immutable variables.
+	* expr.cc (ExprVisitor::visit (ArrayLiteralExp *)): Set TREE_READONLY
+	on immutable dynamic array literals.
+
 2023-06-26  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f5663000107..6b424d9d717 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2023-07-01  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-07-01  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110514
+	* gdc.dg/pr110514a.d: New test.
+	* gdc.dg/pr110514b.d: New test.
+	* gdc.dg/pr110514c.d: New test.
+	* gdc.dg/pr110514d.d: New test.
+
 2023-06-30  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gcc.c-torture/execute/20230630-1.c: New test.

commit b224692084e40aabcba1e73166eedf55dfd7f563
Author: Iain Buclaw <ibuclaw@gdcproject.org>
Date:   Sun Jul 2 03:24:53 2023

    d: Fix core.volatile.volatileLoad discarded if result is unused
    
    The first pass of code generation in the D front-end splits up all
    compound expressions and discards expressions that have no side effects.
    This included calls to the `volatileLoad' intrinsic if its result was
    not used, causing such calls to be eliminated from the program.
    
    We already set TREE_THIS_VOLATILE on the expression, however the
    tree documentation says if this bit is set in an expression, so is
    TREE_SIDE_EFFECTS.  So set TREE_SIDE_EFFECTS on the expression too.
    This prevents any early discarding from occuring.
    
            PR d/110516
    
    gcc/d/ChangeLog:
    
            * intrinsics.cc (expand_volatile_load): Set TREE_SIDE_EFFECTS on the
            expanded expression.
            (expand_volatile_store): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gdc.dg/torture/pr110516a.d: New test.
            * gdc.dg/torture/pr110516b.d: New test.
    
    (cherry picked from commit 80ae426a195a0d035640a6301da833564deade52)

diff --git a/gcc/d/intrinsics.cc b/gcc/d/intrinsics.cc
index 4222b8a0290..8ec94a6b8f9 100644
--- a/gcc/d/intrinsics.cc
+++ b/gcc/d/intrinsics.cc
@@ -721,6 +721,7 @@ expand_volatile_load (tree callexp)
   tree type = build_qualified_type (TREE_TYPE (ptrtype), TYPE_QUAL_VOLATILE);
   tree result = indirect_ref (type, ptr);
   TREE_THIS_VOLATILE (result) = 1;
+  TREE_SIDE_EFFECTS (result) = 1;
 
   return result;
 }
@@ -748,6 +749,7 @@ expand_volatile_store (tree callexp)
   tree type = build_qualified_type (TREE_TYPE (ptrtype), TYPE_QUAL_VOLATILE);
   tree result = indirect_ref (type, ptr);
   TREE_THIS_VOLATILE (result) = 1;
+  TREE_SIDE_EFFECTS (result) = 1;
 
   /* (*(volatile T *) ptr) = value;  */
   tree value = CALL_EXPR_ARG (callexp, 1);
diff --git a/gcc/testsuite/gdc.dg/torture/pr110516a.d b/gcc/testsuite/gdc.dg/torture/pr110516a.d
new file mode 100644
index 00000000000..276455ae408
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/torture/pr110516a.d
@@ -0,0 +1,12 @@
+// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110516
+// { dg-do compile }
+// { dg-options "-fno-moduleinfo -fdump-tree-optimized" }
+void fn110516(ubyte* ptr)
+{
+    import core.volatile : volatileLoad;
+    volatileLoad(ptr);
+    volatileLoad(ptr);
+    volatileLoad(ptr);
+    volatileLoad(ptr);
+}
+// { dg-final { scan-tree-dump-times " ={v} " 4 "optimized" } }
diff --git a/gcc/testsuite/gdc.dg/torture/pr110516b.d b/gcc/testsuite/gdc.dg/torture/pr110516b.d
new file mode 100644
index 00000000000..b7a67e716a5
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/torture/pr110516b.d
@@ -0,0 +1,12 @@
+// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110516
+// { dg-do compile }
+// { dg-options "-fno-moduleinfo -fdump-tree-optimized" }
+void fn110516(ubyte* ptr)
+{
+    import core.volatile : volatileStore;
+    volatileStore(ptr, 0);
+    volatileStore(ptr, 0);
+    volatileStore(ptr, 0);
+    volatileStore(ptr, 0);
+}
+// { dg-final { scan-tree-dump-times " ={v} " 4 "optimized" } }

commit 2577f8a936c2d6e0508d4696cbc8dd15e6e6b287
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 3 02:20:57 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ae3ab38a574..4686be8f754 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230702
+20230703
diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog
index 17c5f25cacb..81d4a7a2837 100644
--- a/gcc/d/ChangeLog
+++ b/gcc/d/ChangeLog
@@ -1,3 +1,13 @@
+2023-07-02  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-07-02  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110516
+	* intrinsics.cc (expand_volatile_load): Set TREE_SIDE_EFFECTS on the
+	expanded expression.
+	(expand_volatile_store): Likewise.
+
 2023-07-01  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6b424d9d717..d75fade304e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2023-07-02  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-07-02  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/110516
+	* gdc.dg/torture/pr110516a.d: New test.
+	* gdc.dg/torture/pr110516b.d: New test.
+
 2023-07-01  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	Backported from master:

commit 4600de6f961c1495433e7fef69a9ef57d86aec56
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 4 02:20:45 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4686be8f754..a75b56cd2f4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230703
+20230704

commit 94907dba5250b8038be24b3d0e57daec7ac822eb
Author: Cui, Lili <lili.cui@intel.com>
Date:   Thu Jun 29 05:10:35 2023

    x86: Update model values for Alderlake and Rocketlake.
    
    Update model values for Alderlake and Rocketlake according to SDM.
    
    gcc/ChangeLog
    
            * common/config/i386/cpuinfo.h (get_intel_cpu): Remove model value 0xa8
            from Rocketlake, remove model value 0xbf from Alderlake.

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 0333da56ba5..28b2ff0b033 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -435,7 +435,6 @@ get_intel_cpu (struct __processor_model *cpu_model,
       cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE;
       break;
     case 0xa7:
-    case 0xa8:
       /* Rocket Lake.  */
       cpu = "rocketlake";
       CHECK___builtin_cpu_is ("corei7");
@@ -508,7 +507,6 @@ get_intel_cpu (struct __processor_model *cpu_model,
       break;
     case 0x97:
     case 0x9a:
-    case 0xbf:
       /* Alder Lake.  */
       cpu = "alderlake";
       CHECK___builtin_cpu_is ("corei7");

commit 6c072ec50158d6ca9134d4778ad60bb452b1f664
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 5 02:19:53 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 619ad3f14e6..44d249a1614 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2023-07-04  Cui, Lili  <lili.cui@intel.com>
+
+	* common/config/i386/cpuinfo.h (get_intel_cpu): Remove model value 0xa8
+	from Rocketlake, remove model value 0xbf from Alderlake.
+
 2023-06-30  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gimple-fold.cc (fold_array_ctor_reference): Fix head comment.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a75b56cd2f4..31e1a2e29a7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230704
+20230705

commit c70c3bea37bbbaea0c68d072cf7395553b08730b
Author: Segher Boessenkool <segher@kernel.crashing.org>
Date:   Fri Jun 2 17:32:41 2023

    rs6000: genfusion: Rewrite load/compare code
    
    This makes the code more readable, more digestible, more maintainable,
    more extensible.  That kind of thing.  It does that by pulling things
    apart a bit, but also making what stays together more cohesive lumps.
    
    The original function was a bunch of loops and early-outs, and then
    quite a bit of stuff done per iteration, with the iterations essentially
    independent of each other.  This patch moves the stuff done for one
    iteration to a new _one function.
    
    The second big thing is the stuff printed to the .md file is done in
    "here documents" now, which is a lot more readable than having to quote
    and escape and double-escape pieces of text.  Whitespace inside the
    here-document is significant (will be printed as-is), which is a bit
    awkward sometimes, or might take some getting used to, but it is also
    one of the benefits of using them.
    
    Local variables are declared at first use (or close to first use).
    There also shouldn't be many at all, often you can write easier to
    read and manage code by omitting to name something that is hard to name
    in the first place.
    
    Finally some things are done in more typical, more modern, and tighter
    Perl style, for example REs in "if"s or "qw" for lists of constants.
    
    2023-06-06  Segher Boessenkool  <segher@kernel.crashing.org>
    
            * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and
            split out from...
            (gen_ld_cmpi_p10): ... this.
    
    (cherry picked from commit 19e5bf1d5fac00da0b8cd4144d5651b2979d8308)

diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 81cc2255f53..911220838d7 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,92 +53,113 @@ sub mode_to_ldst_char
     return '?';
 }
 
+sub gen_ld_cmpi_p10_one
+{
+  my ($lmode, $result, $ccmode) = @_;
+
+  my $np = "NON_PREFIXED_D";
+  my $mempred = "non_update_memory_operand";
+  my $extend;
+
+  if ($ccmode eq "CC") {
+    # ld and lwa are both DS-FORM.
+    ($lmode =~ /^[SD]I$/) and $np = "NON_PREFIXED_DS";
+    ($lmode =~ /^[SD]I$/) and $mempred = "ds_form_mem_operand";
+  } else {
+    if ($lmode eq "DI") {
+      # ld is DS-form, but lwz is not.
+      $np = "NON_PREFIXED_DS";
+      $mempred = "ds_form_mem_operand";
+    }
+  }
+
+  my $cmpl = ($ccmode eq "CC") ? "" : "l";
+  my $echr = ($ccmode eq "CC") ? "a" : "z";
+  if ($lmode eq "DI") { $echr = ""; }
+  my $constpred = ($ccmode eq "CC") ? "const_m1_to_1_operand"
+  				    : "const_0_to_1_operand";
+
+  # For clobber, we need a SI/DI reg in case we
+  # split because we have to sign/zero extend.
+  my $clobbermode = ($lmode =~ /^[QH]I$/) ? "GPR" : $lmode;
+  if ($result =~ /^EXT/ || $result eq "GPR" || $clobbermode eq "GPR") {
+    # We always need extension if result > lmode.
+    $extend = ($ccmode eq "CC") ? "sign" : "zero";
+  } else {
+    # Result of SI/DI does not need sign extension.
+    $extend = "none";
+  }
+
+  my $ldst = mode_to_ldst_char($lmode);
+  print <<HERE;
+;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
+;; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend
+(define_insn_and_split "*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}"
+  [(set (match_operand:${ccmode} 2 "cc_reg_operand" "=x")
+        (compare:${ccmode} (match_operand:${lmode} 1 "${mempred}" "m")
+HERE
+  print "   " if $ccmode eq "CCUNS";
+print <<HERE;
+                    (match_operand:${lmode} 3 "${constpred}" "n")))
+HERE
+
+  if ($result eq "clobber") {
+    print <<HERE;
+   (clobber (match_scratch:${clobbermode} 0 "=r"))]
+HERE
+  } elsif ($result eq $lmode) {
+    print <<HERE;
+   (set (match_operand:${result} 0 "gpc_reg_operand" "=r") (match_dup 1))]
+HERE
+  } else {
+    print <<HERE;
+   (set (match_operand:${result} 0 "gpc_reg_operand" "=r") (${extend}_extend:${result} (match_dup 1)))]
+HERE
+  }
+
+  print <<HERE;
+  "(TARGET_P10_FUSION)"
+  "l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3"
+  "&& reload_completed
+   && (cc_reg_not_cr0_operand (operands[2], CCmode)
+       || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+                                      ${lmode}mode, ${np}))"
+HERE
+
+  if ($extend eq "none") {
+    print "  [(set (match_dup 0) (match_dup 1))\n";
+  } elsif ($result eq "clobber") {
+    print "  [(set (match_dup 0) (${extend}_extend:${clobbermode} (match_dup 1)))\n";
+  } else {
+    print "  [(set (match_dup 0) (${extend}_extend:${result} (match_dup 1)))\n";
+  }
+
+  print <<HERE;
+   (set (match_dup 2)
+        (compare:${ccmode} (match_dup 0) (match_dup 3)))]
+  ""
+  [(set_attr "type" "fused_load_cmpi")
+   (set_attr "cost" "8")
+   (set_attr "length" "8")])
+
+HERE
+}
+
 sub gen_ld_cmpi_p10
 {
-    my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
-	$mempred, $ccmode, $np, $extend, $resultmode);
-  LMODE: foreach $lmode ('DI','SI','HI','QI') {
-      $ldst = mode_to_ldst_char($lmode);
-      $clobbermode = $lmode;
-      # For clobber, we need a SI/DI reg in case we
-      # split because we have to sign/zero extend.
-      if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
-    RESULT: foreach $result ('clobber', $lmode,  "EXT".$lmode) {
-	# EXTDI does not exist, and we cannot directly produce HI/QI results.
-	next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
-	# Don't allow EXTQI because that would allow HI result which we can't do.
-	$result = "GPR" if $result eq "EXTQI";
-      CCMODE: foreach $ccmode ('CC','CCUNS') {
-	  $np = "NON_PREFIXED_D";
-	  $mempred = "non_update_memory_operand";
-	  if ( $ccmode eq 'CC' ) {
-	      next CCMODE if $lmode eq 'QI';
-	      if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
-		  # ld and lwa are both DS-FORM.
-		  $np = "NON_PREFIXED_DS";
-		  $mempred = "ds_form_mem_operand";
-	      }
-	      $cmpl = "";
-	      $echr = "a";
-	      $constpred = "const_m1_to_1_operand";
-	  } else {
-	      if ( $lmode eq 'DI' ) {
-		  # ld is DS-form, but lwz is not.
-		  $np = "NON_PREFIXED_DS";
-		  $mempred = "ds_form_mem_operand";
-	      }
-	      $cmpl = "l";
-	      $echr = "z";
-	      $constpred = "const_0_to_1_operand";
-	  }
-	  if ($lmode eq 'DI') { $echr = ""; }
-	  if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
-	      # We always need extension if result > lmode.
-	      if ( $ccmode eq 'CC' ) {
-		  $extend = "sign";
-	      } else {
-		  $extend = "zero";
-	      }
-	  } else {
-	      # Result of SI/DI does not need sign extension.
-	      $extend = "none";
-	  }
-	  print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
-	  print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+  foreach my $lmode (qw/DI SI HI QI/) {
+    foreach my $result ("clobber", $lmode,  "EXT$lmode") {
+      # EXTDI does not exist, and we cannot directly produce HI/QI results.
+      next if $result =~ /^(QI|HI|EXTDI)$/;
 
-	  print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
-	  print "  [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
-	  print "        (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
-	  if ($ccmode eq 'CCUNS') { print "   "; }
-	  print "                    (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
-	  if ($result eq 'clobber') {
-	      print "   (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
-	  } elsif ($result eq $lmode) {
-	      print "   (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
-	  } else {
-	      print "   (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
-	  }
-	  print "  \"(TARGET_P10_FUSION)\"\n";
-	  print "  \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
-	  print "  \"&& reload_completed\n";
-	  print "   && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
-	  print "       || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
-	  print "                                      ${lmode}mode, ${np}))\"\n";
+      # Don't allow EXTQI because that would allow HI result which we can't do.
+      $result = "GPR" if $result eq "EXTQI";
 
-	  if ($extend eq "none") {
-	      print "  [(set (match_dup 0) (match_dup 1))\n";
-	  } else {
-	      $resultmode = $result;
-	      if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
-	      print "  [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
-	  }
-	  print "   (set (match_dup 2)\n";
-	  print "        (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
-	  print "  \"\"\n";
-	  print "  [(set_attr \"type\" \"fused_load_cmpi\")\n";
-	  print "   (set_attr \"cost\" \"8\")\n";
-	  print "   (set_attr \"length\" \"8\")])\n";
-	  print "\n";
+      foreach my $ccmode (qw/CC CCUNS/) {
+	# We do not have signed single-byte loads.
+	next if ($lmode eq "QI" and $ccmode eq "CC");
+
+	gen_ld_cmpi_p10_one($lmode, $result, $ccmode);
       }
     }
   }

commit 7fc075626012b9fd09b20049d8681f2d72395f5c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Jul 5 20:08:58 2023

    Fix power10 fusion bug with prefixed loads, PR target/105325
    
    This changes fixes PR target/105325.  PR target/105325 is a bug where an
    invalid lwa instruction is generated due to power10 fusion of a load
    instruction to a GPR and an compare immediate instruction with the immediate
    being -1, 0, or 1.
    
    In some cases, when the load instruction is done, the GCC compiler would
    generate a load instruction with an offset that was too large to fit into the
    normal load instruction.
    
    In particular, loads from the stack might originally have a small offset, so
    that the load is not a prefixed load.  However, after the stack is set up, and
    register allocation has been done, the offset now is large enough that we would
    have to use a prefixed load instruction.
    
    The support for prefixed loads did not consider that patterns with a fused load
    and compare might have a prefixed address.  Without this support, the proper
    prefixed load won't be generated.
    
    In the original code, when the split2 pass is run after reload has finished the
    ds_form_mem_operand predicate that was used for lwa and ld no longer returns
    true.  When the pattern was created, ds_form_mem_operand recognized the insn as
    being valid since the offset was small.  But after register allocation,
    ds_form_mem_operand did not return true.  Because it didn't return true, the
    insn could not be split.  Since the insn was not split and the prefix support
    did not indicate a prefixed instruction was used, the wrong load is generated.
    
    The solution involves:
    
        1)  Don't use ds_form_mem_operand for ld and lwa, always use
            non_update_memory_operand.
    
        2)  Delete ds_form_mem_operand since it is no longer used.
    
        3)  Use the "YZ" constraints for ld/lwa instead of "m".
    
        4)  If we don't need to sign extend the lwa, convert it to lwz, and use
            cmpwi instead of cmpdi.  Adjust the insn name to reflect the code
            generate.
    
        5)  Insure that the insn using lwa will be recognized as having a prefixed
            operand (and hence the insn length will be 16 bytes instead of 8
            bytes).
    
            5a) Set the prefixed and maybe_prefix attributes to know that
                fused_load_cmpi are also load insns;
    
            5b) In the case where we are just setting CC and not using the memory
                afterward, set the clobber to use a DI register, and put an
                explicit sign_extend operation in the split;
    
            5c) Set the sign_extend attribute to "yes" for lwa.
    
            5d) 5a-5c are the things that prefixed_load_p in rs6000.cc checks to
                ensure that lwa is treated as a ds-form instruction and not as
                a d-form instruction (i.e. lwz).
    
        6)  Add a new test case for this case.
    
        7)  Adjust the insn counts in fusion-p10-ldcmpi.c.  Because we are no
            longer using ds_form_mem_operand, the ld and lwa instructions will fuse
            x-form (reg+reg) addresses in addition ds-form (reg+offset or reg).
    
    2023-06-23   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            PR target/105325
            * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
            allowed prefixed lwa to be generated.
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/predicates.md (ds_form_mem_operand): Delete.
            * config/rs6000/rs6000.md (prefixed attribute): Add support for load
            plus compare immediate fused insns.
            (maybe_prefixed): Likewise.
    
    gcc/testsuite/
    
            PR target/105325
            * g++.target/powerpc/pr105325.C: New test.
            * gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn counts.
    
            (cherry picked from commit 370de1488a9a49956c47e5ec8c8f1489b4314a34)
    
    Co-Authored-By: Aaron Sawdey  <acsawdey@linux.ibm.com>

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 15f0c16f705..4067ee76215 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
 ;; load mode is DI result mode is clobber compare mode is CC extend is none
 (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-        (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
+        (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ")
                     (match_operand:DI 3 "const_m1_to_1_operand" "n")))
    (clobber (match_scratch:DI 0 "=r"))]
   "(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
 ;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
 (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
   [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
-        (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
+        (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ")
                        (match_operand:DI 3 "const_0_to_1_operand" "n")))
    (clobber (match_scratch:DI 0 "=r"))]
   "(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
 ;; load mode is DI result mode is DI compare mode is CC extend is none
 (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-        (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
+        (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ")
                     (match_operand:DI 3 "const_m1_to_1_operand" "n")))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
   "(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
 ;; load mode is DI result mode is DI compare mode is CCUNS extend is none
 (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
   [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
-        (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
+        (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ")
                        (match_operand:DI 3 "const_0_to_1_operand" "n")))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
   "(TARGET_P10_FUSION)"
@@ -104,17 +104,17 @@
 
 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
 ;; load mode is SI result mode is clobber compare mode is CC extend is none
-(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
+(define_insn_and_split "*lwz_cmpwi_cr0_SI_clobber_CC_none"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-        (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
+        (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m")
                     (match_operand:SI 3 "const_m1_to_1_operand" "n")))
    (clobber (match_scratch:SI 0 "=r"))]
   "(TARGET_P10_FUSION)"
-  "lwa%X1 %0,%1\;cmpdi %2,%0,%3"
+  "lwz%X1 %0,%1\;cmpwi %2,%0,%3"
   "&& reload_completed
    && (cc_reg_not_cr0_operand (operands[2], CCmode)
        || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
-                                      SImode, NON_PREFIXED_DS))"
+                                      SImode, NON_PREFIXED_D))"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2)
         (compare:CC (match_dup 0) (match_dup 3)))]
@@ -146,17 +146,17 @@
 
 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
 ;; load mode is SI result mode is SI compare mode is CC extend is none
-(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
+(define_insn_and_split "*lwz_cmpwi_cr0_SI_SI_CC_none"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-        (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
+        (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m")
                     (match_operand:SI 3 "const_m1_to_1_operand" "n")))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
   "(TARGET_P10_FUSION)"
-  "lwa%X1 %0,%1\;cmpdi %2,%0,%3"
+  "lwz%X1 %0,%1\;cmpwi %2,%0,%3"
   "&& reload_completed
    && (cc_reg_not_cr0_operand (operands[2], CCmode)
        || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
-                                      SImode, NON_PREFIXED_DS))"
+                                      SImode, NON_PREFIXED_D))"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2)
         (compare:CC (match_dup 0) (match_dup 3)))]
@@ -190,7 +190,7 @@
 ;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
 (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-        (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
+        (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ")
                     (match_operand:SI 3 "const_m1_to_1_operand" "n")))
    (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
   "(TARGET_P10_FUSION)"
@@ -205,6 +205,7 @@
   ""
   [(set_attr "type" "fused_load_cmpi")
    (set_attr "cost" "8")
+   (set_attr "sign_extend" "yes")
    (set_attr "length" "8")])
 
 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 911220838d7..d0517970ace 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -61,20 +61,31 @@ sub gen_ld_cmpi_p10_one
   my $mempred = "non_update_memory_operand";
   my $extend;
 
+  # We need to special case lwa.  The prefixed_load_p function in rs6000.cc
+  # (which determines if a load instruction is prefixed) uses the fact that the
+  # register mode is different from the memory mode, and that the sign_extend
+  # attribute is set to use DS-form rules for the address instead of D-form.
+  # If the register size is the same, prefixed_load_p assumes we are doing a
+  # lwz.  We change to use an lwz and word compare if we don't need to sign
+  # extend the SImode value.  Otherwise if we need the value, we need to
+  # make sure the insn is marked as ds-form.
+  my $cmp_size_char = ($lmode eq "SI"
+		       && $ccmode eq "CC"
+		       && $result !~ /^EXT|^DI$/) ? "w" : "d";
+
   if ($ccmode eq "CC") {
     # ld and lwa are both DS-FORM.
-    ($lmode =~ /^[SD]I$/) and $np = "NON_PREFIXED_DS";
-    ($lmode =~ /^[SD]I$/) and $mempred = "ds_form_mem_operand";
+    ($lmode eq "DI") and $np = "NON_PREFIXED_DS";
+    ($lmode eq "SI" && $cmp_size_char eq "d") and $np = "NON_PREFIXED_DS";
   } else {
     if ($lmode eq "DI") {
       # ld is DS-form, but lwz is not.
       $np = "NON_PREFIXED_DS";
-      $mempred = "ds_form_mem_operand";
     }
   }
 
   my $cmpl = ($ccmode eq "CC") ? "" : "l";
-  my $echr = ($ccmode eq "CC") ? "a" : "z";
+  my $echr = ($ccmode eq "CC" && $cmp_size_char eq "d") ? "a" : "z";
   if ($lmode eq "DI") { $echr = ""; }
   my $constpred = ($ccmode eq "CC") ? "const_m1_to_1_operand"
   				    : "const_0_to_1_operand";
@@ -91,12 +102,15 @@ sub gen_ld_cmpi_p10_one
   }
 
   my $ldst = mode_to_ldst_char($lmode);
+
+  # DS-form addresses need YZ, and not m.
+  my $constraint = ($np eq "NON_PREFIXED_DS") ? "YZ" : "m";
   print <<HERE;
 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
 ;; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend
-(define_insn_and_split "*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}"
+(define_insn_and_split "*l${ldst}${echr}_cmp${cmpl}${cmp_size_char}i_cr0_${lmode}_${result}_${ccmode}_${extend}"
   [(set (match_operand:${ccmode} 2 "cc_reg_operand" "=x")
-        (compare:${ccmode} (match_operand:${lmode} 1 "${mempred}" "m")
+        (compare:${ccmode} (match_operand:${lmode} 1 "${mempred}" "${constraint}")
 HERE
   print "   " if $ccmode eq "CCUNS";
 print <<HERE;
@@ -119,7 +133,7 @@ HERE
 
   print <<HERE;
   "(TARGET_P10_FUSION)"
-  "l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3"
+  "l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}${cmp_size_char}i %2,%0,%3"
   "&& reload_completed
    && (cc_reg_not_cr0_operand (operands[2], CCmode)
        || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
@@ -140,6 +154,15 @@ HERE
   ""
   [(set_attr "type" "fused_load_cmpi")
    (set_attr "cost" "8")
+HERE
+
+  if ($lmode eq "SI" && $ccmode eq "CC" && $cmp_size_char eq "d") {
+    # prefixed_load_p needs the sign_extend attribute to validate lwa as a
+    # DS-form instruction instead of D-form.
+    print "   (set_attr \"sign_extend\" \"yes\")\n";
+  }
+
+  print <<HERE
    (set_attr "length" "8")])
 
 HERE
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 274bdbe468f..129664da94c 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1125,20 +1125,6 @@
   return INTVAL (offset) % 4 == 0;
 })
 
-;; Return 1 if the operand is a memory operand that has a valid address for
-;; a DS-form instruction. I.e. the address has to be either just a register,
-;; or register + const where the two low order bits of const are zero.
-(define_predicate "ds_form_mem_operand"
-  (match_code "subreg,mem")
-{
-  if (!any_memory_operand (op, mode))
-    return false;
-
-  rtx addr = XEXP (op, 0);
-
-  return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS;
-})
-
 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
 (define_predicate "symbol_ref_operand"
   (and (match_code "symbol_ref")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 914ddcc8884..9d5e0244d81 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -287,7 +287,7 @@
 ;; Whether this insn has a prefixed form and a non-prefixed form.
 (define_attr "maybe_prefixed" "no,yes"
   (if_then_else (eq_attr "type" "load,fpload,vecload,store,fpstore,vecstore,
-  				 integer,add")
+  				 integer,add,fused_load_cmpi")
 		(const_string "yes")
 		(const_string "no")))
 
@@ -302,7 +302,7 @@
 	      (eq_attr "maybe_prefixed" "no"))
 	 (const_string "no")
 
-	 (eq_attr "type" "load,fpload,vecload")
+	 (eq_attr "type" "load,fpload,vecload,fused_load_cmpi")
 	 (if_then_else (match_test "prefixed_load_p (insn)")
 		       (const_string "yes")
 		       (const_string "no"))
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
new file mode 100644
index 00000000000..18a2e520d6c
--- /dev/null
+++ b/gcc/testsuite/g++.target/powerpc/pr105325.C
@@ -0,0 +1,28 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
+
+/* PR target/105324.  Test that power10 fusion does not generate an LWA/CMPDI
+   with a large offset that the assembler rejects.  Instead it should a
+   PLWZ/CMPWI combination.
+
+   Originally, the code was dying because the fusion load + compare -1/0/1
+   patterns did not handle the possibility that the load might be prefixed.
+   The -fstack-protector option is needed to show the bug.  */
+
+struct Ath__array1D {
+  int _current;
+  int getCnt() { return _current; }
+};
+struct extMeasure {
+  int _mapTable[10000];
+  Ath__array1D _metRCTable;
+};
+void measureRC() {
+  extMeasure m;
+  for (; m._metRCTable.getCnt();)
+    for (;;)
+      ;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index 526a026d874..165bd9a07ad 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -54,15 +54,17 @@ TEST(uint8_t)
 TEST(int8_t)
 
 /* { dg-final { scan-assembler-times "lbz_cmpldi_cr0_QI_clobber_CCUNS_zero"   4 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none"             4 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none"        4 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none"         1 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none"    1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none"            24 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none"        8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none"         2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none"    2 { target lp64 } } } */
 /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign"      16 { target lp64 } } } */
 /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero"   4 { target lp64 } } } */
 /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign"         0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none"       4 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_clobber_CC_none"       8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_SI_CC_none"            8 { target lp64 } } } */
 /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero"     0 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_SI_CCUNS_none"        2 { target lp64 } } } */
 /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none"   2 { target lp64 } } } */
 
 /* { dg-final { scan-assembler-times "lbz_cmpldi_cr0_QI_clobber_CCUNS_zero"   2 { target ilp32 } } } */
@@ -73,6 +75,8 @@ TEST(int8_t)
 /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign"       8 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero"   2 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign"         0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none"       9 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_SI_CC_none"           36 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_clobber_CC_none"      16 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero"     0 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none"   6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_SI_CCUNS_none"        2 { target ilp32 } } } */

commit a7edbb014f8d4730395e6da0f74a993170d3bc5d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 6 02:20:38 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 44d249a1614..98754c72f1a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,27 @@
+2023-07-05  Michael Meissner  <meissner@linux.ibm.com>
+
+	Backported from master:
+	2023-06-23   Michael Meissner  <meissner@linux.ibm.com>
+		    Aaron Sawdey   <acsawdey@linux.ibm.com>
+
+	PR target/105325
+	* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
+	allowed prefixed lwa to be generated.
+	* config/rs6000/fusion.md: Regenerate.
+	* config/rs6000/predicates.md (ds_form_mem_operand): Delete.
+	* config/rs6000/rs6000.md (prefixed attribute): Add support for load
+	plus compare immediate fused insns.
+	(maybe_prefixed): Likewise.
+
+2023-07-05  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	Backported from master:
+	2023-06-06  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and
+	split out from...
+	(gen_ld_cmpi_p10): ... this.
+
 2023-07-04  Cui, Lili  <lili.cui@intel.com>
 
 	* common/config/i386/cpuinfo.h (get_intel_cpu): Remove model value 0xa8
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 31e1a2e29a7..ec0d4f34cd2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230705
+20230706
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d75fade304e..cdcdeddbd46 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2023-07-05  Michael Meissner  <meissner@linux.ibm.com>
+
+	Backported from master:
+	2023-06-23   Michael Meissner  <meissner@linux.ibm.com>
+		    Aaron Sawdey   <acsawdey@linux.ibm.com>
+
+	PR target/105325
+	* g++.target/powerpc/pr105325.C: New test.
+	* gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn counts.
+
 2023-07-02  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	Backported from master:

commit 67bda4331dc4f548820ed2f3138aa7f64fd4c77d
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Jul 6 17:25:47 2023

    libstdc++: Document --enable-cstdio=stdio_pure [PR104299]
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/104299
            * doc/xml/manual/configure.xml: Describe stdio_pure argument to
            --enable-cstdio.
            * doc/html/manual/configure.html: Regenerate.
    
    (cherry picked from commit b90a70984a9beee39b41f842b56926f9db2069ca)

diff --git a/libstdc++-v3/doc/html/manual/configure.html b/libstdc++-v3/doc/html/manual/configure.html
index 31c4da8a5e3..5981c6c548b 100644
--- a/libstdc++-v3/doc/html/manual/configure.html
+++ b/libstdc++-v3/doc/html/manual/configure.html
@@ -38,9 +38,14 @@
      </p><pre class="programlisting">
    --with-gxx-include-dir=/foo/H-x86-gcc-3-c-gxx-inc/include/4.4-20090404</pre></dd><dt><span class="term"><code class="code">--enable-cstdio</code></span></dt><dd><p>This is an abbreviated form of <code class="code">'--enable-cstdio=stdio'</code>
 	(described next).
-     </p></dd><dt><span class="term"><code class="code">--enable-cstdio=OPTION</code></span></dt><dd><p>Select a target-specific I/O package. At the moment, the only
-	choice is to use 'stdio', a generic "C" abstraction.
-	The default is 'stdio'. This option can change the library ABI.
+     </p></dd><dt><span class="term"><code class="code">--enable-cstdio=OPTION</code></span></dt><dd><p>Select a target-specific I/O package. The choices are 'stdio'
+       which is a generic abstraction using POSIX file I/O APIs
+       (<code class="function">read</code>, <code class="function">write</code>,
+       <code class="function">lseek</code>, etc.), and 'stdio_pure' which is similar
+       but only uses standard C file I/O APIs (<code class="function">fread</code>,
+       <code class="function">fwrite</code>, <code class="function">fseek</code>, etc.).
+       The 'stdio_posix' choice is a synonym for 'stdio'.
+       The default is 'stdio'. This option can change the library ABI.
      </p></dd><dt><span class="term"><code class="code">--enable-clocale</code></span></dt><dd><p>This is an abbreviated form of <code class="code">'--enable-clocale=generic'</code>
 	(described next).
      </p></dd><dt><span class="term"><code class="code">--enable-clocale=OPTION</code></span></dt><dd><p>Select a target-specific underlying locale package.  The
diff --git a/libstdc++-v3/doc/xml/manual/configure.xml b/libstdc++-v3/doc/xml/manual/configure.xml
index 8c26acc95a7..f01fdb9b0d4 100644
--- a/libstdc++-v3/doc/xml/manual/configure.xml
+++ b/libstdc++-v3/doc/xml/manual/configure.xml
@@ -74,9 +74,14 @@
  </listitem></varlistentry>
 
  <varlistentry><term><code>--enable-cstdio=OPTION</code></term>
- <listitem><para>Select a target-specific I/O package. At the moment, the only
-	choice is to use 'stdio', a generic "C" abstraction.
-	The default is 'stdio'. This option can change the library ABI.
+ <listitem><para>Select a target-specific I/O package. The choices are 'stdio'
+       which is a generic abstraction using POSIX file I/O APIs
+       (<function>read</function>, <function>write</function>,
+       <function>lseek</function>, etc.), and 'stdio_pure' which is similar
+       but only uses standard C file I/O APIs (<function>fread</function>,
+       <function>fwrite</function>, <function>fseek</function>, etc.).
+       The 'stdio_posix' choice is a synonym for 'stdio'.
+       The default is 'stdio'. This option can change the library ABI.
      </para>
  </listitem></varlistentry>
 

commit 456ec5a2aa17f27d740a450019cbcbd25f6b91e8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 7 02:19:41 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ec0d4f34cd2..2e3c50b9d1e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230706
+20230707
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index bb874201610..7dff8934305 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,13 @@
+2023-07-06  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2023-07-06  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/104299
+	* doc/xml/manual/configure.xml: Describe stdio_pure argument to
+	--enable-cstdio.
+	* doc/html/manual/configure.html: Regenerate.
+
 2023-06-23  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 0444c2065aef569aa16e43cffc564c202a59af33
Author: Iain Buclaw <ibuclaw@gdcproject.org>
Date:   Fri Jul 7 21:06:07 2023

    d: Fix PR 108842: Cannot use enum array with -fno-druntime
    
    Restrict the generating of CONST_DECLs for D manifest constants to just
    scalars without pointers.  It shouldn't happen that a reference to a
    manifest constant has not been expanded within a function body during
    codegen, but it has been found to occur in older versions of the D
    front-end (PR98277), so if the decl of a non-scalar constant is
    requested, just return its initializer as an expression.
    
            PR d/108842
    
    gcc/d/ChangeLog:
    
            * decl.cc (DeclVisitor::visit (VarDeclaration *)): Only emit scalar
            manifest constants.
            (get_symbol_decl): Don't generate CONST_DECL for non-scalar manifest
            constants.
            * imports.cc (ImportVisitor::visit (VarDeclaration *)): New method.
    
    gcc/testsuite/ChangeLog:
    
            * gdc.dg/pr98277.d: Add more tests.
            * gdc.dg/pr108842.d: New test.
    
    (cherry picked from commit f934c5753849f7c48c6a3abfcd73b8f6008e8371)

diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc
index de1dfd14189..8f0026b7be9 100644
--- a/gcc/d/decl.cc
+++ b/gcc/d/decl.cc
@@ -781,7 +781,7 @@ public:
       {
 	/* Do not store variables we cannot take the address of,
 	   but keep the values for purposes of debugging.  */
-	if (!d->type->isscalar ())
+	if (d->type->isscalar () && !d->type->hasPointers ())
 	  {
 	    tree decl = get_symbol_decl (d);
 	    d_pushdecl (decl);
@@ -1199,6 +1199,20 @@ get_symbol_decl (Declaration *decl)
       return decl->csym;
     }
 
+  if (VarDeclaration *vd = decl->isVarDeclaration ())
+    {
+      /* CONST_DECL was initially intended for enumerals and may be used for
+	 scalars in general, but not for aggregates.  Here a non-constant
+	 value is generated anyway so as its value can be used.  */
+      if (!vd->canTakeAddressOf () && !vd->type->isscalar ())
+	{
+	  gcc_assert (vd->_init && !vd->_init->isVoidInitializer ());
+	  Expression *ie = initializerToExpression (vd->_init);
+	  decl->csym = build_expr (ie, false);
+	  return decl->csym;
+	}
+    }
+
   /* Build the tree for the symbol.  */
   FuncDeclaration *fd = decl->isFuncDeclaration ();
   if (fd)
@@ -1246,23 +1260,15 @@ get_symbol_decl (Declaration *decl)
       if (vd->storage_class & STCextern)
 	DECL_EXTERNAL (decl->csym) = 1;
 
-      /* CONST_DECL was initially intended for enumerals and may be used for
-	 scalars in general, but not for aggregates.  Here a non-constant
-	 value is generated anyway so as the CONST_DECL only serves as a
-	 placeholder for the value, however the DECL itself should never be
-	 referenced in any generated code, or passed to the back-end.  */
-      if (vd->storage_class & STCmanifest)
+      if (!vd->canTakeAddressOf ())
 	{
 	  /* Cannot make an expression out of a void initializer.  */
-	  if (vd->_init && !vd->_init->isVoidInitializer ())
-	    {
-	      Expression *ie = initializerToExpression (vd->_init);
+	  gcc_assert (vd->_init && !vd->_init->isVoidInitializer ());
+	  /* Non-scalar manifest constants have already been dealt with.  */
+	  gcc_assert (vd->type->isscalar ());
 
-	      if (!vd->type->isscalar ())
-		DECL_INITIAL (decl->csym) = build_expr (ie, false);
-	      else
-		DECL_INITIAL (decl->csym) = build_expr (ie, true);
-	    }
+	  Expression *ie = initializerToExpression (vd->_init);
+	  DECL_INITIAL (decl->csym) = build_expr (ie, true);
 	}
 
       /* [type-qualifiers/const-and-immutable]
diff --git a/gcc/d/imports.cc b/gcc/d/imports.cc
index 6a59ef61b9c..c8447b9674c 100644
--- a/gcc/d/imports.cc
+++ b/gcc/d/imports.cc
@@ -127,6 +127,15 @@ public:
     this->result_ = this->make_import (TYPE_STUB_DECL (type));
   }
 
+  void visit (VarDeclaration *d)
+  {
+    /* Not all kinds of manifest constants create a CONST_DECL.  */
+    if (!d->canTakeAddressOf () && !d->type->isscalar ())
+      return;
+
+    visit ((Declaration *) d);
+  }
+
   /* For now, ignore importing other kinds of dsymbols.  */
   void visit (ScopeDsymbol *)
   {
diff --git a/gcc/testsuite/gdc.dg/pr108842.d b/gcc/testsuite/gdc.dg/pr108842.d
new file mode 100644
index 00000000000..5aae9e5000d
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr108842.d
@@ -0,0 +1,4 @@
+// { dg-do compile }
+// { dg-options "-fno-rtti" }
+module object;
+enum int[] x = [0, 1, 2];
diff --git a/gcc/testsuite/gdc.dg/pr98277.d b/gcc/testsuite/gdc.dg/pr98277.d
index 0dff142a6ef..c88c735dec8 100644
--- a/gcc/testsuite/gdc.dg/pr98277.d
+++ b/gcc/testsuite/gdc.dg/pr98277.d
@@ -11,3 +11,14 @@ ref int getSide(Side side, return ref int left, return ref int right)
 {
     return side == Side.left ? left : right;
 }
+
+enum SideA : int[]
+{
+    left = [0],
+    right = [1],
+}
+
+int getSideA(SideA side, ref int left, ref int right)
+{
+    return side == SideA.left ? left : right;
+}

commit 3d36bf02f4b22e12f2598ea1f7150cc968d7af22
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 8 02:18:22 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2e3c50b9d1e..f3144f1474c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230707
+20230708
diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog
index 81d4a7a2837..bba0074bdef 100644
--- a/gcc/d/ChangeLog
+++ b/gcc/d/ChangeLog
@@ -1,3 +1,15 @@
+2023-07-07  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-07-07  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/108842
+	* decl.cc (DeclVisitor::visit (VarDeclaration *)): Only emit scalar
+	manifest constants.
+	(get_symbol_decl): Don't generate CONST_DECL for non-scalar manifest
+	constants.
+	* imports.cc (ImportVisitor::visit (VarDeclaration *)): New method.
+
 2023-07-02  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cdcdeddbd46..5e6843c2313 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2023-07-07  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	Backported from master:
+	2023-07-07  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/108842
+	* gdc.dg/pr98277.d: Add more tests.
+	* gdc.dg/pr108842.d: New test.
+
 2023-07-05  Michael Meissner  <meissner@linux.ibm.com>
 
 	Backported from master:

commit 45aab94325eb4b44547c38ac0090eeacc723c589
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Sat Jul 8 11:22:29 2023

    doc: Fix typo in Warning Options [PR110595]
    
    gcc/ChangeLog:
    
            PR c++/110595
            * doc/invoke.texi (Warning Options): Fix typo.
    
    (cherry picked from commit 238944752e20d7714352152cb26a08fb26aea831)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d945a5eae9f..f1599ba04ad 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -6647,7 +6647,7 @@ This warning is enabled by @option{-Wall}.
 @item -Wmissing-include-dirs @r{(C, C++, Objective-C, Objective-C++ and Fortran only)}
 @opindex Wmissing-include-dirs
 @opindex Wno-missing-include-dirs
-Warn if a user-supplied include directory does not exist. This opions is disabled
+Warn if a user-supplied include directory does not exist. This option is disabled
 by default for C, C++, Objective-C and Objective-C++. For Fortran, it is partially
 enabled by default by warning for -I and -J, only.
 

commit 2d416f352be898c408fd3db402719d6625f26720
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Fri Jul 7 20:25:06 2023

    Fortran: simplification of FINDLOC for constant complex arguments [PR110585]
    
    gcc/fortran/ChangeLog:
    
            PR fortran/110585
            * arith.cc (gfc_compare_expr): Handle equality comparison of constant
            complex gfc_expr arguments.
    
    gcc/testsuite/ChangeLog:
    
            PR fortran/110585
            * gfortran.dg/findloc_9.f90: New test.
    
    (cherry picked from commit 7ac1581d066a6f3a0d4acf1042a74634258b4966)

diff --git a/gcc/fortran/arith.cc b/gcc/fortran/arith.cc
index 1e521cc0cc5..bdde333293e 100644
--- a/gcc/fortran/arith.cc
+++ b/gcc/fortran/arith.cc
@@ -1080,6 +1080,11 @@ gfc_compare_expr (gfc_expr *op1, gfc_expr *op2, gfc_intrinsic_op op)
 	    || (op1->value.logical && !op2->value.logical));
       break;
 
+    case BT_COMPLEX:
+      gcc_assert (op == INTRINSIC_EQ);
+      rc = mpc_cmp (op1->value.complex, op2->value.complex);
+      break;
+
     default:
       gfc_internal_error ("gfc_compare_expr(): Bad basic type");
     }
diff --git a/gcc/testsuite/gfortran.dg/findloc_9.f90 b/gcc/testsuite/gfortran.dg/findloc_9.f90
new file mode 100644
index 00000000000..05974476cb3
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/findloc_9.f90
@@ -0,0 +1,19 @@
+! { dg-do compile }
+! { dg-options "-fdump-tree-original" }
+! PR fortran/110585 - simplification of FINDLOC for constant complex arguments
+
+program mvce
+  implicit none
+  integer, parameter :: a(*) = findloc([(1.,0.),(2.,1.)], (2.,0.))
+  integer, parameter :: b(*) = findloc([(1.,0.),(2.,1.)], (2.,0.), back=.true.)
+  integer, parameter :: c(*) = findloc([(1.,0.),(2.,1.)], (2.,1.))
+  integer, parameter :: d(*) = findloc([(1.,0.),(2.,1.)], (2.,1.), back=.true.)
+  integer, parameter :: e    = findloc([(1.,0.),(2.,1.)], (2.,1.), dim=1)
+  if (a(1) /= 0) stop 1
+  if (b(1) /= 0) stop 2
+  if (c(1) /= 2) stop 3
+  if (d(1) /= 2) stop 4
+  if (e    /= 2) stop 5
+end
+
+! { dg-final { scan-tree-dump-not "_gfortran_stop_numeric" "original" } }

commit b29e90ec2c47253fe1b6b56d590c20c5282c3f91
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 9 02:18:52 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 98754c72f1a..05202840a12 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2023-07-08  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2023-07-08  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR c++/110595
+	* doc/invoke.texi (Warning Options): Fix typo.
+
 2023-07-05  Michael Meissner  <meissner@linux.ibm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f3144f1474c..6ca206c427e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230708
+20230709
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 21b5d65d2dc..e9057cdf00b 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,12 @@
+2023-07-08  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-07-08  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/110585
+	* arith.cc (gfc_compare_expr): Handle equality comparison of constant
+	complex gfc_expr arguments.
+
 2023-06-09  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5e6843c2313..7069f3f2029 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2023-07-08  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-07-08  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/110585
+	* gfortran.dg/findloc_9.f90: New test.
+
 2023-07-07  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	Backported from master:

commit 87482df5e09c075c13c0cf5c77f7a31a7fd08407
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 10 02:19:03 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6ca206c427e..1d5dd3c5cda 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230709
+20230710

commit 3fe26353fd302a04c7d4767a0756cdff02dc1792
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 11 02:19:30 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1d5dd3c5cda..2dbd21ed6c0 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230710
+20230711

commit 623d28e713bb17160f3e1107d5de2ed824599847
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 12 02:19:10 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2dbd21ed6c0..b130beac02a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230711
+20230712

commit dfbe77ab8a70bc7eb48a96775da04095d933a3a6
Author: Patrick Palka <ppalka@redhat.com>
Date:   Thu Jun 29 22:10:18 2023

    c++: NSDMI instantiation during overload resolution [PR110468]
    
    Here we find ourselves instantiating the NSDMI for A<1>::m when
    computing argument conversions during overload resolution, and
    thus tf_conv is set.  The flag causes mark_used for the constructor
    used in the NSDMI to exit early and not instantiate its noexcept-spec,
    which eventually leads to an ICE from nothrow_spec_p.
    
    This patch fixes this by clearing any special tsubst flags during
    instantiation of an NSDMI, since the result should be independent of
    the context that requires the instantiation.
    
            PR c++/110468
    
    gcc/cp/ChangeLog:
    
            * init.cc (maybe_instantiate_nsdmi_init): Mask out all
            tsubst flags except for tf_warning_or_error.
    
    gcc/testsuite/ChangeLog:
    
            * g++.dg/cpp0x/noexcept79.C: New test.
    
    (cherry picked from commit 9479da4515f7d019b4ef282d0e21536431c44f71)

diff --git a/gcc/cp/init.cc b/gcc/cp/init.cc
index 36dcd70e152..b32ec2ed247 100644
--- a/gcc/cp/init.cc
+++ b/gcc/cp/init.cc
@@ -579,6 +579,10 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain)
   tree init = DECL_INITIAL (member);
   if (init && DECL_LANG_SPECIFIC (member) && DECL_TEMPLATE_INFO (member))
     {
+      /* Clear any special tsubst flags; the result of NSDMI instantiation
+	 should be independent of the substitution context.  */
+      complain &= tf_warning_or_error;
+
       init = DECL_INITIAL (DECL_TI_TEMPLATE (member));
       location_t expr_loc
 	= cp_expr_loc_or_loc (init, DECL_SOURCE_LOCATION (member));
diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept79.C b/gcc/testsuite/g++.dg/cpp0x/noexcept79.C
new file mode 100644
index 00000000000..d1f54d14431
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/noexcept79.C
@@ -0,0 +1,18 @@
+// PR c++/110468
+// { dg-do compile { target c++11 } }
+
+template<int T>
+struct variant {
+  variant() noexcept(T > 0);
+};
+
+template<int N>
+struct A {
+  variant<N> m = {};
+};
+
+struct B {
+  B(A<1>);
+};
+
+B b = {{}};

commit 530b749c71d7aaaf965d53227911411572c35146
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Wed Jul 12 15:40:19 2023

    libstdc++: Check conversion from filesystem::path to wide strings [PR95048]
    
    The testcase added for this bug only checks conversion from wide strings
    on construction, but the fix also covered conversion to wide strings via
    path::wstring(). Add checks for that, and u16string() and u32string().
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/95048
            * testsuite/27_io/filesystem/path/construct/95048.cc: Check
            conversions to wide strings.
            * testsuite/experimental/filesystem/path/construct/95048.cc:
            Likewise.
    
    (cherry picked from commit d6384ad1a9ab7ea46990a7ed1299d5a2be4acece)

diff --git a/libstdc++-v3/testsuite/27_io/filesystem/path/construct/95048.cc b/libstdc++-v3/testsuite/27_io/filesystem/path/construct/95048.cc
index c1a382d1420..cd80d668b23 100644
--- a/libstdc++-v3/testsuite/27_io/filesystem/path/construct/95048.cc
+++ b/libstdc++-v3/testsuite/27_io/filesystem/path/construct/95048.cc
@@ -16,6 +16,8 @@ test_wide()
   VERIFY( CHECK(L, "\U0001F4C1") ); // folder
   VERIFY( CHECK(L, "\U0001F4C2") ); // open folder
   VERIFY( CHECK(L, "\U0001F4C4") ); // filing cabient
+
+  VERIFY( path(u8"\U0001D11E").wstring() == L"\U0001D11E" ); // G Clef
 }
 
 void
@@ -25,6 +27,8 @@ test_u16()
   VERIFY( CHECK(u, "\U0001F4C1") ); // folder
   VERIFY( CHECK(u, "\U0001F4C2") ); // open folder
   VERIFY( CHECK(u, "\U0001F4C4") ); // filing cabient
+
+  VERIFY( path(u8"\U0001D11E").u16string() == u"\U0001D11E" ); // G Clef
 }
 
 void
@@ -34,6 +38,8 @@ test_u32()
   VERIFY( CHECK(U, "\U0001F4C1") ); // folder
   VERIFY( CHECK(U, "\U0001F4C2") ); // open folder
   VERIFY( CHECK(U, "\U0001F4C4") ); // filing cabient
+
+  VERIFY( path(u8"\U0001D11E").u32string() == U"\U0001D11E" ); // G Clef
 }
 
 int
diff --git a/libstdc++-v3/testsuite/experimental/filesystem/path/construct/95048.cc b/libstdc++-v3/testsuite/experimental/filesystem/path/construct/95048.cc
index b7a93f3c985..fc65bfecd4d 100644
--- a/libstdc++-v3/testsuite/experimental/filesystem/path/construct/95048.cc
+++ b/libstdc++-v3/testsuite/experimental/filesystem/path/construct/95048.cc
@@ -18,6 +18,8 @@ test_wide()
   VERIFY( CHECK(L, "\U0001F4C1") ); // folder
   VERIFY( CHECK(L, "\U0001F4C2") ); // open folder
   VERIFY( CHECK(L, "\U0001F4C4") ); // filing cabient
+
+  VERIFY( path(u8"\U0001D11E").wstring() == L"\U0001D11E" ); // G Clef
 }
 
 void
@@ -27,6 +29,8 @@ test_u16()
   VERIFY( CHECK(u, "\U0001F4C1") ); // folder
   VERIFY( CHECK(u, "\U0001F4C2") ); // open folder
   VERIFY( CHECK(u, "\U0001F4C4") ); // filing cabient
+
+  VERIFY( path(u8"\U0001D11E").u16string() == u"\U0001D11E" ); // G Clef
 }
 
 void
@@ -36,6 +40,8 @@ test_u32()
   VERIFY( CHECK(U, "\U0001F4C1") ); // folder
   VERIFY( CHECK(U, "\U0001F4C2") ); // open folder
   VERIFY( CHECK(U, "\U0001F4C4") ); // filing cabient
+
+  VERIFY( path(u8"\U0001D11E").u32string() == U"\U0001D11E" ); // G Clef
 }
 
 int

commit 68e4bb1e6de6ee0a8e9d6a16a9d246e265261f48
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 13 02:19:48 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b130beac02a..da7e2171bfa 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230712
+20230713
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 7c0497dc46f..7adbf30acc5 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,12 @@
+2023-07-12  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-06-29  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/110468
+	* init.cc (maybe_instantiate_nsdmi_init): Mask out all
+	tsubst flags except for tf_warning_or_error.
+
 2023-05-17  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7069f3f2029..f276cc6563b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2023-07-12  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-06-29  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/110468
+	* g++.dg/cpp0x/noexcept79.C: New test.
+
 2023-07-08  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 7dff8934305..d861f59a62a 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,14 @@
+2023-07-12  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2023-07-12  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/95048
+	* testsuite/27_io/filesystem/path/construct/95048.cc: Check
+	conversions to wide strings.
+	* testsuite/experimental/filesystem/path/construct/95048.cc:
+	Likewise.
+
 2023-07-06  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 4520e2dbc73262028ad556f732871565101ef615
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu Jul 13 18:32:15 2023

    alpha: Fix computation mode in alpha_emit_set_long_cost [PR106966]
    
            PR target/106966
    
    gcc/ChangeLog:
    
            * config/alpha/alpha.cc (alpha_emit_set_long_const):
            Always use DImode when constructing long const.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/alpha/pr106966.c: New test.
    
    (cherry picked from commit 337649c1660211db733c1ba34ae260b8c66a3578)

diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc
index 0a85e66fa89..06c8356fc4e 100644
--- a/gcc/config/alpha/alpha.cc
+++ b/gcc/config/alpha/alpha.cc
@@ -2070,6 +2070,8 @@ static rtx
 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1)
 {
   HOST_WIDE_INT d1, d2, d3, d4;
+  machine_mode mode = GET_MODE (target);
+  rtx orig_target = target;
 
   /* Decompose the entire word */
 
@@ -2082,6 +2084,9 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1)
   d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
   gcc_assert (c1 == d4);
 
+  if (mode != DImode)
+    target = gen_lowpart (DImode, target);
+
   /* Construct the high word */
   if (d4)
     {
@@ -2101,7 +2106,7 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1)
   if (d1)
     emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
 
-  return target;
+  return orig_target;
 }
 
 /* Given an integral CONST_INT or CONST_VECTOR, return the low 64 bits.  */
diff --git a/gcc/testsuite/gcc.target/alpha/pr106966.c b/gcc/testsuite/gcc.target/alpha/pr106966.c
new file mode 100644
index 00000000000..7145c2096c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/alpha/pr106966.c
@@ -0,0 +1,13 @@
+/* PR target/106906 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbuild-constants" } */
+
+void
+do_console (unsigned short *vga)
+{
+  vga[0] = 'H';
+  vga[1] = 'e';
+  vga[2] = 'l';
+  vga[3] = 'l';
+  vga[4] = 'o';
+}

commit 762b7e42394b05b0616613ff84a53c62fd1f9b88
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 14 02:22:48 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 05202840a12..85fc290ebaf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2023-07-13  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backported from master:
+	2023-07-13  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/106966
+	* config/alpha/alpha.cc (alpha_emit_set_long_const):
+	Always use DImode when constructing long const.
+
 2023-07-08  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index da7e2171bfa..f1d307746c6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230713
+20230714
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f276cc6563b..7f69a3367bc 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2023-07-13  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backported from master:
+	2023-07-13  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/106966
+	* gcc.target/alpha/pr106966.c: New test.
+
 2023-07-12  Patrick Palka  <ppalka@redhat.com>
 
 	Backported from master:

commit 5f20f736c1144dd9f2ae2f99099b7f7b21a3ab4e
Author: Oleg Endo <olegendo@gcc.gnu.org>
Date:   Fri Jul 14 02:54:20 2023

    SH: Fix PR101469 peephole bug
    
    gcc/ChangeLog:
    
            PR target/101469
            * config/sh/sh.md (peephole2): Handle case where eliminated reg
            is also used by the address of the following memory operand.

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 59a7b216433..15cdfe9ac33 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -10680,6 +10680,45 @@
    && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])"
   [(const_int 0)]
 {
+  if (MEM_P (operands[3]) && reg_overlap_mentioned_p (operands[0], operands[3]))
+    {
+      // Take care when the eliminated operand[0] register is part of
+      // the destination memory address.
+      rtx addr = XEXP (operands[3], 0);
+
+      if (REG_P (addr))
+	operands[3] = replace_equiv_address (operands[3], operands[1]);
+
+      else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr, 0))
+	       && CONST_INT_P (XEXP (addr, 1))
+	       && REGNO (operands[0]) == REGNO (XEXP (addr, 0)))
+	operands[3] = replace_equiv_address (operands[3],
+			    gen_rtx_PLUS (SImode, operands[1], XEXP (addr, 1)));
+
+      else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr, 0))
+	       && REG_P (XEXP (addr, 1)))
+        {
+          // register + register address  @(R0, Rn)
+          // can change only the Rn in the address, not R0.
+          if (REGNO (operands[0]) == REGNO (XEXP (addr, 0))
+	      && REGNO (XEXP (addr, 0)) != 0)
+	    {
+	      operands[3] = replace_equiv_address (operands[3],
+			    gen_rtx_PLUS (SImode, operands[1], XEXP (addr, 1)));
+	    }
+          else if (REGNO (operands[0]) == REGNO (XEXP (addr, 1))
+		   && REGNO (XEXP (addr, 1)) != 0)
+            {
+	      operands[3] = replace_equiv_address (operands[3],
+			    gen_rtx_PLUS (SImode, XEXP (addr, 0), operands[1]));
+            }
+          else
+            FAIL;
+        }
+      else
+        FAIL;
+    }
+
   emit_insn (gen_addsi3 (operands[1], operands[1], operands[2]));
   sh_peephole_emit_move_insn (operands[3], operands[1]);
 })

commit 995c717500c368c5aec7889dfa047cff7cb0139b
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Tue Jul 11 21:21:25 2023

    Fortran: formal symbol attributes for intrinsic procedures [PR110288]
    
    gcc/fortran/ChangeLog:
    
            PR fortran/110288
            * symbol.cc (gfc_copy_formal_args_intr): When deriving the formal
            argument attributes from the actual ones for intrinsic procedure
            calls, take special care of CHARACTER arguments that we do not
            wrongly treat them formally as deferred-length.
    
    gcc/testsuite/ChangeLog:
    
            PR fortran/110288
            * gfortran.dg/findloc_10.f90: New test.
    
    (cherry picked from commit 3b2c523ae31b68fc3b8363b458a55eec53a44365)

diff --git a/gcc/fortran/symbol.cc b/gcc/fortran/symbol.cc
index af5a2e41bf5..e7de5a8f525 100644
--- a/gcc/fortran/symbol.cc
+++ b/gcc/fortran/symbol.cc
@@ -4719,6 +4719,13 @@ gfc_copy_formal_args_intr (gfc_symbol *dest, gfc_intrinsic_sym *src,
       formal_arg->sym->attr.flavor = FL_VARIABLE;
       formal_arg->sym->attr.dummy = 1;
 
+      /* Do not treat an actual deferred-length character argument wrongly
+	 as template for the formal argument.  */
+      if (formal_arg->sym->ts.type == BT_CHARACTER
+	  && !(formal_arg->sym->attr.allocatable
+	       || formal_arg->sym->attr.pointer))
+	formal_arg->sym->ts.deferred = false;
+
       if (formal_arg->sym->ts.type == BT_CHARACTER)
 	formal_arg->sym->ts.u.cl = gfc_new_charlen (gfc_current_ns, NULL);
 
diff --git a/gcc/testsuite/gfortran.dg/findloc_10.f90 b/gcc/testsuite/gfortran.dg/findloc_10.f90
new file mode 100644
index 00000000000..4d5ecd2306a
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/findloc_10.f90
@@ -0,0 +1,13 @@
+! { dg-do run }
+! { dg-options "-fdump-tree-original" }
+! PR fortran/110288 - FINDLOC and deferred-length character arguments
+
+program test
+  character(len=:), allocatable :: array(:)
+  character(len=:), allocatable :: value
+  array = ["bb", "aa"]
+  value = "aa"
+  if (findloc (array, value, dim=1) /= 2) stop 1
+end program test
+
+! { dg-final { scan-tree-dump "_gfortran_findloc2_s1 \\(.*, \\.array, \\.value\\)" "original" } }

commit eeb8e9a36d7aa9bc4ac8b0d7abe1e84e9afc4250
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri Jul 14 11:46:22 2023

    cprop: Do not set REG_EQUAL note when simplifying paradoxical subreg [PR110206]
    
    cprop1 pass does not consider paradoxical subreg and for (insn 22) claims
    that it equals 8 elements of HImodeby setting REG_EQUAL note:
    
    (insn 21 19 22 4 (set (reg:V4QI 98)
            (mem/u/c:V4QI (symbol_ref/u:DI ("*.LC1") [flags 0x2]) [0  S4 A32])) "pr110206.c":12:42 1530 {*movv4qi_internal}
         (expr_list:REG_EQUAL (const_vector:V4QI [
                    (const_int -52 [0xffffffffffffffcc]) repeated x4
                ])
            (nil)))
    (insn 22 21 23 4 (set (reg:V8HI 100)
            (zero_extend:V8HI (vec_select:V8QI (subreg:V16QI (reg:V4QI 98) 0)
                    (parallel [
                            (const_int 0 [0])
                            (const_int 1 [0x1])
                            (const_int 2 [0x2])
                            (const_int 3 [0x3])
                            (const_int 4 [0x4])
                            (const_int 5 [0x5])
                            (const_int 6 [0x6])
                            (const_int 7 [0x7])
                        ])))) "pr110206.c":12:42 7471 {sse4_1_zero_extendv8qiv8hi2}
         (expr_list:REG_EQUAL (const_vector:V8HI [
                    (const_int 204 [0xcc]) repeated x8
                ])
            (expr_list:REG_DEAD (reg:V4QI 98)
                (nil))))
    
    We rely on the "undefined" vals to have a specific value (from the earlier
    REG_EQUAL note) but actual code generation doesn't ensure this (it doesn't
    need to).  That said, the issue isn't the constant folding per-se but that
    we do not actually constant fold but register an equality that doesn't hold.
    
            PR target/110206
    
    gcc/ChangeLog:
    
            * fwprop.cc (contains_paradoxical_subreg_p): Move to ...
            * rtlanal.cc (contains_paradoxical_subreg_p): ... here.
            * rtlanal.h (contains_paradoxical_subreg_p): Add prototype.
            * cprop.cc (try_replace_reg): Do not set REG_EQUAL note
            when the original source contains a paradoxical subreg.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/pr110206.c: New test.
    
    (cherry picked from commit 1815e313a8fb519a77c94a908eb6dafc4ce51ffe)

diff --git a/gcc/cprop.cc b/gcc/cprop.cc
index 2a99553a5a5..f049e6df857 100644
--- a/gcc/cprop.cc
+++ b/gcc/cprop.cc
@@ -22,6 +22,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "coretypes.h"
 #include "backend.h"
 #include "rtl.h"
+#include "rtlanal.h"
 #include "cfghooks.h"
 #include "df.h"
 #include "insn-config.h"
@@ -795,7 +796,8 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
       /* If we've failed perform the replacement, have a single SET to
 	 a REG destination and don't yet have a note, add a REG_EQUAL note
 	 to not lose information.  */
-      if (!success && note == 0 && set != 0 && REG_P (SET_DEST (set)))
+      if (!success && note == 0 && set != 0 && REG_P (SET_DEST (set))
+	  && !contains_paradoxical_subreg_p (SET_SRC (set)))
 	note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
     }
 
diff --git a/gcc/fwprop.cc b/gcc/fwprop.cc
index d12fc2f34ac..5451e663ad6 100644
--- a/gcc/fwprop.cc
+++ b/gcc/fwprop.cc
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "coretypes.h"
 #include "backend.h"
 #include "rtl.h"
+#include "rtlanal.h"
 #include "df.h"
 #include "rtl-ssa.h"
 
@@ -353,21 +354,6 @@ reg_single_def_p (rtx x)
   return REG_P (x) && crtl->ssa->single_dominating_def (REGNO (x));
 }
 
-/* Return true if X contains a paradoxical subreg.  */
-
-static bool
-contains_paradoxical_subreg_p (rtx x)
-{
-  subrtx_var_iterator::array_type array;
-  FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
-    {
-      x = *iter;
-      if (SUBREG_P (x) && paradoxical_subreg_p (x))
-	return true;
-    }
-  return false;
-}
-
 /* Try to substitute (set DEST SRC), which defines DEF, into note NOTE of
    USE_INSN.  Return the number of substitutions on success, otherwise return
    -1 and leave USE_INSN unchanged.
diff --git a/gcc/rtlanal.cc b/gcc/rtlanal.cc
index c436c640c37..78a740cb54b 100644
--- a/gcc/rtlanal.cc
+++ b/gcc/rtlanal.cc
@@ -6990,3 +6990,18 @@ vec_series_lowpart_p (machine_mode result_mode, machine_mode op_mode, rtx sel)
     }
   return false;
 }
+
+/* Return true if X contains a paradoxical subreg.  */
+
+bool
+contains_paradoxical_subreg_p (rtx x)
+{
+  subrtx_var_iterator::array_type array;
+  FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
+    {
+      x = *iter;
+      if (SUBREG_P (x) && paradoxical_subreg_p (x))
+	return true;
+    }
+  return false;
+}
diff --git a/gcc/rtlanal.h b/gcc/rtlanal.h
index 9fd84a74fc3..606d2047265 100644
--- a/gcc/rtlanal.h
+++ b/gcc/rtlanal.h
@@ -338,4 +338,6 @@ vec_series_highpart_p (machine_mode result_mode, machine_mode op_mode,
 bool
 vec_series_lowpart_p (machine_mode result_mode, machine_mode op_mode, rtx sel);
 
+bool
+contains_paradoxical_subreg_p (rtx x);
 #endif
diff --git a/gcc/testsuite/gcc.target/i386/pr110206.c b/gcc/testsuite/gcc.target/i386/pr110206.c
new file mode 100644
index 00000000000..af1455c5aa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr110206.c
@@ -0,0 +1,39 @@
+/* PR target/110206 */
+/* { dg-do run } */
+/* { dg-options "-Os -mavx512bw -mavx512vl" } */
+/* { dg-require-effective-target avx512bw } */
+/* { dg-require-effective-target avx512vl } */
+
+#define AVX512BW
+#define AVX512VL
+
+#include "avx512f-check.h"
+
+typedef unsigned char __attribute__((__vector_size__ (4))) U;
+typedef unsigned char __attribute__((__vector_size__ (8))) V;
+typedef unsigned short u16;
+
+V g;
+
+void
+__attribute__((noinline))
+foo (U u, u16 c, V *r)
+{
+  if (!c)
+    abort ();
+  V x = __builtin_shufflevector (u, (204 >> u), 7, 0, 5, 1, 3, 5, 0, 2);
+  V y = __builtin_shufflevector (g, (V) { }, 7, 6, 6, 7, 2, 6, 3, 5);
+  V z = __builtin_shufflevector (y, 204 * x, 3, 9, 8, 1, 4, 6, 14, 5);
+  *r = z;
+}
+
+static void test_256 (void) { };
+
+static void
+test_128 (void)
+{
+  V r;
+  foo ((U){4}, 5, &r);
+  if (r[6] != 0x30)
+    abort();
+}

commit 68af3efa63ce6f308bf0d9f9638d0b978b09b299
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 15 02:19:37 2023

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 85fc290ebaf..4130f2b70bb 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2023-07-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backported from master:
+	2023-07-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/110206
+	* fwprop.cc (contains_paradoxical_subreg_p): Move to ...
+	* rtlanal.cc (contains_paradoxical_subreg_p): ... here.
+	* rtlanal.h (contains_paradoxical_subreg_p): Add prototype.
+	* cprop.cc (try_replace_reg): Do not set REG_EQUAL note
+	when the original source contains a paradoxical subreg.
+
+2023-07-14  Oleg Endo  <olegendo@gcc.gnu.org>
+
+	PR target/101469
+	* config/sh/sh.md (peephole2): Handle case where eliminated reg
+	is also	used by the address of the following memory operand.
+
 2023-07-13  Uros Bizjak  <ubizjak@gmail.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f1d307746c6..fc4e8edc1af 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230714
+20230715
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index e9057cdf00b..3f05b8968c9 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,14 @@
+2023-07-14  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-07-11  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/110288
+	* symbol.cc (gfc_copy_formal_args_intr): When deriving the formal
+	argument attributes from the actual ones for intrinsic procedure
+	calls, take special care of CHARACTER arguments that we do not
+	wrongly treat them formally as deferred-length.
+
 2023-07-08  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7f69a3367bc..3a5273d564d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2023-07-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	Backported from master:
+	2023-07-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/110206
+	* gcc.target/i386/pr110206.c: New test.
+
+2023-07-14  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-07-11  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/110288
+	* gfortran.dg/findloc_10.f90: New test.
+
 2023-07-13  Uros Bizjak  <ubizjak@gmail.com>
 
 	Backported from master:

commit 57dd3d8c1bca75354fc514c6a1b0ec051c180a52
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 16 02:19:17 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index fc4e8edc1af..d452cda0b47 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230715
+20230716

commit 0b84c6cc6a7909c114146c7751e2094fe9d4296f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 17 02:19:20 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d452cda0b47..4a97c3e4719 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230716
+20230717

commit 4c3a74323830a9f9bc6fe87e8fee2d2f88f734e1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 18 02:19:26 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4a97c3e4719..5e9edc95482 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230717
+20230718

commit ca77af3efd75b1b86ba5ab4ce350edb78f021c37
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 19 02:19:53 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5e9edc95482..2292579c26f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230718
+20230719

commit cda68d77b2835b67fc80abe7ec4d71de1065bb21
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Tue Jul 11 16:57:33 2023

    testsuite: Require vectors of doubles for pr97428.c
    
    The pr97428.c test assumes support for vectors of doubles, but some
    targets only support vectors of floats, causing this test to fail with
    such targets.  Limit this test to targets that support vectors of
    doubles then.
    
            gcc/testsuite/
            * gcc.dg/vect/pr97428.c: Limit to `vect_double' targets.
    
    (cherry picked from commit 5d9fc2aced3a2128527afd4a627424542f238471)

diff --git a/gcc/testsuite/gcc.dg/vect/pr97428.c b/gcc/testsuite/gcc.dg/vect/pr97428.c
index bbd743a76c4..ad6416096aa 100644
--- a/gcc/testsuite/gcc.dg/vect/pr97428.c
+++ b/gcc/testsuite/gcc.dg/vect/pr97428.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-require-effective-target vect_double } */
 
 typedef struct { double re, im; } dcmlx_t;
 typedef struct { double re[4], im[4]; } dcmlx4_t;

commit 506cb58756290284351e628a98871b341b888e54
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 20 02:19:50 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2292579c26f..4b8414aa23f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230719
+20230720
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3a5273d564d..a3f050e0a2a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2023-07-19  Maciej W. Rozycki  <macro@embecosm.com>
+
+	Backported from master:
+	2023-07-11  Maciej W. Rozycki  <macro@embecosm.com>
+
+	* gcc.dg/vect/pr97428.c: Limit to `vect_double' targets.
+
 2023-07-14  Uros Bizjak  <ubizjak@gmail.com>
 
 	Backported from master:

commit 5279d2db0c4ace4f8d311d9c875d51a0fe7b40ea
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Sun Jul 16 22:17:27 2023

    Fortran: intrinsics and deferred-length character arguments [PR95947,PR110658]
    
    gcc/fortran/ChangeLog:
    
            PR fortran/95947
            PR fortran/110658
            * trans-expr.cc (gfc_conv_procedure_call): For intrinsic procedures
            whose result characteristics depends on the first argument and which
            can be of type character, the character length will not be deferred.
    
    gcc/testsuite/ChangeLog:
    
            PR fortran/95947
            PR fortran/110658
            * gfortran.dg/deferred_character_37.f90: New test.
    
    (cherry picked from commit 95ddd2659849a904509067ec3a2770135149a722)

diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 057cb8a3041..27b34984705 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -7428,7 +7428,12 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym,
 	     (and other intrinsics?) and dummy functions.  In the case of SPREAD,
 	     we take the character length of the first argument for the result.
 	     For dummies, we have to look through the formal argument list for
-	     this function and use the character length found there.*/
+	     this function and use the character length found there.
+	     Likewise, we handle the case of deferred-length character dummy
+	     arguments to intrinsics that determine the characteristics of
+	     the result, which cannot be deferred-length.  */
+	  if (expr->value.function.isym)
+	    ts.deferred = false;
 	  if (ts.deferred)
 	    cl.backend_decl = gfc_create_var (gfc_charlen_type_node, "slen");
 	  else if (!sym->attr.dummy)
diff --git a/gcc/testsuite/gfortran.dg/deferred_character_37.f90 b/gcc/testsuite/gfortran.dg/deferred_character_37.f90
new file mode 100644
index 00000000000..8a5a8c5daf8
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/deferred_character_37.f90
@@ -0,0 +1,88 @@
+! { dg-do run }
+! PR fortran/95947
+! PR fortran/110658
+!
+! Test deferred-length character arguments to selected intrinsics
+! that may return a character result of same length as first argument:
+! CSHIFT, EOSHIFT, MAXVAL, MERGE, MINVAL, PACK, SPREAD, TRANSPOSE, UNPACK
+
+program p
+  implicit none
+  call pr95947 ()
+  call pr110658 ()
+  call s ()
+
+contains
+
+  subroutine pr95947
+    character(len=:), allocatable :: m(:)
+
+    m = [ character(len=10) :: 'ape','bat','cat','dog','eel','fly','gnu']
+    m = pack (m, mask=(m(:)(2:2) == 'a'))
+
+!   print *, "m = '", m,"' ",               "; expected is ['bat','cat']"
+    if (.not. all (m == ['bat','cat'])) stop 1
+   
+!   print *, "size(m) =     ", size(m),     "; expected is 2"
+    if (size (m) /= 2) stop 2
+   
+!   print *, "len(m) =      ", len(m),      "; expected is 10"
+    if (len (m) /= 10) stop 3
+   
+!   print *, "len_trim(m) = ", len_trim(m), "; expected is 3 3"
+    if (.not. all (len_trim(m) == [3,3])) stop 4
+  end
+
+  subroutine pr110658
+    character(len=:), allocatable :: array(:), array2(:,:)
+    character(len=:), allocatable :: res, res1(:), res2(:)
+
+    array = ["bb", "aa", "cc"]
+
+    res = minval (array)
+    if (res /= "aa") stop 11
+
+    res = maxval (array, mask=[.true.,.true.,.false.])
+    if (res /= "bb") stop 12
+
+    res1 = cshift (array, 1)
+    if (any (res1 /= ["aa","cc","bb"])) stop 13
+
+    res2 = eoshift (res1, -1)
+    if (any (res2 /= ["  ", "aa", "cc"])) stop 14
+
+    res2 = pack (array, mask=[.true.,.false.,.true.])
+    if (any (res2 /= ["bb","cc"])) stop 15
+
+    res2 = unpack (res2, mask=[.true.,.false.,.true.], field="aa")
+    if (any (res2 /= array)) stop 16
+
+    res2 = merge (res2, array, [.true.,.false.,.true.])
+    if (any (res2 /= array)) stop 17
+
+    array2 = spread (array, dim=2, ncopies=2)
+    array2 = transpose (array2)
+    if (any (shape (array2) /= [2,3])) stop 18
+    if (any (array2(2,:) /= array))    stop 19
+  end
+
+  subroutine s
+    character(:), allocatable :: array1(:), array2(:)
+    array1 = ["aa","cc","bb"]
+    array2 = copy (array1)
+    if (any (array1 /= array2)) stop 20
+  end
+
+  function copy (arg) result (res)
+    character(:), allocatable :: res(:)
+    character(*), intent(in)  :: arg(:)
+    integer :: i, k, n
+    k = len (arg)
+    n = size (arg)
+    allocate (character(k) :: res(n))
+    do i = 1, n
+       res(i) = arg(i)
+    end do
+  end
+
+end

commit f7ecd7ee5120b3b43f2facf7a862882f286f1e54
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 21 02:19:33 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4b8414aa23f..0e7d73c1914 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230720
+20230721
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 3f05b8968c9..605126db43e 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,14 @@
+2023-07-20  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-07-17  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/95947
+	PR fortran/110658
+	* trans-expr.cc (gfc_conv_procedure_call): For intrinsic procedures
+	whose result characteristics depends on the first argument and which
+	can be of type character, the character length will not be deferred.
+
 2023-07-14  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a3f050e0a2a..faea7a5b471 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2023-07-20  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-07-17  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/95947
+	PR fortran/110658
+	* gfortran.dg/deferred_character_37.f90: New test.
+
 2023-07-19  Maciej W. Rozycki  <macro@embecosm.com>
 
 	Backported from master:

commit 30af83d3e086574e88d3e1003ade289d4e69c9f1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 22 02:20:37 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0e7d73c1914..05e1afb478c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230721
+20230722

commit be5dcb6f4812d328b3d99ef74af23f08caaba6fb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 23 02:19:50 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 05e1afb478c..15985d1de54 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230722
+20230723

commit 8e1ad4ad8c37743e793c603d2c682d800a37663c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 24 02:19:32 2023

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 15985d1de54..03f4ad7154f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230723
+20230724