Index: gcc/DATESTAMP =================================================================== --- gcc/DATESTAMP (.../tags/gcc_6_2_0_release) +++ gcc/DATESTAMP (.../branches/gcc-6-branch) @@ -1 +1 @@ -20160822 +20160823 Index: gcc/ChangeLog =================================================================== --- gcc/ChangeLog (.../tags/gcc_6_2_0_release) +++ gcc/ChangeLog (.../branches/gcc-6-branch) @@ -1,3 +1,44 @@ +2016-08-22 Uros Bizjak + + Backport from mainline + 2016-08-15 Uros Bizjak + + PR target/72867 + * config/i386/sse.md (3): + Emit ieee_3 + for !flag_finite_math_only or flag_signed_zeros. + (*3): Rename from + *3_finite. Do not + depend on flag_finite_math_only. + (ieee_3): + New insn pattern. + (*3): Remove. + (*ieee_smin3): Ditto. + (*ieee_smax3): Ditto. + * config/i386/mmx.md (mmx_v2sf3): Emit + mmx_ieee_v2sf3 for !flag_finite_math_only or + flag_signed_zeros. + (*mmx_v2sf3): Rename from *mmx_v2sf3_finite. Do not + depend on flag_finite_math_only. + (mmx_ieee_v2sf3): New insn pattern. + (*mmx_v2sf3): Remove. + * config/i386/subst.md (round_saeonly_mask_arg3): New subst attribute. + * config/i386/i386.c (ix86_expand_sse_fp_mimnax): Check + flag_signed_zeros instead of !flag_unsafe_math_optimizations. + +2016-08-22 Kyrylo Tkachov + + Backport from mainline + 2016-07-12 Kyrylo Tkachov + + PR middle-end/71700 + * expr.c (store_constructor): Mask sign-extended bits when widening + sub-word constructor element at the start of a word. + +2016-08-22 Richard Biener + + * BASE-VER: Set to 6.2.1. + 2016-08-22 Release Manager * GCC 6.2.0 released. Index: gcc/testsuite/gcc.target/i386/pr72867.c =================================================================== --- gcc/testsuite/gcc.target/i386/pr72867.c (.../tags/gcc_6_2_0_release) (nonexistent) +++ gcc/testsuite/gcc.target/i386/pr72867.c (.../branches/gcc-6-branch) @@ -0,0 +1,23 @@ +/* PR target/72867 */ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" +#include + +static void +sse_test (void) +{ + float nan = __builtin_nanf (""); + + __m128 x = _mm_min_ps(_mm_set1_ps(nan), _mm_set1_ps(1.0f)); + + if (x[0] != 1.0f) + abort (); + + x = _mm_min_ps(_mm_set1_ps(1.f), _mm_set1_ps(nan)); + + if (!__builtin_isnan (x[0])) + abort (); +} Index: gcc/testsuite/gcc.c-torture/execute/pr71700.c =================================================================== --- gcc/testsuite/gcc.c-torture/execute/pr71700.c (.../tags/gcc_6_2_0_release) (nonexistent) +++ gcc/testsuite/gcc.c-torture/execute/pr71700.c (.../branches/gcc-6-branch) @@ -0,0 +1,19 @@ +struct S +{ + signed f0 : 16; + unsigned f1 : 1; +}; + +int b; +static struct S c[] = {{-1, 0}, {-1, 0}}; +struct S d; + +int +main () +{ + struct S e = c[0]; + d = e; + if (d.f1 != 0) + __builtin_abort (); + return 0; +} Index: gcc/testsuite/ChangeLog =================================================================== --- gcc/testsuite/ChangeLog (.../tags/gcc_6_2_0_release) +++ gcc/testsuite/ChangeLog (.../branches/gcc-6-branch) @@ -1,3 +1,25 @@ +2016-08-22 Uros Bizjak + + Backport from mainline + 2016-08-16 Jakub Jelinek + + PR target/72867 + * gcc.target/i386/pr72867.c: Add -msse to dg-options. + + Backport from mainline + 2016-08-15 Uros Bizjak + + PR target/72867 + * gcc.target/i386/pr72867.c: New test. + +2016-08-22 Kyrylo Tkachov + + Backport from mainline + 2016-07-12 Kyrylo Tkachov + + PR middle-end/71700 + * gcc.c-torture/execute/pr71700.c: New test. + 2016-08-22 Release Manager * GCC 6.2.0 released. Index: gcc/expr.c =================================================================== --- gcc/expr.c (.../tags/gcc_6_2_0_release) +++ gcc/expr.c (.../branches/gcc-6-branch) @@ -6139,6 +6139,13 @@ type = lang_hooks.types.type_for_mode (word_mode, TYPE_UNSIGNED (type)); value = fold_convert (type, value); + /* Make sure the bits beyond the original bitsize are zero + so that we can correctly avoid extra zeroing stores in + later constructor elements. */ + tree bitsize_mask + = wide_int_to_tree (type, wi::mask (bitsize, false, + BITS_PER_WORD)); + value = fold_build2 (BIT_AND_EXPR, type, value, bitsize_mask); } if (BYTES_BIG_ENDIAN) Index: gcc/BASE-VER =================================================================== --- gcc/BASE-VER (.../tags/gcc_6_2_0_release) +++ gcc/BASE-VER (.../branches/gcc-6-branch) @@ -1 +1 @@ -6.2.0 +6.2.1 Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md (.../tags/gcc_6_2_0_release) +++ gcc/config/i386/i386.md (.../branches/gcc-6-branch) @@ -886,6 +886,14 @@ (umax "maxu") (umin "minu")]) (define_code_attr maxmin_float [(smax "max") (smin "min")]) +(define_int_iterator IEEE_MAXMIN + [UNSPEC_IEEE_MAX + UNSPEC_IEEE_MIN]) + +(define_int_attr ieee_maxmin + [(UNSPEC_IEEE_MAX "max") + (UNSPEC_IEEE_MIN "min")]) + ;; Mapping of logic operators (define_code_iterator any_logic [and ior xor]) (define_code_iterator any_or [ior xor]) @@ -17383,14 +17391,6 @@ ;; Their operands are not commutative, and thus they may be used in the ;; presence of -0.0 and NaN. -(define_int_iterator IEEE_MAXMIN - [UNSPEC_IEEE_MAX - UNSPEC_IEEE_MIN]) - -(define_int_attr ieee_maxmin - [(UNSPEC_IEEE_MAX "max") - (UNSPEC_IEEE_MIN "min")]) - (define_insn "*ieee_s3" [(set (match_operand:MODEF 0 "register_operand" "=x,v") (unspec:MODEF Index: gcc/config/i386/mmx.md =================================================================== --- gcc/config/i386/mmx.md (.../tags/gcc_6_2_0_release) +++ gcc/config/i386/mmx.md (.../branches/gcc-6-branch) @@ -296,10 +296,6 @@ (set_attr "prefix_extra" "1") (set_attr "mode" "V2SF")]) -;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX -;; isn't really correct, as those rtl operators aren't defined when -;; applied to NaNs. Hopefully the optimizers won't get too smart on us. - (define_expand "mmx_v2sf3" [(set (match_operand:V2SF 0 "register_operand") (smaxmin:V2SF @@ -307,30 +303,47 @@ (match_operand:V2SF 2 "nonimmediate_operand")))] "TARGET_3DNOW" { - if (!flag_finite_math_only) - operands[1] = force_reg (V2SFmode, operands[1]); - ix86_fixup_binary_operands_no_copy (, V2SFmode, operands); + if (!flag_finite_math_only || flag_signed_zeros) + { + operands[1] = force_reg (V2SFmode, operands[1]); + emit_insn (gen_mmx_ieee_v2sf3 + (operands[0], operands[1], operands[2])); + DONE; + } + else + ix86_fixup_binary_operands_no_copy (, V2SFmode, operands); }) -(define_insn "*mmx_v2sf3_finite" +;; These versions of the min/max patterns are intentionally ignorant of +;; their behavior wrt -0.0 and NaN (via the commutative operand mark). +;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator +;; are undefined in this condition, we're certain this is correct. + +(define_insn "*mmx_v2sf3" [(set (match_operand:V2SF 0 "register_operand" "=y") (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] - "TARGET_3DNOW && flag_finite_math_only - && ix86_binary_operator_ok (, V2SFmode, operands)" + "TARGET_3DNOW && ix86_binary_operator_ok (, V2SFmode, operands)" "pf\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "prefix_extra" "1") (set_attr "mode" "V2SF")]) -(define_insn "*mmx_v2sf3" +;; These versions of the min/max patterns implement exactly the operations +;; min = (op1 < op2 ? op1 : op2) +;; max = (!(op1 < op2) ? op1 : op2) +;; Their operands are not commutative, and thus they may be used in the +;; presence of -0.0 and NaN. + +(define_insn "mmx_ieee_v2sf3" [(set (match_operand:V2SF 0 "register_operand" "=y") - (smaxmin:V2SF - (match_operand:V2SF 1 "register_operand" "0") - (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] + (unspec:V2SF + [(match_operand:V2SF 1 "register_operand" "0") + (match_operand:V2SF 2 "nonimmediate_operand" "ym")] + IEEE_MAXMIN))] "TARGET_3DNOW" - "pf\t{%2, %0|%0, %2}" + "pf\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "prefix_extra" "1") (set_attr "mode" "V2SF")]) Index: gcc/config/i386/sse.md =================================================================== --- gcc/config/i386/sse.md (.../tags/gcc_6_2_0_release) +++ gcc/config/i386/sse.md (.../branches/gcc-6-branch) @@ -1945,10 +1945,6 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "SF")]) -;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX -;; isn't really correct, as those rtl operators aren't defined when -;; applied to NaNs. Hopefully the optimizers won't get too smart on us. - (define_expand "3" [(set (match_operand:VF 0 "register_operand") (smaxmin:VF @@ -1956,18 +1952,30 @@ (match_operand:VF 2 "")))] "TARGET_SSE && && " { - if (!flag_finite_math_only) - operands[1] = force_reg (mode, operands[1]); - ix86_fixup_binary_operands_no_copy (, mode, operands); + if (!flag_finite_math_only || flag_signed_zeros) + { + operands[1] = force_reg (mode, operands[1]); + emit_insn (gen_ieee_3 + (operands[0], operands[1], operands[2] + + )); + DONE; + } + else + ix86_fixup_binary_operands_no_copy (, mode, operands); }) -(define_insn "*3_finite" +;; These versions of the min/max patterns are intentionally ignorant of +;; their behavior wrt -0.0 and NaN (via the commutative operand mark). +;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator +;; are undefined in this condition, we're certain this is correct. + +(define_insn "*3" [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "" "%0,v") (match_operand:VF 2 "" "xBm,")))] - "TARGET_SSE && flag_finite_math_only - && ix86_binary_operator_ok (, mode, operands) + "TARGET_SSE && ix86_binary_operator_ok (, mode, operands) && && " "@ \t{%2, %0|%0, %2} @@ -1978,16 +1986,23 @@ (set_attr "prefix" "") (set_attr "mode" "")]) -(define_insn "*3" +;; These versions of the min/max patterns implement exactly the operations +;; min = (op1 < op2 ? op1 : op2) +;; max = (!(op1 < op2) ? op1 : op2) +;; Their operands are not commutative, and thus they may be used in the +;; presence of -0.0 and NaN. + +(define_insn "ieee_3" [(set (match_operand:VF 0 "register_operand" "=x,v") - (smaxmin:VF - (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "" "xBm,")))] - "TARGET_SSE && !flag_finite_math_only + (unspec:VF + [(match_operand:VF 1 "register_operand" "0,v") + (match_operand:VF 2 "" "xBm,")] + IEEE_MAXMIN))] + "TARGET_SSE && && " "@ - \t{%2, %0|%0, %2} - v\t{%2, %1, %0|%0, %1, %2}" + \t{%2, %0|%0, %2} + v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") (set_attr "btver2_sse_attr" "maxmin") @@ -2012,42 +2027,6 @@ (set_attr "prefix" "") (set_attr "mode" "")]) -;; These versions of the min/max patterns implement exactly the operations -;; min = (op1 < op2 ? op1 : op2) -;; max = (!(op1 < op2) ? op1 : op2) -;; Their operands are not commutative, and thus they may be used in the -;; presence of -0.0 and NaN. - -(define_insn "*ieee_smin3" - [(set (match_operand:VF 0 "register_operand" "=x,v") - (unspec:VF - [(match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "vector_operand" "xBm,vm")] - UNSPEC_IEEE_MIN))] - "TARGET_SSE" - "@ - min\t{%2, %0|%0, %2} - vmin\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "sseadd") - (set_attr "prefix" "orig,vex") - (set_attr "mode" "")]) - -(define_insn "*ieee_smax3" - [(set (match_operand:VF 0 "register_operand" "=x,v") - (unspec:VF - [(match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "vector_operand" "xBm,vm")] - UNSPEC_IEEE_MAX))] - "TARGET_SSE" - "@ - max\t{%2, %0|%0, %2} - vmax\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "sseadd") - (set_attr "prefix" "orig,vex") - (set_attr "mode" "")]) - (define_insn "avx_addsubv4df3" [(set (match_operand:V4DF 0 "register_operand" "=x") (vec_merge:V4DF Index: gcc/config/i386/subst.md =================================================================== --- gcc/config/i386/subst.md (.../tags/gcc_6_2_0_release) +++ gcc/config/i386/subst.md (.../branches/gcc-6-branch) @@ -161,6 +161,7 @@ (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "") (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "") (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[]") (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v") (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v") (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand") Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c (.../tags/gcc_6_2_0_release) +++ gcc/config/i386/i386.c (.../branches/gcc-6-branch) @@ -22671,7 +22671,7 @@ /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here, but MODE may be a vector mode and thus not appropriate. */ - if (!flag_finite_math_only || !flag_unsafe_math_optimizations) + if (!flag_finite_math_only || flag_signed_zeros) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX; rtvec v;